Angel Pons | 182dbde | 2020-04-02 23:49:05 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 3 | |
| 4 | #include <console/console.h> |
| 5 | #include <device/device.h> |
| 6 | #include <device/pci.h> |
Kyösti Mälkki | df128a5 | 2019-09-21 18:35:37 +0300 | [diff] [blame] | 7 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 9 | #include <device/pciexp.h> |
| 10 | #include <device/pci_ids.h> |
| 11 | #include <southbridge/intel/common/pciehp.h> |
| 12 | #include "chip.h" |
| 13 | |
| 14 | static void pci_init(struct device *dev) |
| 15 | { |
| 16 | u16 reg16; |
| 17 | u32 reg32; |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 18 | struct southbridge_intel_i82801jx_config *config = dev->chip_info; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 19 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 20 | printk(BIOS_DEBUG, "Initializing ICH10 PCIe root port.\n"); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 21 | |
| 22 | /* Enable Bus Master */ |
| 23 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 24 | reg32 |= PCI_COMMAND_MASTER; |
| 25 | pci_write_config32(dev, PCI_COMMAND, reg32); |
| 26 | |
| 27 | /* Set Cache Line Size to 0x10 */ |
| 28 | // This has no effect but the OS might expect it |
| 29 | pci_write_config8(dev, 0x0c, 0x10); |
| 30 | |
Kyösti Mälkki | df128a5 | 2019-09-21 18:35:37 +0300 | [diff] [blame] | 31 | reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); |
| 32 | reg16 &= ~PCI_BRIDGE_CTL_PARITY; |
| 33 | reg16 |= PCI_BRIDGE_CTL_NO_ISA; |
| 34 | pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 35 | |
| 36 | /* Enable IO xAPIC on this PCIe port */ |
| 37 | reg32 = pci_read_config32(dev, 0xd8); |
| 38 | reg32 |= (1 << 7); |
| 39 | pci_write_config32(dev, 0xd8, reg32); |
| 40 | |
| 41 | /* Enable Backbone Clock Gating */ |
| 42 | reg32 = pci_read_config32(dev, 0xe1); |
| 43 | reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); |
| 44 | pci_write_config32(dev, 0xe1, reg32); |
| 45 | |
| 46 | /* Set VC0 transaction class */ |
| 47 | reg32 = pci_read_config32(dev, 0x114); |
| 48 | reg32 &= 0xffffff00; |
| 49 | reg32 |= 1; |
| 50 | pci_write_config32(dev, 0x114, reg32); |
| 51 | |
| 52 | /* Mask completion timeouts */ |
| 53 | reg32 = pci_read_config32(dev, 0x148); |
| 54 | reg32 |= (1 << 14); |
| 55 | pci_write_config32(dev, 0x148, reg32); |
| 56 | |
| 57 | /* Lock R/WO Correctable Error Mask. */ |
| 58 | pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); |
| 59 | |
| 60 | /* Clear errors in status registers */ |
| 61 | reg16 = pci_read_config16(dev, 0x06); |
| 62 | pci_write_config16(dev, 0x06, reg16); |
| 63 | reg16 = pci_read_config16(dev, 0x1e); |
| 64 | pci_write_config16(dev, 0x1e, reg16); |
| 65 | |
| 66 | /* Get configured ASPM state */ |
| 67 | const enum aspm_type apmc = pci_read_config32(dev, 0x50) & 3; |
| 68 | |
| 69 | /* If both L0s and L1 enabled then set root port 0xE8[1]=1 */ |
| 70 | if (apmc == PCIE_ASPM_BOTH) { |
| 71 | reg32 = pci_read_config32(dev, 0xe8); |
| 72 | reg32 |= (1 << 1); |
| 73 | pci_write_config32(dev, 0xe8, reg32); |
| 74 | } |
| 75 | |
| 76 | /* Enable expresscard hotplug events. */ |
| 77 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 78 | pci_write_config32(dev, 0xd8, |
| 79 | pci_read_config32(dev, 0xd8) |
| 80 | | (1 << 30)); |
| 81 | pci_write_config16(dev, 0x42, 0x142); |
| 82 | } |
| 83 | } |
| 84 | |
Elyes HAOUAS | 1a8c1df | 2018-05-13 13:36:44 +0200 | [diff] [blame] | 85 | static void pch_pciexp_scan_bridge(struct device *dev) |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 86 | { |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 87 | struct southbridge_intel_i82801jx_config *config = dev->chip_info; |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 88 | |
| 89 | /* Normal PCIe Scan */ |
| 90 | pciexp_scan_bridge(dev); |
| 91 | |
| 92 | if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { |
| 93 | intel_acpi_pcie_hotplug_scan_slot(dev->link_list); |
| 94 | } |
| 95 | } |
| 96 | |
| 97 | static struct pci_operations pci_ops = { |
Subrata Banik | 15ccbf0 | 2019-03-20 15:09:44 +0530 | [diff] [blame] | 98 | .set_subsystem = pci_dev_set_subsystem, |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | static struct device_operations device_ops = { |
| 102 | .read_resources = pci_bus_read_resources, |
| 103 | .set_resources = pci_dev_set_resources, |
| 104 | .enable_resources = pci_bus_enable_resources, |
| 105 | .init = pci_init, |
| 106 | .scan_bus = pch_pciexp_scan_bridge, |
| 107 | .ops_pci = &pci_ops, |
| 108 | }; |
| 109 | |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 110 | /* 82801lJx, ICH10 */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 111 | static const unsigned short pci_device_ids[] = { |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 112 | 0x3a40, /* Port 1 */ |
| 113 | 0x3a42, /* Port 2 */ |
| 114 | 0x3a44, /* Port 3 */ |
| 115 | 0x3a46, /* Port 4 */ |
| 116 | 0x3a48, /* Port 5 */ |
| 117 | 0x3a4a, /* Port 6 */ |
| 118 | |
| 119 | 0x3a70, /* Port 1 */ |
| 120 | 0x3a72, /* Port 2 */ |
| 121 | 0x3a74, /* Port 3 */ |
| 122 | 0x3a76, /* Port 4 */ |
| 123 | 0x3a78, /* Port 5 */ |
| 124 | 0x3a7a, /* Port 6 */ |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 125 | 0 |
| 126 | }; |
Arthur Heymans | 349e085 | 2017-04-09 20:48:37 +0200 | [diff] [blame] | 127 | |
| 128 | static const struct pci_driver ich10_pcie __pci_driver = { |
Arthur Heymans | 7b9c139 | 2017-04-09 20:40:39 +0200 | [diff] [blame] | 129 | .ops = &device_ops, |
| 130 | .vendor = PCI_VENDOR_ID_INTEL, |
| 131 | .devices = pci_device_ids, |
| 132 | }; |