soc/intel/xeon_sp: Enable build for IO Margining
This commit enables the build for IO Margining, ensuring that ASPM is
disabled and certain FSP knobs are adjusted in coreboot as below
1. Enable DFXEnable
2. Disable PcieGlobalAspm
3. Disable KtiLinkL1En & KtiLinkL0pEn
Since the FSP UPD does not provide all the necessary knobs for IO
Margining, the following settings need to be applied during the FSP
build process:
1. Enable PcdBiosDfxKnobEnabled
2. Disable PchDmiAspm
3. Enable SataTestMode
4. Enable WmphyMargining
5. Disable IioErrorEn
TEST=Build for IBM sbp1 board.
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 4db0529..308ec2d 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -173,4 +173,13 @@
endif # INTEL_TXT
+config ENABLE_IO_MARGINING
+ bool "Enable IO Margining"
+ default n
+ depends on !PCIEXP_ASPM
+ help
+ Enable support for I/O margining. This is mutually exclusive with
+ ASPM. This option is intended for debugging and validation and
+ should normally be disabled.
+
endif