treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index bccd455..d3a2841 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -434,7 +434,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 88ae228..2a056a2 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -466,7 +466,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 2e9022f..654c6e3 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -454,7 +454,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 322e9f3..f7aae1c 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -490,7 +490,7 @@
/*
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
- * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
+ * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is
* currently selected partition.
diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c
index 27b23f1..8bc45e5 100644
--- a/src/soc/rockchip/rk3399/spi_bitbang.c
+++ b/src/soc/rockchip/rk3399/spi_bitbang.c
@@ -46,7 +46,7 @@
gpio_set(slave->cs, value);
}
-/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */
+/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
static const struct rockchip_bitbang_slave slaves[] = {
[0] = {
.ops = { get_miso, set_mosi, set_clk, set_cs },