treewide: Unify Google branding
Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
diff --git a/src/acpi/dsdt_top.asl b/src/acpi/dsdt_top.asl
index b8be798..4fbbec5 100644
--- a/src/acpi/dsdt_top.asl
+++ b/src/acpi/dsdt_top.asl
@@ -3,7 +3,7 @@
#include <acpi/acpigen_extern.asl>
#if CONFIG(CHROMEOS_NVS)
-/* Chrome OS specific */
+/* ChromeOS specific */
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
#endif
diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h
index 35a42e6..44f1051 100644
--- a/src/commonlib/bsd/include/commonlib/bsd/elog.h
+++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h
@@ -203,7 +203,7 @@
uint32_t instance;
} __packed;
-/* Chrome OS related events */
+/* ChromeOS related events */
#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1
#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
@@ -305,7 +305,7 @@
#define ELOG_TYPE_MI_HRPC 0xb4
#define ELOG_TYPE_MI_HR 0xb5
-/* Chrome OS diagnostics-related events */
+/* ChromeOS diagnostics-related events */
#define ELOG_TYPE_CROS_DIAGNOSTICS 0xb6
#define ELOG_CROS_LAUNCH_DIAGNOSTICS 0x01
diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h
index 67b9656..bc2152e 100644
--- a/src/commonlib/include/commonlib/timestamp_serialized.h
+++ b/src/commonlib/include/commonlib/timestamp_serialized.h
@@ -165,7 +165,7 @@
TS_KERNEL_START = 1101,
TS_KERNEL_DECOMPRESSION = 1102,
- /* 1200-1300: Chrome OS Hypervisor */
+ /* 1200-1300: ChromeOS Hypervisor */
TS_CRHV_BOOT = 1200,
TS_CRHV_PLATFORM_INIT = 1201,
TS_CRHV_SERVICES_STARTED = 1202,
@@ -247,10 +247,10 @@
TS_NAME_DEF(TS_EC_HASH_READY, 0, "EC vboot hash ready"),
TS_NAME_DEF(TS_EC_POWER_LIMIT_WAIT, 0, "waiting for EC to allow higher power draw"),
TS_NAME_DEF(TS_EC_SYNC_END, 0, "finished EC software sync"),
- TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load Chrome OS VPD"),
+ TS_NAME_DEF(TS_COPYVPD_START, TS_COPYVPD_RW_END, "starting to load ChromeOS VPD"),
TS_NAME_DEF(TS_COPYVPD_RO_END, TS_COPYVPD_RW_END,
- "finished loading Chrome OS VPD (RO)"),
- TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading Chrome OS VPD (RW)"),
+ "finished loading ChromeOS VPD (RO)"),
+ TS_NAME_DEF(TS_COPYVPD_RW_END, 0, "finished loading ChromeOS VPD (RW)"),
TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_START, TS_TPM_ENABLE_UPDATE_END,
"started TPM enable update"),
TS_NAME_DEF(TS_TPM_ENABLE_UPDATE_END, 0, "finished TPM enable update"),
@@ -344,7 +344,7 @@
TS_NAME_DEF(TS_KERNEL_START, 0, "jumping to kernel"),
TS_NAME_DEF(TS_KERNEL_DECOMPRESSION, 0, "starting kernel decompression/relocation"),
- /* Chrome OS hypervisor */
+ /* ChromeOS hypervisor */
TS_NAME_DEF(TS_CRHV_BOOT, 0, "hypervisor boot finished"),
TS_NAME_DEF(TS_CRHV_PLATFORM_INIT, 0, "hypervisor platform initialized"),
TS_NAME_DEF(TS_CRHV_SERVICES_STARTED, 0, "hypervisor services started"),
diff --git a/src/drivers/camera/Kconfig b/src/drivers/camera/Kconfig
index 1c0c0a3..4956ca2 100644
--- a/src/drivers/camera/Kconfig
+++ b/src/drivers/camera/Kconfig
@@ -2,6 +2,6 @@
bool
default n
help
- Camera with identifiers following Chrome OS Camera Info. The info is
+ Camera with identifiers following ChromeOS Camera Info. The info is
usually available on MIPI camera EEPROM for identifying correct
drivers and config.
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index d6778b0..f7aaed4 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -42,7 +42,7 @@
/*
* Save MRC Data to CBMEM. By always saving the data this forces
- * a retrain after a trip through Chrome OS recovery path. The
+ * a retrain after a trip through ChromeOS recovery path. The
* code which saves the data to flash doesn't write if the latest
* training data matches this one.
*/
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 4bb0d65..1a4dcdb 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -125,9 +125,9 @@
config EC_GOOGLE_CHROMEEC_RTC
depends on EC_GOOGLE_CHROMEEC
- bool "Enable Chrome OS EC RTC"
+ bool "Enable ChromeOS EC RTC"
help
- Enable support for the real-time clock on the Chrome OS EC. This
+ Enable support for the real-time clock on the ChromeOS EC. This
uses the EC_CMD_RTC_GET_VALUE command to read the current time.
choice
@@ -194,7 +194,7 @@
depends on EC_GOOGLE_CHROMEEC && VBOOT
bool
help
- Enable support for Chrome OS mode switches provided by the Chrome OS
+ Enable support for ChromeOS mode switches provided by the ChromeOS
EC.
config EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
index 0620e09..84afa17 100644
--- a/src/ec/google/chromeec/acpi/superio.asl
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Chrome OS Embedded Controller interface
+ * ChromeOS Embedded Controller interface
*
* Constants that should be defined:
*
diff --git a/src/ec/google/chromeec/ec_message.h b/src/ec/google/chromeec/ec_message.h
index f074ae8..4423bd8 100644
--- a/src/ec/google/chromeec/ec_message.h
+++ b/src/ec/google/chromeec/ec_message.h
@@ -1,5 +1,5 @@
/*
- * Chromium OS Matrix Keyboard Message Protocol definitions
+ * ChromiumOS Matrix Keyboard Message Protocol definitions
*/
/* SPDX-License-Identifier: GPL-2.0-or-later */
@@ -9,7 +9,7 @@
/*
* Command interface between EC and AP, for LPC, I2C and SPI interfaces.
*
- * This is copied from the Chromium OS Open Source Embedded Controller code.
+ * This is copied from the ChromiumOS Open Source Embedded Controller code.
*/
enum {
/* The header byte, which follows the preamble */
diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd
index 7194632..bb2a95c 100644
--- a/src/mainboard/google/asurada/chromeos.fmd
+++ b/src/mainboard/google/asurada/chromeos.fmd
@@ -1,4 +1,4 @@
-# Firmware Layout Description for Chrome OS.
+# Firmware Layout Description for ChromeOS.
#
# The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig
index b985be2..228aecd 100644
--- a/src/mainboard/google/brya/Kconfig
+++ b/src/mainboard/google/brya/Kconfig
@@ -97,7 +97,7 @@
select HAS_RECOVERY_MRC_CACHE
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl
index de3337f..ab4d210 100644
--- a/src/mainboard/google/brya/dsdt.asl
+++ b/src/mainboard/google/brya/dsdt.asl
@@ -36,7 +36,7 @@
/* Chipset specific sleep states */
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/brya/variants/anahera/overridetree.cb b/src/mainboard/google/brya/variants/anahera/overridetree.cb
index 48a1fdd..e5c2e96 100644
--- a/src/mainboard/google/brya/variants/anahera/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera/overridetree.cb
@@ -79,7 +79,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
index cac7299..63fb2a9 100644
--- a/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/anahera4es/overridetree.cb
@@ -71,7 +71,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/brya0/overridetree.cb b/src/mainboard/google/brya/variants/brya0/overridetree.cb
index a944103..6ac469a 100644
--- a/src/mainboard/google/brya/variants/brya0/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya0/overridetree.cb
@@ -570,7 +570,7 @@
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/brya4es/overridetree.cb b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
index 9d9233b..eed5777 100644
--- a/src/mainboard/google/brya/variants/brya4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/brya4es/overridetree.cb
@@ -571,7 +571,7 @@
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb
index 4d7d6a5..3b92b63 100644
--- a/src/mainboard/google/brya/variants/redrix/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb
@@ -99,7 +99,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
index 9a0eb1f..60eb8a3 100644
--- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb
@@ -85,7 +85,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
index 6f0eb21..3280b4b 100644
--- a/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/skolas4es/overridetree.cb
@@ -570,7 +570,7 @@
end
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb
index 5a964c6..9a4de93 100644
--- a/src/mainboard/google/brya/variants/taeko/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb
@@ -416,7 +416,7 @@
device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
index f1074de..3ec57e4 100644
--- a/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
+++ b/src/mainboard/google/brya/variants/taeko4es/overridetree.cb
@@ -320,7 +320,7 @@
device ref i2c2 on
chip drivers/i2c/generic
register "hid" = ""GOOG0020""
- register "desc" = ""Chrome OS HPS""
+ register "desc" = ""ChromeOS HPS""
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" # EN_HPS_PWR
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E3_IRQ)" # HPS_INT_ODL
# HPS uses I2C addresses 0x30 and 0x51.
diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb
index 903b67f..d8ef5096 100644
--- a/src/mainboard/google/brya/variants/vell/overridetree.cb
+++ b/src/mainboard/google/brya/variants/vell/overridetree.cb
@@ -94,7 +94,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/cherry/chromeos.fmd b/src/mainboard/google/cherry/chromeos.fmd
index 7194632..bb2a95c 100644
--- a/src/mainboard/google/cherry/chromeos.fmd
+++ b/src/mainboard/google/cherry/chromeos.fmd
@@ -1,4 +1,4 @@
-# Firmware Layout Description for Chrome OS.
+# Firmware Layout Description for ChromeOS.
#
# The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
diff --git a/src/mainboard/google/corsola/chromeos.fmd b/src/mainboard/google/corsola/chromeos.fmd
index a8c4dfe..5b2234d 100644
--- a/src/mainboard/google/corsola/chromeos.fmd
+++ b/src/mainboard/google/corsola/chromeos.fmd
@@ -1,4 +1,4 @@
-# Firmware Layout Description for Chrome OS.
+# Firmware Layout Description for ChromeOS.
#
# The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig
index 396347d..84626ef 100644
--- a/src/mainboard/google/dedede/Kconfig
+++ b/src/mainboard/google/dedede/Kconfig
@@ -65,7 +65,7 @@
select VBOOT_LID_SWITCH
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select SAR_ENABLE
diff --git a/src/mainboard/google/dedede/dsdt.asl b/src/mainboard/google/dedede/dsdt.asl
index f88e2df..7b6066e 100644
--- a/src/mainboard/google/dedede/dsdt.asl
+++ b/src/mainboard/google/dedede/dsdt.asl
@@ -37,7 +37,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/drallion/Kconfig b/src/mainboard/google/drallion/Kconfig
index 40afdf4..916a235 100644
--- a/src/mainboard/google/drallion/Kconfig
+++ b/src/mainboard/google/drallion/Kconfig
@@ -39,7 +39,7 @@
select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/drallion/dsdt.asl b/src/mainboard/google/drallion/dsdt.asl
index 5556c98..62bed72 100644
--- a/src/mainboard/google/drallion/dsdt.asl
+++ b/src/mainboard/google/drallion/dsdt.asl
@@ -33,7 +33,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/eve/dsdt.asl b/src/mainboard/google/eve/dsdt.asl
index 357f3bf..a42e9de 100644
--- a/src/mainboard/google/eve/dsdt.asl
+++ b/src/mainboard/google/eve/dsdt.asl
@@ -34,7 +34,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/fizz/dsdt.asl b/src/mainboard/google/fizz/dsdt.asl
index 01e94f2..287e426 100644
--- a/src/mainboard/google/fizz/dsdt.asl
+++ b/src/mainboard/google/fizz/dsdt.asl
@@ -33,7 +33,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/guybrush/dsdt.asl b/src/mainboard/google/guybrush/dsdt.asl
index 9579ae3..6c208cf 100644
--- a/src/mainboard/google/guybrush/dsdt.asl
+++ b/src/mainboard/google/guybrush/dsdt.asl
@@ -15,7 +15,7 @@
#include <acpi/dsdt_top.asl>
#include <soc.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
index 8270b14..2fc416e 100644
--- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
+++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb
@@ -182,7 +182,7 @@
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD""
- # Use Chrome OS privacy screen _HID
+ # Use ChromeOS privacy screen _HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
register "device[0].addr" = "0x80010400"
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 749b0df..712ed06e 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -166,7 +166,7 @@
select CHROMEOS_CSE_BOARD_RESET_OVERRIDE if SOC_INTEL_CSE_LITE_SKU
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
index 022a607..dad2267 100644
--- a/src/mainboard/google/hatch/dsdt.asl
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -35,7 +35,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index be4033b..7aa4ae0 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -52,7 +52,7 @@
/* Thermal handler */
#include <variant/acpi/thermal.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/kukui/chromeos.fmd b/src/mainboard/google/kukui/chromeos.fmd
index 2635854..61d45b0 100644
--- a/src/mainboard/google/kukui/chromeos.fmd
+++ b/src/mainboard/google/kukui/chromeos.fmd
@@ -1,4 +1,4 @@
-# Firmware Layout Description for Chrome OS.
+# Firmware Layout Description for ChromeOS.
#
# The size and address of every section must be aligned to at least 4K, except:
# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections.
diff --git a/src/mainboard/google/octopus/dsdt.asl b/src/mainboard/google/octopus/dsdt.asl
index bebee41..7ae3cc8 100644
--- a/src/mainboard/google/octopus/dsdt.asl
+++ b/src/mainboard/google/octopus/dsdt.asl
@@ -32,7 +32,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl
index dbba806..950ac2e 100644
--- a/src/mainboard/google/poppy/dsdt.asl
+++ b/src/mainboard/google/poppy/dsdt.asl
@@ -41,7 +41,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index fde3975..79277c6 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -32,7 +32,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/sarien/dsdt.asl b/src/mainboard/google/sarien/dsdt.asl
index fd91f64..00def91 100644
--- a/src/mainboard/google/sarien/dsdt.asl
+++ b/src/mainboard/google/sarien/dsdt.asl
@@ -34,7 +34,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
#if CONFIG(EC_GOOGLE_WILCO)
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/skyrim/dsdt.asl b/src/mainboard/google/skyrim/dsdt.asl
index 3aec6ba..39399d8 100644
--- a/src/mainboard/google/skyrim/dsdt.asl
+++ b/src/mainboard/google/skyrim/dsdt.asl
@@ -15,7 +15,7 @@
#include <acpi/dsdt_top.asl>
#include <soc.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/google/volteer/Kconfig b/src/mainboard/google/volteer/Kconfig
index 8947cd8..926a0ca 100644
--- a/src/mainboard/google/volteer/Kconfig
+++ b/src/mainboard/google/volteer/Kconfig
@@ -140,7 +140,7 @@
default n
config CHROMEOS_WIFI_SAR
- bool "Enable SAR options for Chrome OS build"
+ bool "Enable SAR options for ChromeOS build"
depends on CHROMEOS
select DSAR_ENABLE
select GEO_SAR_ENABLE
diff --git a/src/mainboard/google/volteer/dsdt.asl b/src/mainboard/google/volteer/dsdt.asl
index 66747d1..d4e9339 100644
--- a/src/mainboard/google/volteer/dsdt.asl
+++ b/src/mainboard/google/volteer/dsdt.asl
@@ -36,7 +36,7 @@
#include "mainboard.asl"
}
- // Chrome OS Embedded Controller
+ // ChromeOS Embedded Controller
Scope (\_SB.PCI0.LPCB)
{
// ACPI code for EC SuperIO functions
diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl
index c2df9b7..e67a8dc 100644
--- a/src/mainboard/google/zork/dsdt.asl
+++ b/src/mainboard/google/zork/dsdt.asl
@@ -44,7 +44,7 @@
/* Thermal handler */
#include <variant/acpi/thermal.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/intel/adlrvp/dsdt.asl b/src/mainboard/intel/adlrvp/dsdt.asl
index 4b41b22..6449e26c 100644
--- a/src/mainboard/intel/adlrvp/dsdt.asl
+++ b/src/mainboard/intel/adlrvp/dsdt.asl
@@ -28,7 +28,7 @@
}
#if CONFIG(EC_GOOGLE_CHROMEEC)
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/intel/glkrvp/dsdt.asl b/src/mainboard/intel/glkrvp/dsdt.asl
index f4169da..bc5f999 100644
--- a/src/mainboard/intel/glkrvp/dsdt.asl
+++ b/src/mainboard/intel/glkrvp/dsdt.asl
@@ -31,7 +31,7 @@
#include <southbridge/intel/common/acpi/sleepstates.asl>
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/intel/icelake_rvp/dsdt.asl b/src/mainboard/intel/icelake_rvp/dsdt.asl
index 2097b3e..236762d 100644
--- a/src/mainboard/intel/icelake_rvp/dsdt.asl
+++ b/src/mainboard/intel/icelake_rvp/dsdt.asl
@@ -31,7 +31,7 @@
}
#if CONFIG(EC_GOOGLE_CHROMEEC)
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/intel/jasperlake_rvp/dsdt.asl b/src/mainboard/intel/jasperlake_rvp/dsdt.asl
index cebd048..dd93b43 100644
--- a/src/mainboard/intel/jasperlake_rvp/dsdt.asl
+++ b/src/mainboard/intel/jasperlake_rvp/dsdt.asl
@@ -31,7 +31,7 @@
}
#if CONFIG(EC_GOOGLE_CHROMEEC)
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
index 57324b3..3e8f6e2 100644
--- a/src/mainboard/intel/shadowmountain/dsdt.asl
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -30,7 +30,7 @@
}
}
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
// ACPI code for EC SuperIO functions
diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl
index ca1e441..785e985 100644
--- a/src/mainboard/intel/tglrvp/dsdt.asl
+++ b/src/mainboard/intel/tglrvp/dsdt.asl
@@ -33,7 +33,7 @@
}
#if CONFIG(EC_GOOGLE_CHROMEEC)
- /* Chrome OS Embedded Controller */
+ /* ChromeOS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
/* ACPI code for EC SuperIO functions */
diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig
index 06f9e93..a36510d 100644
--- a/src/security/vboot/Kconfig
+++ b/src/security/vboot/Kconfig
@@ -103,7 +103,7 @@
bool
default n
help
- When this option is enabled, the Chrome OS device leaves the
+ When this option is enabled, the ChromeOS device leaves the
developer mode as soon as recovery request is detected. This is
handy on embedded devices with limited input capabilities.
@@ -321,10 +321,10 @@
string "Hardware ID"
default ""
help
- A hardware identifier for device. On Chrome OS this is used for auto
+ A hardware identifier for device. On ChromeOS this is used for auto
update and recovery, and will be generated when manufacturing by the
factory software, in a strictly defined format.
- Leave empty to get a test-only Chrome OS HWID v2 string generated.
+ Leave empty to get a test-only ChromeOS HWID v2 string generated.
config GBB_BMPFV_FILE
string "Path to bmpfv image"
@@ -339,7 +339,7 @@
default n
config GBB_FLAG_ENABLE_ALTERNATE_OS
- bool "Allow booting a non-Chrome OS kernel if dev switch is on"
+ bool "Allow booting a non-ChromeOS kernel if dev switch is on"
default n
config GBB_FLAG_FORCE_DEV_SWITCH_ON
diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig
index bccd455..d3a2841 100644
--- a/src/soc/amd/cezanne/Kconfig
+++ b/src/soc/amd/cezanne/Kconfig
@@ -434,7 +434,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index 88ae228..2a056a2 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -466,7 +466,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/amd/sabrina/Kconfig b/src/soc/amd/sabrina/Kconfig
index 2e9022f..654c6e3 100644
--- a/src/soc/amd/sabrina/Kconfig
+++ b/src/soc/amd/sabrina/Kconfig
@@ -454,7 +454,7 @@
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
- certain Chrome OS branded parts from AMD.
+ certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex
diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h
index 322e9f3..f7aae1c 100644
--- a/src/soc/intel/common/block/include/intelblocks/cse.h
+++ b/src/soc/intel/common/block/include/intelblocks/cse.h
@@ -490,7 +490,7 @@
/*
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
- * CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
+ * CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is
* currently selected partition.
diff --git a/src/soc/rockchip/rk3399/spi_bitbang.c b/src/soc/rockchip/rk3399/spi_bitbang.c
index 27b23f1..8bc45e5 100644
--- a/src/soc/rockchip/rk3399/spi_bitbang.c
+++ b/src/soc/rockchip/rk3399/spi_bitbang.c
@@ -46,7 +46,7 @@
gpio_set(slave->cs, value);
}
-/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */
+/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
static const struct rockchip_bitbang_slave slaves[] = {
[0] = {
.ops = { get_miso, set_mosi, set_clk, set_cs },
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 32af5538..8684920 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -23,7 +23,7 @@
if CHROMEOS
config CHROMEOS_RAMOOPS
- bool "Reserve space for Chrome OS ramoops"
+ bool "Reserve space for ChromeOS ramoops"
default y
config CHROMEOS_RAMOOPS_RAM_SIZE
diff --git a/src/vendorcode/google/chromeos/acpi/amac.asl b/src/vendorcode/google/chromeos/acpi/amac.asl
index 7d614f3..18b9f28 100644
--- a/src/vendorcode/google/chromeos/acpi/amac.asl
+++ b/src/vendorcode/google/chromeos/acpi/amac.asl
@@ -11,7 +11,7 @@
* The Linux kernel implementation can be found at
* drivers/net/usb/r8152.c:vendor_mac_passthru_addr_read()
*
- * For Chrome OS, the policy which controls where the dock MAC address
+ * For ChromeOS, the policy which controls where the dock MAC address
* comes from is written into RW_VPD property "dock_passthrough":
*
* "dock_mac" or empty: Use MAC address from RO_VPD value "dock_mac"
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index 5db7867..98aa4fa 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -38,7 +38,7 @@
enum cb_err get_dsm_calibration_from_key(const char *key, uint64_t *value);
/*
- * Declaration for mainboards to use to generate ACPI-specific Chrome OS needs.
+ * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs.
*/
void chromeos_acpi_gpio_generate(void);