| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2007-2009 coresystems GmbH |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| config NORTHBRIDGE_INTEL_I945 |
| bool |
| select HAVE_DEBUG_RAM_SETUP |
| |
| config FALLBACK_VGA_BIOS_ID |
| string |
| default "8086,27a2" |
| depends on NORTHBRIDGE_INTEL_I945 |
| |
| choice |
| default I945GM |
| depends on NORTHBRIDGE_INTEL_I945 |
| help |
| Different i945 variants require slightly different setup. |
| |
| config I945GM |
| bool "i945GM (Mobile) chipset" |
| |
| config I945GC |
| bool "i945GC chipset" |
| |
| endchoice |
| |
| config CHANNEL_XOR_RANDOMIZATION |
| bool |
| default n |
| depends on NORTHBRIDGE_INTEL_I945 |
| |
| config OVERRIDE_CLOCK_DISABLE |
| bool |
| default n |
| depends on NORTHBRIDGE_INTEL_I945 |
| help |
| Usually system firmware turns off system memory clock |
| signals to unused SO-DIMM slots to reduce EMI and power |
| consumption. |
| However, some boards do not like unused clock signals to |
| be disabled. |
| |
| config MAXIMUM_SUPPORTED_FREQUENCY |
| int |
| default 0 |
| depends on NORTHBRIDGE_INTEL_I945 |
| help |
| If non-zero, this designates the maximum DDR frequency |
| the board supports, despite what the chipset should be |
| capable of. |