acpi: Change Processor ACPI Name (Intel only)
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.
Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10
FWTS does not return FAIL anymore on ACPI tests
Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/Documentation/acpi/index.md b/Documentation/acpi/index.md
index c378722..2f65e29 100644
--- a/Documentation/acpi/index.md
+++ b/Documentation/acpi/index.md
@@ -1,6 +1,9 @@
# ACPI-specific documentation
-This section contains documentation about coreboot on ACPI.
+This section contains documentation about coreboot on ACPI. coreboot dropped
+backwards support for ACPI 1.0 and is only compatible to ACPI version 2.0 and
+upwards.
+
- [SSDT UID generation](uid.md)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 810a5bb..a4e5314 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -254,11 +254,11 @@
config ACPI_CPU_STRING
string
- default "\\_PR.CP%02d"
+ default "\\_SB.CP%02d"
depends on HAVE_ACPI_TABLES
help
Sets the ACPI name string in the processor scope as written by
- the acpigen function. Default is \_PR.CPxx. Note that you need
+ the acpigen function. Default is \_SB.CPxx. Note that you need
the \ escape character in the string.
config COLLECT_TIMESTAMPS_NO_TSC
diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c
index a599b0e..26fe08f 100644
--- a/src/arch/x86/acpigen.c
+++ b/src/arch/x86/acpigen.c
@@ -340,7 +340,7 @@
void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len)
{
/*
- Processor (\_PR.CPcpuindex, cpuindex, pblock_addr, pblock_len)
+ Processor (\_SB.CPcpuindex, cpuindex, pblock_addr, pblock_len)
{
*/
char pscope[16];
@@ -376,7 +376,7 @@
{
int core_id;
- acpigen_write_method("\\_PR.CNOT", 1);
+ acpigen_write_method("\\_SB.CNOT", 1);
for (core_id = 0; core_id < number_of_cores; core_id++) {
char buffer[DEVICE_PATH_MAX];
snprintf(buffer, sizeof(buffer), CONFIG_ACPI_CPU_STRING,
diff --git a/src/cpu/intel/common/acpi/cpu.asl b/src/cpu/intel/common/acpi/cpu.asl
index 14ade7d..153527b 100644
--- a/src/cpu/intel/common/acpi/cpu.asl
+++ b/src/cpu/intel/common/acpi/cpu.asl
@@ -13,22 +13,22 @@
*/
/* These come from the dynamically created CPU SSDT */
-External (\_PR.CNOT, MethodObj)
+External (\_SB.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
- \_PR.CNOT (0x81)
+ \_SB.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
- \_PR.CNOT (0x80)
+ \_SB.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
- \_PR.CNOT (0x82)
+ \_SB.CNOT (0x82)
}
diff --git a/src/cpu/intel/haswell/acpi.c b/src/cpu/intel/haswell/acpi.c
index 282dd96..fe2add7 100644
--- a/src/cpu/intel/haswell/acpi.c
+++ b/src/cpu/intel/haswell/acpi.c
@@ -317,7 +317,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
diff --git a/src/cpu/intel/model_2065x/acpi.c b/src/cpu/intel/model_2065x/acpi.c
index af2606c..54da4e8 100644
--- a/src/cpu/intel/model_2065x/acpi.c
+++ b/src/cpu/intel/model_2065x/acpi.c
@@ -309,7 +309,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index 6066421..c31bb5e 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -312,7 +312,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 47565f4..71570b1 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -124,7 +124,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx. */
+ /* Generate processor \_SB.CPUx. */
acpigen_write_processor(
cpuID * cores_per_package + coreID - 1,
pcontrol_blk, plen);
diff --git a/src/cpu/intel/speedstep/acpi/cpu.asl b/src/cpu/intel/speedstep/acpi/cpu.asl
index 9ff3f76..2d1a47b 100644
--- a/src/cpu/intel/speedstep/acpi/cpu.asl
+++ b/src/cpu/intel/speedstep/acpi/cpu.asl
@@ -12,20 +12,20 @@
*/
/* These come from the dynamically created CPU SSDT */
-External (\_PR.CNOT, MethodObj)
-External (\_PR_.CP00, DeviceObj)
-External (\_PR_.CP00._PPC)
-External (\_PR_.CP01._PPC)
+External (\_SB.CNOT, MethodObj)
+External (\_SB_.CP00, DeviceObj)
+External (\_SB_.CP00._PPC)
+External (\_SB_.CP01._PPC)
Method (PNOT)
{
If (MPEN) {
- \_PR.CNOT (0x80) // _PPC
+ \_SB.CNOT (0x80) // _PPC
Sleep(100)
- \_PR.CNOT (0x81) // _CST
+ \_SB.CNOT (0x81) // _CST
} Else { // UP
- Notify (\_PR_.CP00, 0x80)
+ Notify (\_SB_.CP00, 0x80)
Sleep(0x64)
- Notify(\_PR_.CP00, 0x81)
+ Notify(\_SB_.CP00, 0x81)
}
}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
index 0f66413..9b792db 100644
--- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl
+++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
@@ -18,7 +18,7 @@
* re-evaluate their _PPC and _CST tables.
*/
-External (\_PR.CP00._PPC, IntObj)
+External (\_SB.CP00._PPC, IntObj)
Device (EC0)
{
@@ -146,12 +146,12 @@
And(Local0, Ones, Local0)
// Find and program number of P-States
- Store (SizeOf (\_PR.CP00._PSS), MPST)
+ Store (SizeOf (\_SB.CP00._PSS), MPST)
Store ("Programming number of P-states: ", Debug)
Store (MPST, Debug)
// Find and program the current P-State
- Store(\_PR.CP00._PPC, NPST)
+ Store(\_SB.CP00._PPC, NPST)
Store ("Programming Current P-state: ", Debug)
Store (NPST, Debug)
}
@@ -190,7 +190,7 @@
{
Store ("Pstate Event 0x0E", Debug)
- Store(\_PR.CP00._PPC, Local0)
+ Store(\_SB.CP00._PPC, Local0)
Subtract(PPCM, 0x01, Local1)
If(LLess(Local0, Local1)) {
@@ -205,7 +205,7 @@
Method (_Q0F)
{
Store ("Pstate Event 0x0F", Debug)
- Store(\_PR.CP00._PPC, Local0)
+ Store(\_SB.CP00._PPC, Local0)
If(Local0) {
Decrement(Local0)
diff --git a/src/mainboard/getac/p470/acpi/ec.asl b/src/mainboard/getac/p470/acpi/ec.asl
index 618055b..1b30e03 100644
--- a/src/mainboard/getac/p470/acpi/ec.asl
+++ b/src/mainboard/getac/p470/acpi/ec.asl
@@ -99,7 +99,7 @@
// EC Query methods, called upon SCI interrupts.
Method (_Q01, 0)
{
- Notify (\_PR.CP00, 0x80)
+ Notify (\_SB.CP00, 0x80)
If(ADP) {
Store(1, \_SB.AC.ACST)
TRAP(0xe3)
diff --git a/src/mainboard/getac/p470/acpi/platform.asl b/src/mainboard/getac/p470/acpi/platform.asl
index 6d1948f..b2d9fd0 100644
--- a/src/mainboard/getac/p470/acpi/platform.asl
+++ b/src/mainboard/getac/p470/acpi/platform.asl
@@ -89,15 +89,15 @@
// Windows XP SP2 P-State restore
If (LAnd(LEqual(OSYS, 2002), And(CFGD, 1))) {
- If (LGreater(\_PR.CP00._PPC, 0)) {
- Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
+ If (LGreater(\_SB.CP00._PPC, 0)) {
+ Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
- Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
+ Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
} Else {
- Add(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
+ Add(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
- Subtract(\_PR.CP00._PPC, 1, \_PR.CP00._PPC)
+ Subtract(\_SB.CP00._PPC, 1, \_SB.CP00._PPC)
PNOT()
}
}
diff --git a/src/mainboard/getac/p470/acpi/thermal.asl b/src/mainboard/getac/p470/acpi/thermal.asl
index 9e83384..2a4d7a9 100644
--- a/src/mainboard/getac/p470/acpi/thermal.asl
+++ b/src/mainboard/getac/p470/acpi/thermal.asl
@@ -73,9 +73,9 @@
Method (_PSL, 0, Serialized)
{
If (MPEN) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
+ Return (Package() {\_SB.CP00, \_SB.CP01})
}
- Return (Package() {\_PR.CP00})
+ Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling
diff --git a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl
index bdd9792..49991a8 100644
--- a/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl
+++ b/src/mainboard/google/cyan/variants/terra/include/variant/acpi/cpu.asl
@@ -41,11 +41,11 @@
#define DPTF_CPU_ACTIVE_AC4 50
#endif
-External (\_PR.CP00._TSS, MethodObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
-External (\_PR.CP00._PSS, MethodObj)
+External (\_SB.CP00._TSS, MethodObj)
+External (\_SB.CP00._TPC, MethodObj)
+External (\_SB.CP00._PTC, PkgObj)
+External (\_SB.CP00._TSD, PkgObj)
+External (\_SB.CP00._PSS, MethodObj)
Device (B0DB)
{
@@ -66,8 +66,8 @@
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@@ -78,8 +78,8 @@
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_SB.CP00._TPC)) {
+ Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@@ -87,8 +87,8 @@
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_SB.CP00._PTC)) {
+ Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@@ -100,8 +100,8 @@
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_SB.CP00._TSD)) {
+ Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@@ -112,8 +112,8 @@
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -140,8 +140,8 @@
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_SB.CP00._PSS)) {
+ Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@@ -155,8 +155,8 @@
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+ } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
+ Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
diff --git a/src/mainboard/roda/rk886ex/acpi/thermal.asl b/src/mainboard/roda/rk886ex/acpi/thermal.asl
index 405a9e0..f06b273 100644
--- a/src/mainboard/roda/rk886ex/acpi/thermal.asl
+++ b/src/mainboard/roda/rk886ex/acpi/thermal.asl
@@ -61,9 +61,9 @@
Method (_PSL, 0, Serialized)
{
If (MPEN) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
+ Return (Package() {\_SB.CP00, \_SB.CP01})
}
- Return (Package() {\_PR.CP00})
+ Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling
diff --git a/src/mainboard/roda/rk9/acpi/thermal.asl b/src/mainboard/roda/rk9/acpi/thermal.asl
index de6fd02..8eb8195 100644
--- a/src/mainboard/roda/rk9/acpi/thermal.asl
+++ b/src/mainboard/roda/rk9/acpi/thermal.asl
@@ -79,9 +79,9 @@
Method (_PSL, 0, Serialized)
{
If (MPEN) {
- Return (Package() {\_PR.CP00, \_PR.CP01})
+ Return (Package() {\_SB.CP00, \_SB.CP01})
}
- Return (Package() {\_PR.CP00})
+ Return (Package() {\_SB.CP00})
}
// TC1 value for passive cooling
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index 7c33d20..1a4f33d 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -151,16 +151,16 @@
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
- External (\_PR.CP00._PSS)
+ External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_PR.CP00._PSS), Local1)
+ Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+ (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}
diff --git a/src/northbridge/intel/ironlake/acpi/hostbridge.asl b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
index 57d6ba0..8d4ec25 100644
--- a/src/northbridge/intel/ironlake/acpi/hostbridge.asl
+++ b/src/northbridge/intel/ironlake/acpi/hostbridge.asl
@@ -102,16 +102,16 @@
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
- External (\_PR.CP00._PSS)
+ External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_PR.CP00._PSS), Local1)
+ Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+ (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 9dd6fc0..b0e314e 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -141,16 +141,16 @@
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
- External (\_PR.CP00._PSS)
+ External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_PR.CP00._PSS), Local1)
+ Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+ (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}
diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c
index c9ccdbd..1797e48 100644
--- a/src/soc/intel/baytrail/acpi.c
+++ b/src/soc/intel/baytrail/acpi.c
@@ -419,7 +419,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
core, pcontrol_blk, plen);
diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
index a351e6c..289dcd4 100644
--- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl
+++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl
@@ -12,11 +12,11 @@
* GNU General Public License for more details.
*/
-External (\_PR.CP00._TSS, MethodObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
-External (\_PR.CP00._PSS, MethodObj)
+External (\_SB.CP00._TSS, MethodObj)
+External (\_SB.CP00._TPC, MethodObj)
+External (\_SB.CP00._PTC, PkgObj)
+External (\_SB.CP00._TSD, PkgObj)
+External (\_SB.CP00._PSS, MethodObj)
Device (TCPU)
{
@@ -38,8 +38,8 @@
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@@ -50,8 +50,8 @@
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_SB.CP00._TPC)) {
+ Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@@ -59,8 +59,8 @@
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_SB.CP00._PTC)) {
+ Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@@ -72,8 +72,8 @@
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_SB.CP00._TSD)) {
+ Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@@ -84,8 +84,8 @@
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -112,8 +112,8 @@
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_SB.CP00._PSS)) {
+ Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@@ -127,8 +127,8 @@
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+ } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
+ Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 765be82..8142e1b 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -422,7 +422,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(core, pcontrol_blk, plen);
/* Generate P-state tables */
diff --git a/src/soc/intel/braswell/acpi/dptf/cpu.asl b/src/soc/intel/braswell/acpi/dptf/cpu.asl
index 5b91699..1236c84 100644
--- a/src/soc/intel/braswell/acpi/dptf/cpu.asl
+++ b/src/soc/intel/braswell/acpi/dptf/cpu.asl
@@ -41,11 +41,11 @@
#define DPTF_CPU_ACTIVE_AC4 50
#endif
-External (\_PR.CP00._TSS, MethodObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
-External (\_PR.CP00._PSS, MethodObj)
+External (\_SB.CP00._TSS, MethodObj)
+External (\_SB.CP00._TPC, MethodObj)
+External (\_SB.CP00._PTC, PkgObj)
+External (\_SB.CP00._TSD, PkgObj)
+External (\_SB.CP00._PSS, MethodObj)
Device (B0DB)
{
@@ -66,8 +66,8 @@
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@@ -78,8 +78,8 @@
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_SB.CP00._TPC)) {
+ Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@@ -87,8 +87,8 @@
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_SB.CP00._PTC)) {
+ Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@@ -100,8 +100,8 @@
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_SB.CP00._TSD)) {
+ Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@@ -112,8 +112,8 @@
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS ()), Local0)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Store (SizeOf (\_SB.CP00._TSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -140,8 +140,8 @@
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_SB.CP00._PSS)) {
+ Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@@ -155,8 +155,8 @@
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS ()), Local0)
+ } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
+ Store (SizeOf (\_SB.CP00._PSS ()), Local0)
Decrement (Local0)
Return (Local0)
} Else {
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index 61f1008..1664fdf 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -517,7 +517,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID - 1) * cores_per_package+coreID - 1,
pcontrol_blk, plen);
diff --git a/src/soc/intel/broadwell/acpi/ctdp.asl b/src/soc/intel/broadwell/acpi/ctdp.asl
index 86ebdd5..6f3cad6 100644
--- a/src/soc/intel/broadwell/acpi/ctdp.asl
+++ b/src/soc/intel/broadwell/acpi/ctdp.asl
@@ -71,16 +71,16 @@
* Package (6) { freq, power, tlat, blat, control, status }
* }
*/
- External (\_PR.CP00._PSS)
+ External (\_SB.CP00._PSS)
Method (PSSS, 1, NotSerialized)
{
Store (One, Local0) /* Start at P1 */
- Store (SizeOf (\_PR.CP00._PSS), Local1)
+ Store (SizeOf (\_SB.CP00._PSS), Local1)
While (LLess (Local0, Local1)) {
/* Store _PSS entry Control value to Local2 */
ShiftRight (DeRefOf (Index (DeRefOf (Index
- (\_PR.CP00._PSS, Local0)), 4)), 8, Local2)
+ (\_SB.CP00._PSS, Local0)), 4)), 8, Local2)
If (LEqual (Local2, Arg0)) {
Return (Subtract (Local0, 1))
}
diff --git a/src/soc/intel/common/acpi/dptf/cpu.asl b/src/soc/intel/common/acpi/dptf/cpu.asl
index 99dc32a..982776f 100644
--- a/src/soc/intel/common/acpi/dptf/cpu.asl
+++ b/src/soc/intel/common/acpi/dptf/cpu.asl
@@ -12,11 +12,11 @@
* GNU General Public License for more details.
*/
-External (\_PR.CP00._PSS, PkgObj)
-External (\_PR.CP00._TSS, PkgObj)
-External (\_PR.CP00._TPC, MethodObj)
-External (\_PR.CP00._PTC, PkgObj)
-External (\_PR.CP00._TSD, PkgObj)
+External (\_SB.CP00._PSS, PkgObj)
+External (\_SB.CP00._TSS, PkgObj)
+External (\_SB.CP00._TPC, MethodObj)
+External (\_SB.CP00._PTC, PkgObj)
+External (\_SB.CP00._TSD, PkgObj)
External (\_SB.MPDL, IntObj)
Device (DPTF_CPU_DEVICE)
@@ -38,8 +38,8 @@
Method (_TSS)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Return (\_PR.CP00._TSS)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Return (\_SB.CP00._TSS)
} Else {
Return (Package ()
{
@@ -50,8 +50,8 @@
Method (_TPC)
{
- If (CondRefOf (\_PR.CP00._TPC)) {
- Return (\_PR.CP00._TPC)
+ If (CondRefOf (\_SB.CP00._TPC)) {
+ Return (\_SB.CP00._TPC)
} Else {
Return (0)
}
@@ -59,8 +59,8 @@
Method (_PTC)
{
- If (CondRefOf (\_PR.CP00._PTC)) {
- Return (\_PR.CP00._PTC)
+ If (CondRefOf (\_SB.CP00._PTC)) {
+ Return (\_SB.CP00._PTC)
} Else {
Return (Package ()
{
@@ -72,8 +72,8 @@
Method (_TSD)
{
- If (CondRefOf (\_PR.CP00._TSD)) {
- Return (\_PR.CP00._TSD)
+ If (CondRefOf (\_SB.CP00._TSD)) {
+ Return (\_SB.CP00._TSD)
} Else {
Return (Package ()
{
@@ -84,8 +84,8 @@
Method (_TDL)
{
- If (CondRefOf (\_PR.CP00._TSS)) {
- Store (SizeOf (\_PR.CP00._TSS), Local0)
+ If (CondRefOf (\_SB.CP00._TSS)) {
+ Store (SizeOf (\_SB.CP00._TSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
@@ -112,8 +112,8 @@
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_SB.CP00._PSS)) {
+ Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@@ -128,8 +128,8 @@
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS), Local0)
+ } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
+ Store (SizeOf (\_SB.CP00._PSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c
index bed4401..b848db44 100644
--- a/src/soc/intel/common/block/acpi/acpi.c
+++ b/src/soc/intel/common/block/acpi/acpi.c
@@ -433,7 +433,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor((cpu_id) * cores_per_package +
core_id, pcontrol_blk, plen);
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index 10eec8a..e6723aa 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -522,7 +522,7 @@
plen = 0;
}
- /* Generate processor \_PR.CPUx */
+ /* Generate processor \_SB.CPUx */
acpigen_write_processor(
cpu_id*cores_per_package+core_id,
pcontrol_blk, plen);
diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl
index 9ffe040..b069919 100644
--- a/src/soc/intel/skylake/acpi/dptf/cpu.asl
+++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl
@@ -20,7 +20,7 @@
#define DPTF_CPU_CRITICAL 90
#endif
-External (\_PR.CP00._PSS, PkgObj)
+External (\_SB.CP00._PSS, PkgObj)
External (\_SB.MPDL, IntObj)
Device (B0D4)
@@ -55,8 +55,8 @@
Method (_PSS)
{
- If (CondRefOf (\_PR.CP00._PSS)) {
- Return (\_PR.CP00._PSS)
+ If (CondRefOf (\_SB.CP00._PSS)) {
+ Return (\_SB.CP00._PSS)
} Else {
Return (Package ()
{
@@ -71,8 +71,8 @@
/* Check for mainboard specific _PDL override */
If (CondRefOf (\_SB.MPDL)) {
Return (\_SB.MPDL)
- } ElseIf (CondRefOf (\_PR.CP00._PSS)) {
- Store (SizeOf (\_PR.CP00._PSS), Local0)
+ } ElseIf (CondRefOf (\_SB.CP00._PSS)) {
+ Store (SizeOf (\_SB.CP00._PSS), Local0)
Decrement (Local0)
Return (Local0)
} Else {
diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c
index 8059c2c..8a8d99e 100644
--- a/src/southbridge/intel/i82371eb/acpi_tables.c
+++ b/src/southbridge/intel/i82371eb/acpi_tables.c
@@ -44,7 +44,7 @@
/* without the outer scope, furhter ssdt addition will end up
* within the processor statement */
- acpigen_write_scope("\\_PR");
+ acpigen_write_scope("\\_SB");
for (cpu=0; cpu < numcpus; cpu++) {
acpigen_write_processor(cpu, pcontrol_blk, plen);
acpigen_pop_len();