| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| config RANGELEY_FSP_SPECIFIC_OPTIONS |
| def_bool y |
| select PLATFORM_USES_FSP |
| select USE_GENERIC_FSP_CAR_INC |
| select FSP_USES_UPD |
| select ENABLE_MRC_CACHE #rangeley FSP always needs MRC data |
| |
| config FSP_FILE |
| string |
| default "../intel/fsp/rangeley/FvFsp.bin" |
| help |
| The path and filename of the Intel FSP binary for this platform. |
| |
| config FSP_LOC |
| hex |
| default 0xfff80000 |
| help |
| The location in CBFS that the FSP is located. This must match the |
| value that is set in the FSP binary. If the FSP needs to be moved, |
| rebase the FSP with Intel's BCT (tool). |
| |
| The Rangeley FSP is built with a preferred base address of 0xFFF80000 |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xfef00000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x4000 |