cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld
index 72836b5..aa925a2 100644
--- a/src/soc/rockchip/rk3399/memlayout.ld
+++ b/src/soc/rockchip/rk3399/memlayout.ld
@@ -24,11 +24,12 @@
FMAP_CACHE(0xFF8C1400, 2K)
TIMESTAMP(0xFF8C1C00, 1K)
/* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
- OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
- BOOTBLOCK(0xFF8D8000, 40K)
+ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4)
+ BOOTBLOCK(0xFF8D7000, 40K)
#endif
- VBOOT2_WORK(0XFF8E2000, 12K)
- TTB(0xFF8E5000, 24K)
+ CBFS_MCACHE(0xFF8E1000, 8K)
+ VBOOT2_WORK(0XFF8E3000, 12K)
+ TTB(0xFF8E6000, 20K)
PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
STACK(0xFF8ED000, 12K)
SRAM_END(0xFF8F0000)