cbfs: Enable CBFS mcache on most chipsets
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is
enabled by default. Some older chipsets with insufficient SRAM/CAR space
still have it explicitly disabled. All others get the new section added
to their memlayout... 8K seems like a sane default to start with.
Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc
index a88e81a..d9bd096 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc
@@ -12,6 +12,7 @@
ALIGN_COUNTER(64)
PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE)
TIMESTAMP(., TIMESTAMP_BUFFER_SIZE)
+ CBFS_MCACHE(., CONFIG_CBFS_MCACHE_SIZE)
FMAP_CACHE(., FMAP_SIZE)
#if CONFIG(VBOOT)
diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
index 369d431..bf101e3 100644
--- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
+++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld
@@ -39,6 +39,8 @@
* | Unused hole |
* +--------------------------------+
* | FMAP cache (FMAP_SIZE) |
+ * +--------------------------------+
+ * | CBFS mcache (CBFS_MCACHE_SIZE) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE + 0x200
* | Early Timestamp region (512B) |
* +--------------------------------+ PSP_SHAREDMEM_BASE + 0x40 + VB2_FIRMWARE_WORKBUF_RECOMMENDED_SIZE + PRERAM_CBMEM_CONSOLE_SIZE
diff --git a/src/soc/cavium/cn81xx/memlayout.ld b/src/soc/cavium/cn81xx/memlayout.ld
index 79673c9..0257b23 100644
--- a/src/soc/cavium/cn81xx/memlayout.ld
+++ b/src/soc/cavium/cn81xx/memlayout.ld
@@ -20,7 +20,8 @@
PRERAM_CBFS_CACHE(BOOTROM_OFFSET + 0x6000, 6K)
FMAP_CACHE(BOOTROM_OFFSET + 0x7800, 2K)
PRERAM_CBMEM_CONSOLE(BOOTROM_OFFSET + 0x8000, 8K)
- BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 64K)
+ BOOTBLOCK(BOOTROM_OFFSET + 0x20000, 56K)
+ CBFS_MCACHE(BOOTROM_OFFSET + 0x2e000, 8K)
VBOOT2_WORK(BOOTROM_OFFSET + 0x30000, 12K)
TPM_TCPA_LOG(BOOTROM_OFFSET + 0x33000, 2K)
VERSTAGE(BOOTROM_OFFSET + 0x33800, 50K)
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index edbc6fd..dcc30ee 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -42,6 +42,7 @@
select CPU_INTEL_COMMON
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT
+ select NO_CBFS_MCACHE
config DCACHE_BSP_STACK_SIZE
hex
diff --git a/src/soc/mediatek/mt8173/memlayout.ld b/src/soc/mediatek/mt8173/memlayout.ld
index 4aece51..d9a6d83 100644
--- a/src/soc/mediatek/mt8173/memlayout.ld
+++ b/src/soc/mediatek/mt8173/memlayout.ld
@@ -30,7 +30,8 @@
FMAP_CACHE(0x00103800, 2K)
PRERAM_CBMEM_CONSOLE(0x00104000, 12K)
WATCHDOG_TOMBSTONE(0x00107000, 4)
- PRERAM_CBFS_CACHE(0x00107004, 16K - 4)
+ PRERAM_CBFS_CACHE(0x00107004, 8K - 4)
+ CBFS_MCACHE(0x00109000, 8K)
TIMESTAMP(0x0010B000, 4K)
ROMSTAGE(0x0010C000, 92K)
STACK(0x00124000, 16K)
diff --git a/src/soc/mediatek/mt8183/memlayout.ld b/src/soc/mediatek/mt8183/memlayout.ld
index a266377..db56666 100644
--- a/src/soc/mediatek/mt8183/memlayout.ld
+++ b/src/soc/mediatek/mt8183/memlayout.ld
@@ -30,7 +30,8 @@
SRAM_L2C_START(0x00200000)
OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0x00201000, 188K)
- BOOTBLOCK(0x00230000, 64K)
+ BOOTBLOCK(0x00230000, 56K)
+ CBFS_MCACHE(0x0023e000, 8K)
DRAM_INIT_CODE(0x00240000, 208K)
PRERAM_CBFS_CACHE(0x00274000, 48K)
SRAM_L2C_END(0x00280000)
diff --git a/src/soc/mediatek/mt8192/include/soc/memlayout.ld b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
index c016d5f..2a21dd6 100644
--- a/src/soc/mediatek/mt8192/include/soc/memlayout.ld
+++ b/src/soc/mediatek/mt8192/include/soc/memlayout.ld
@@ -26,9 +26,10 @@
TPM_TCPA_LOG(0x00103000, 2K)
FMAP_CACHE(0x00103800, 2K)
WATCHDOG_TOMBSTONE(0x00104000, 4)
- PRERAM_CBMEM_CONSOLE(0x00104004, 19K - 4)
- TIMESTAMP(0x00108c00, 1K)
- STACK(0x00109000, 16K)
+ PRERAM_CBMEM_CONSOLE(0x00104004, 15K - 4)
+ CBFS_MCACHE(0x00107c00, 8K)
+ TIMESTAMP(0x00109c00, 1K)
+ STACK(0x0010a000, 12K)
TTB(0x0010d000, 28K)
DMA_COHERENT(0x00114000, 4K)
/*
diff --git a/src/soc/nvidia/tegra124/memlayout.ld b/src/soc/nvidia/tegra124/memlayout.ld
index 94b6fd8..f661d2a 100644
--- a/src/soc/nvidia/tegra124/memlayout.ld
+++ b/src/soc/nvidia/tegra124/memlayout.ld
@@ -16,7 +16,8 @@
TTB(0x40000000, 16K + 32)
PRERAM_CBMEM_CONSOLE(0x40004020, 6K - 32)
FMAP_CACHE(0x40005800, 2K)
- PRERAM_CBFS_CACHE(0x40006000, 14K)
+ CBFS_MCACHE(0x40006000, 8K)
+ PRERAM_CBFS_CACHE(0x40008000, 6K)
VBOOT2_WORK(0x40009800, 12K)
TPM_TCPA_LOG(0x4000D800, 2K)
STACK(0x4000E000, 8K)
diff --git a/src/soc/nvidia/tegra210/memlayout.ld b/src/soc/nvidia/tegra210/memlayout.ld
index e5620bc..42f2164 100644
--- a/src/soc/nvidia/tegra210/memlayout.ld
+++ b/src/soc/nvidia/tegra210/memlayout.ld
@@ -17,7 +17,8 @@
SRAM_START(0x40000000)
PRERAM_CBMEM_CONSOLE(0x40000000, 2K)
FMAP_CACHE(0x40000800, 2K)
- PRERAM_CBFS_CACHE(0x40001000, 28K)
+ PRERAM_CBFS_CACHE(0x40001000, 20K)
+ CBFS_MCACHE(0x40006000, 8K)
VBOOT2_WORK(0x40008000, 12K)
TPM_TCPA_LOG(0x4000B000, 2K)
#if ENV_ARM64
diff --git a/src/soc/qualcomm/ipq40xx/memlayout.ld b/src/soc/qualcomm/ipq40xx/memlayout.ld
index 1a2dd31..4c54294 100644
--- a/src/soc/qualcomm/ipq40xx/memlayout.ld
+++ b/src/soc/qualcomm/ipq40xx/memlayout.ld
@@ -20,7 +20,8 @@
/* This includes bootblock image, can be reused after bootblock starts */
/* UBER_SBL(0x0A0C0000, 48K) */
- PRERAM_CBFS_CACHE(0x0A0C0000, 92K)
+ PRERAM_CBFS_CACHE(0x0A0C0000, 84K)
+ CBFS_MCACHE(0x0A0ED800, 8K)
FMAP_CACHE(0x0A0EF800, 2K)
TTB(0x0A0F0000, 16K)
diff --git a/src/soc/qualcomm/ipq806x/memlayout.ld b/src/soc/qualcomm/ipq806x/memlayout.ld
index 6e7e56c..793e74e 100644
--- a/src/soc/qualcomm/ipq806x/memlayout.ld
+++ b/src/soc/qualcomm/ipq806x/memlayout.ld
@@ -24,7 +24,8 @@
QCA_SHARED_RAM(2A03F000, 4K)
*/
STACK(0x2A040000, 16K)
- PRERAM_CBFS_CACHE(0x2A044000, 91K)
+ PRERAM_CBFS_CACHE(0x2A044000, 83K)
+ CBFS_MCACHE(0x2A059000, 8K)
FMAP_CACHE(0x2A05B000, 2K)
TTB_SUBTABLES(0x2A05B800, 2K)
TTB(0x2A05C000, 16K)
diff --git a/src/soc/qualcomm/qcs405/memlayout.ld b/src/soc/qualcomm/qcs405/memlayout.ld
index ff2ad2f..a282512 100644
--- a/src/soc/qualcomm/qcs405/memlayout.ld
+++ b/src/soc/qualcomm/qcs405/memlayout.ld
@@ -25,7 +25,8 @@
STACK(0x8C4B000, 16K)
TIMESTAMP(0x8C4F000, 1K)
PRERAM_CBMEM_CONSOLE(0x8C4F400, 32K)
- PRERAM_CBFS_CACHE(0x8C57400, 70K)
+ PRERAM_CBFS_CACHE(0x8C57400, 62K)
+ CBFS_MCACHE(0x8C66C00, 8K)
FMAP_CACHE(0x8C68C00, 2K)
REGION(bsram_unused, 0x8C69400, 0xA1C00, 0x100)
BSRAM_END(0x8D80000)
diff --git a/src/soc/qualcomm/sc7180/memlayout.ld b/src/soc/qualcomm/sc7180/memlayout.ld
index 482620a..ca9c993 100644
--- a/src/soc/qualcomm/sc7180/memlayout.ld
+++ b/src/soc/qualcomm/sc7180/memlayout.ld
@@ -43,6 +43,7 @@
REGION(qclib_serial_log, 0x14852000, 4K, 4K)
REGION(ddr_information, 0x14853000, 1K, 1K)
FMAP_CACHE(0x14853400, 2K)
+ CBFS_MCACHE(0x14853C00, 8K)
REGION(dcb, 0x1485b000, 16K, 4K)
REGION(pmic, 0x1485f000, 48K, 4K)
REGION(qclib, 0x1486b000, 596K, 4K)
diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig
index 3dc9a9b..a51df2a 100644
--- a/src/soc/rockchip/rk3288/Kconfig
+++ b/src/soc/rockchip/rk3288/Kconfig
@@ -17,6 +17,7 @@
select HAVE_LINEAR_FRAMEBUFFER
select NO_BOOTBLOCK_CONSOLE
select NO_FMAP_CACHE
+ select NO_CBFS_MCACHE
if SOC_ROCKCHIP_RK3288
diff --git a/src/soc/rockchip/rk3399/memlayout.ld b/src/soc/rockchip/rk3399/memlayout.ld
index 72836b5..aa925a2 100644
--- a/src/soc/rockchip/rk3399/memlayout.ld
+++ b/src/soc/rockchip/rk3399/memlayout.ld
@@ -24,11 +24,12 @@
FMAP_CACHE(0xFF8C1400, 2K)
TIMESTAMP(0xFF8C1C00, 1K)
/* 0xFF8C2004 is the entry point address the masked ROM will jump to. */
- OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 88K - 4)
- BOOTBLOCK(0xFF8D8000, 40K)
+ OVERLAP_DECOMPRESSOR_VERSTAGE_ROMSTAGE(0xFF8C2004, 84K - 4)
+ BOOTBLOCK(0xFF8D7000, 40K)
#endif
- VBOOT2_WORK(0XFF8E2000, 12K)
- TTB(0xFF8E5000, 24K)
+ CBFS_MCACHE(0xFF8E1000, 8K)
+ VBOOT2_WORK(0XFF8E3000, 12K)
+ TTB(0xFF8E6000, 20K)
PRERAM_CBMEM_CONSOLE(0xFF8EB000, 8K)
STACK(0xFF8ED000, 12K)
SRAM_END(0xFF8F0000)
diff --git a/src/soc/samsung/exynos5250/memlayout.ld b/src/soc/samsung/exynos5250/memlayout.ld
index be4bb6e..eec9f60 100644
--- a/src/soc/samsung/exynos5250/memlayout.ld
+++ b/src/soc/samsung/exynos5250/memlayout.ld
@@ -18,7 +18,8 @@
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 76K)
+ PRERAM_CBFS_CACHE(0x205C000, 68K)
+ CBFS_MCACHE(0x206D000, 8K)
FMAP_CACHE(0x206F000, 2K)
TPM_TCPA_LOG(0x206F800, 2K)
VBOOT2_WORK(0x2070000, 12K)
diff --git a/src/soc/samsung/exynos5420/memlayout.ld b/src/soc/samsung/exynos5420/memlayout.ld
index e299001..7c89413 100644
--- a/src/soc/samsung/exynos5420/memlayout.ld
+++ b/src/soc/samsung/exynos5420/memlayout.ld
@@ -19,7 +19,8 @@
ROMSTAGE(0x2030000, 128K)
/* 32K hole */
TTB(0x2058000, 16K)
- PRERAM_CBFS_CACHE(0x205C000, 74K)
+ PRERAM_CBFS_CACHE(0x205C000, 66K)
+ CBFS_MCACHE(0x206C800, 8K)
FMAP_CACHE(0x206E800, 2K)
STACK(0x206F000, 16K)
/* 1K hole for weird kernel-shared CPU/SMP state structure that doesn't
diff --git a/src/soc/sifive/fu540/memlayout.ld b/src/soc/sifive/fu540/memlayout.ld
index fd63dc0..b365b96 100644
--- a/src/soc/sifive/fu540/memlayout.ld
+++ b/src/soc/sifive/fu540/memlayout.ld
@@ -12,8 +12,9 @@
{
L2LIM_START(FU540_L2LIM)
BOOTBLOCK(FU540_L2LIM, 64K)
- CAR_STACK(FU540_L2LIM + 64K, 20K)
- PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
+ CAR_STACK(FU540_L2LIM + 64K, 12K)
+ PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 76K, 8K)
+ CBFS_MCACHE(FU540_L2LIM + 84K, 8K)
FMAP_CACHE(FU540_L2LIM + 92K, 2K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
PRERAM_CBFS_CACHE(FU540_L2LIM + 256K, 128K)
diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld
index 720da26..042febe 100644
--- a/src/soc/ti/am335x/memlayout.ld
+++ b/src/soc/ti/am335x/memlayout.ld
@@ -9,6 +9,7 @@
SRAM_START(0x402f0400)
BOOTBLOCK(0x402f0400, 20K)
FMAP_CACHE(0x402f0400+20K, 2K)
+ CBFS_MCACHE(0x402f0400+20K+2K, 8K)
TTB(0x402F8000, 16K)
ROMSTAGE(0x402F8000+16K, 40K)