| ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
| include /config/nofailovercalculation.lb |
| default CONFIG_ROM_PAYLOAD = 1 |
| |
| arch i386 end |
| |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| #needed by irq_tables and mptable and acpi_tables |
| object get_bus_conf.o |
| |
| if CONFIG_GENERATE_MP_TABLE object mptable.o end |
| if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end |
| #object reset.o |
| if CONFIG_USE_INIT |
| makerule ./auto.o |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| end |
| else |
| makerule ./auto.inc |
| depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h" |
| action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@" |
| action "perl -e 's/\.rodata/.rom.data/g' -pi $@" |
| action "perl -e 's/\.text/.section .rom.text/g' -pi $@" |
| end |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/entry16.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| end |
| |
| mainboardinit cpu/x86/32bit/entry32.inc |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/x86/32bit/entry32.lds |
| end |
| |
| if CONFIG_USE_INIT |
| ldscript /cpu/amd/car/cache_as_ram.lds |
| end |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| else |
| mainboardinit cpu/x86/32bit/reset32.inc |
| ldscript /cpu/x86/32bit/reset32.lds |
| end |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit southbridge/nvidia/ck804/id.inc |
| ldscript /southbridge/nvidia/ck804/id.lds |
| |
| ## |
| ## ROMSTRAP table for CK804 |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit southbridge/nvidia/ck804/romstrap.inc |
| ldscript /southbridge/nvidia/ck804/romstrap.lds |
| end |
| |
| ## |
| ## Setup Cache-As-Ram |
| ## |
| mainboardinit cpu/amd/car/cache_as_ram.inc |
| |
| ### |
| ### This is the early phase of coreboot startup |
| ### Things are delicate and we test to see if we should |
| ### failover to another image. |
| ### |
| if CONFIG_USE_FALLBACK_IMAGE |
| ldscript /arch/i386/lib/failover.lds |
| end |
| |
| ## |
| ## Setup RAM |
| ## |
| if CONFIG_USE_INIT |
| initobject auto.o |
| else |
| mainboardinit ./auto.inc |
| end |
| |
| ## |
| ## Include the secondary Configuration files |
| ## |
| config chip.h |
| |
| # sample config for tyan/s2895 |
| chip northbridge/amd/amdk8/root_complex |
| device apic_cluster 0 on |
| chip cpu/amd/socket_940 |
| device apic 0 on end |
| end |
| end |
| device pci_domain 0 on |
| chip northbridge/amd/amdk8 #mc0 |
| device pci 18.0 on end # link 0 |
| device pci 18.0 on # link1 |
| # devices on link 0, link 0 == LDT 0 |
| chip southbridge/nvidia/ck804 |
| device pci 0.0 on end # HT |
| device pci 1.0 on # LPC |
| chip superio/smsc/lpc47m10x |
| device pnp 2e.0 off # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 2e.3 off # Parallel Port |
| io 0x60 = 0x378 |
| irq 0x70 = 7 |
| end |
| device pnp 2e.4 on # Com1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 2e.5 off # Com2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| device pnp 2e.7 off # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| irq 0x72 = 12 |
| end |
| end |
| end |
| device pci 1.1 on # SM 0 |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-0 |
| device i2c 52 on end |
| end |
| chip drivers/generic/generic #dimm 0-1-1 |
| device i2c 53 on end |
| end |
| chip drivers/generic/generic #dimm 1-0-0 |
| device i2c 54 on end |
| end |
| chip drivers/generic/generic #dimm 1-0-1 |
| device i2c 55 on end |
| end |
| chip drivers/generic/generic #dimm 1-1-0 |
| device i2c 56 on end |
| end |
| chip drivers/generic/generic #dimm 1-1-1 |
| device i2c 57 on end |
| end |
| end # SM |
| device pci 1.1 on # SM 1 |
| #PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? |
| # chip drivers/generic/generic #PCIXA Slot1 |
| # device i2c 50 on end |
| # end |
| # chip drivers/generic/generic #PCIXB Slot1 |
| # device i2c 51 on end |
| # end |
| # chip drivers/generic/generic #PCIXB Slot2 |
| # device i2c 52 on end |
| # end |
| # chip drivers/generic/generic #PCI Slot1 |
| # device i2c 53 on end |
| # end |
| # chip drivers/generic/generic #Master CK804 PCI-E |
| # device i2c 54 on end |
| # end |
| # chip drivers/generic/generic #Slave CK804 PCI-E |
| # device i2c 55 on end |
| # end |
| chip drivers/generic/generic #MAC EEPROM |
| device i2c 51 on end |
| end |
| |
| end # SM |
| device pci 2.0 on end # USB 1.1 |
| device pci 2.1 on end # USB 2 |
| device pci 4.0 on end # ACI |
| device pci 4.1 off end # MCI |
| device pci 6.0 on end # IDE |
| device pci 7.0 on end # SATA 1 |
| device pci 8.0 on end # SATA 0 |
| device pci 9.0 on end # PCI |
| device pci a.0 on end # NIC |
| device pci b.0 off end # PCI E 3 |
| device pci c.0 off end # PCI E 2 |
| device pci d.0 off end # PCI E 1 |
| device pci e.0 on end # PCI E 0 |
| register "ide0_enable" = "1" |
| register "ide1_enable" = "1" |
| register "sata0_enable" = "1" |
| register "sata1_enable" = "1" |
| # register "nic_rom_address" = "0xfff80000" # 64k |
| # register "raid_rom_address" = "0xfff90000" |
| register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 |
| register "mac_eeprom_addr" = "0x51" |
| end |
| end # device pci 18.0 |
| device pci 18.0 on end # link 2 |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| end # mc0 |
| |
| chip northbridge/amd/amdk8 |
| device pci 19.0 on end # link 0 |
| device pci 19.0 on |
| # devices on link 1, link 1 == LDT 1 |
| chip southbridge/nvidia/ck804 |
| device pci 0.0 on end # HT |
| device pci 1.0 on end # LPC |
| device pci 1.1 off end # SM |
| device pci 2.0 off end # USB 1.1 |
| device pci 2.1 off end # USB 2 |
| device pci 4.0 off end # ACI |
| device pci 4.1 off end # MCI |
| device pci 6.0 off end # IDE |
| device pci 7.0 off end # SATA 1 |
| device pci 8.0 off end # SATA 0 |
| device pci 9.0 off end # PCI |
| device pci a.0 on end # NIC |
| device pci b.0 off end # PCI E 3 |
| device pci c.0 off end # PCI E 2 |
| device pci d.0 off end # PCI E 1 |
| device pci e.0 on end # PCI E 0 |
| # register "nic_rom_address" = "0xfff80000" # 64k |
| register "mac_eeprom_smbus" = "3" |
| register "mac_eeprom_addr" = "0x51" |
| end |
| end # device pci 19.0 |
| |
| device pci 19.0 on end |
| device pci 19.1 on end |
| device pci 19.2 on end |
| device pci 19.3 on end |
| end |
| end # PCI domain |
| |
| end #root_complex |