src/mainboard/intel/eagleheights/Config.lb

##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
## MA 02110-1301 USA
##

##
## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
##

##
## Only use the option table in a normal image
##
default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE

## CONFIG_XIP_ROM_SIZE must be a power of 2.
default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb

##
## Set all of the defaults for an x86 architecture
##

arch i386 end

##
## Build the objects we have code for in this directory.
##

driver mainboard.o
if CONFIG_GENERATE_MP_TABLE object mptable.o end
if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end

if CONFIG_GENERATE_ACPI_TABLES
	object fadt.o
	object acpi_tables.o
	makerule dsdt.c
		depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
		action  "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
		action  "mv $(CURDIR)/dsdt.hex dsdt.c"
	end
	object ./dsdt.o
end

object reset.o

if CONFIG_USE_INIT

makerule ./auto.o
	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
end

else

makerule ./auto.inc
	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
	action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
	action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
	action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end

end

##
## Build our 16 bit and 32 bit coreboot entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
if CONFIG_USE_INIT
	ldscript /cpu/x86/32bit/entry32.lds
	ldscript /cpu/x86/car/cache_as_ram.lds
end

##
## Build our reset vector (This is where coreboot is entered)
##
if CONFIG_USE_FALLBACK_IMAGE
        mainboardinit cpu/x86/16bit/reset16.inc
        ldscript /cpu/x86/16bit/reset16.lds
else
        mainboardinit cpu/x86/32bit/reset32.inc
        ldscript /cpu/x86/32bit/reset32.lds
end


##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds

##
## Setup Cache-As-Ram
##
mainboardinit cpu/intel/model_6fx/cache_as_ram.inc

###
### This is the early phase of coreboot startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if CONFIG_USE_FALLBACK_IMAGE
	ldscript /arch/i386/lib/failover.lds
end

###
### O.k. We aren't just an intermediary anymore!
###

if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end

##
## Include the secondary Configuration files
##
dir /pc80
config chip.h

chip northbridge/intel/i3100
        device pci_domain 0 on
                device pci 00.0 on end # IMCH
                device pci 00.1 on end # IMCH error status
                device pci 01.0 on end # IMCH EDMA engine
                device pci 02.0 on end # PCIe port A/A0
                device pci 03.0 on end # PCIe port A1
                chip southbridge/intel/i3100
                        # PIRQ line -> legacy IRQ mappings
			register "pirq_a_d" = "0x8b808a8a"
                        register "pirq_e_h" = "0x85808080"

                        device pci 1c.0 on end # PCIe port B0
                        device pci 1c.1 off end # PCIe port B1
                        device pci 1c.2 off end # PCIe port B2
                        device pci 1c.3 off end # PCIe port B3
                        device pci 1d.0 on end # USB (UHCI) 1
                        device pci 1d.1 on end # USB (UHCI) 2
                        device pci 1d.7 on end # USB (EHCI)
                        device pci 1e.0 on end # PCI bridge
                        device pci 1f.0 on     # LPC bridge
                                chip superio/intel/i3100
                                        device pnp 4e.4 on # Com1
                                                 io 0x60 = 0x3f8
                                                irq 0x70 = 4
                                        end
                                        device pnp 4e.5 on # Com2
                                                 io 0x60 = 0x2f8
                                                irq 0x70 = 3
                                        end
                                end
				chip superio/smsc/smscsuperio
					device pnp 2e.0 off	# Floppy
						io 0x60 = 0x3f0
						irq 0x70 = 6
						drq 0x74 = 2
					end
					device pnp 2e.2 off	# Serial Port 4
						io 0x60 = 0x2e8
						irq 0x70 = 3
					end
					device pnp 2e.3 on	# Parallel Port
						io 0x60 = 0x378
						irq 0x70 = 7
						drq 0x74 = 2
					end
					device pnp 2e.4 off	# Serial Port 3
						io 0x60 = 0x3e8
						irq 0x70 = 4
					end
					device pnp 2e.7 on	# PS/2 Keyboard / Mouse
						io 0x60 = 0x60
						io 0x62 = 0x64
						irq 0x70 = 1    # PS/2 keyboard interrupt
						irq 0x72 = 12   # PS/2 mouse interrupt
					end
					device pnp 2e.a off     # Runtime registers
					       io 0x60 = 0x600
					end
				end
                        end
                        device pci 1f.2 on end # SATA
                        device pci 1f.3 on end # SMBus
			device pci 1f.4 on end # Performance counters
                end
        end
        device apic_cluster 0 on
                chip cpu/intel/bga956
                        device apic 0 on end
                end
        end
end