| ## CONFIG_XIP_ROM_SIZE must be a power of 2. |
| default CONFIG_XIP_ROM_SIZE = 64 * 1024 |
| include /config/nofailovercalculation.lb |
| |
| ## |
| ## Set all of the defaults for an x86 architecture |
| ## |
| |
| arch i386 end |
| |
| ## |
| ## Build the objects we have code for in this directory. |
| ## |
| |
| driver mainboard.o |
| |
| if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end |
| #object reset.o |
| |
| ## |
| ## Romcc output |
| ## |
| makerule ./failover.E |
| depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" |
| action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" |
| end |
| |
| makerule ./failover.inc |
| depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" |
| action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@" |
| end |
| |
| makerule ./auto.E |
| depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
| end |
| makerule ./auto.inc |
| depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" |
| action "../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" |
| end |
| |
| ## |
| ## Build our 16 bit and 32 bit coreboot entry code |
| ## |
| mainboardinit cpu/x86/16bit/entry16.inc |
| mainboardinit cpu/x86/32bit/entry32.inc |
| ldscript /cpu/x86/16bit/entry16.lds |
| ldscript /cpu/x86/32bit/entry32.lds |
| |
| ## |
| ## Build our reset vector (This is where coreboot is entered) |
| ## |
| if CONFIG_USE_FALLBACK_IMAGE |
| mainboardinit cpu/x86/16bit/reset16.inc |
| ldscript /cpu/x86/16bit/reset16.lds |
| else |
| mainboardinit cpu/x86/32bit/reset32.inc |
| ldscript /cpu/x86/32bit/reset32.lds |
| end |
| |
| ### Should this be in the northbridge code? |
| mainboardinit arch/i386/lib/cpu_reset.inc |
| |
| ## |
| ## Include an id string (For safe flashing) |
| ## |
| mainboardinit arch/i386/lib/id.inc |
| ldscript /arch/i386/lib/id.lds |
| |
| ### |
| ### This is the early phase of coreboot startup |
| ### Things are delicate and we test to see if we should |
| ### failover to another image. |
| ### |
| if CONFIG_USE_FALLBACK_IMAGE |
| ldscript /arch/i386/lib/failover.lds |
| mainboardinit ./failover.inc |
| end |
| |
| ### |
| ### O.k. We aren't just an intermediary anymore! |
| ### |
| |
| ## |
| ## Setup RAM |
| ## |
| mainboardinit cpu/x86/fpu/enable_fpu.inc |
| mainboardinit ./auto.inc |
| |
| ## |
| ## Include the secondary Configuration files |
| ## |
| dir /pc80 |
| config chip.h |
| |
| chip northbridge/amd/gx2 |
| device apic_cluster 0 on |
| chip cpu/amd/model_gx2 |
| device apic 0 on end |
| end |
| end |
| device pci_domain 0 on |
| device pci 1.0 on end |
| device pci 1.1 on end |
| chip southbridge/amd/cs5536 |
| register "lpc_serirq_enable" = "0x80" # enabled with default timing |
| device pci d.0 on end # Realtek 8139 LAN |
| device pci f.0 on end # ISA Bridge |
| device pci f.2 on end # IDE Controller |
| device pci f.3 on end # Audio |
| device pci f.4 on end # OHCI |
| device pci f.4 on end # UHCI |
| end |
| end |
| end |
| |