FLASH 32M { | |
SI_ALL 9M { | |
SI_DESC 16K | |
SI_EC 512K | |
SI_ME | |
} | |
SI_BIOS 23M { | |
RW_SECTION_A 6M { | |
VBLOCK_A 64K | |
FW_MAIN_A(CBFS) | |
RW_FWID_A 64 | |
ME_RW_A(CBFS) 3008K | |
} | |
RW_LEGACY(CBFS) 2M | |
RW_MISC 1M { | |
UNIFIED_MRC_CACHE 128K { | |
RECOVERY_MRC_CACHE 64K | |
RW_MRC_CACHE 64K | |
} | |
RW_ELOG(PRESERVE) 16K | |
RW_SHARED 16K { | |
SHARED_DATA 8K | |
VBLOCK_DEV 8K | |
} | |
RW_VPD(PRESERVE) 8K | |
RW_NVRAM(PRESERVE) 24K | |
} | |
RW_SECTION_B 6M { | |
VBLOCK_B 64K | |
FW_MAIN_B(CBFS) | |
RW_FWID_B 64 | |
ME_RW_B(CBFS) 3008K | |
} | |
# Make WP_RO region align with SPI vendor | |
# memory protected range specification. | |
WP_RO 8M { | |
RO_VPD(PRESERVE) 16K | |
RO_SECTION { | |
FMAP 2K | |
RO_FRID 64 | |
GBB@4K 12K | |
COREBOOT(CBFS) | |
} | |
} | |
} | |
} |