sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASE
Make it default to 0x400, which is what the touched southbridges use.
Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/src/mainboard/asus/p8z77-m_pro/early_init.c b/src/mainboard/asus/p8z77-m_pro/early_init.c
index 87da010..41db74c 100644
--- a/src/mainboard/asus/p8z77-m_pro/early_init.c
+++ b/src/mainboard/asus/p8z77-m_pro/early_init.c
@@ -89,7 +89,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c
index df51f66..d00573a 100644
--- a/src/mainboard/google/butterfly/early_init.c
+++ b/src/mainboard/google/butterfly/early_init.c
@@ -83,7 +83,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c
index 8360f2a..beda899 100644
--- a/src/mainboard/google/link/early_init.c
+++ b/src/mainboard/google/link/early_init.c
@@ -90,7 +90,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c
index 3c5c363..c8e467a 100644
--- a/src/mainboard/google/parrot/early_init.c
+++ b/src/mainboard/google/parrot/early_init.c
@@ -58,7 +58,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c
index e71d0ee..93d7875 100644
--- a/src/mainboard/google/stout/early_init.c
+++ b/src/mainboard/google/stout/early_init.c
@@ -95,7 +95,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index e81b4b6..c9f3dcd 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -18,7 +18,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 119346e..b3802f7 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -55,7 +55,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c
index 669577e..c326795 100644
--- a/src/mainboard/kontron/ktqm77/early_init.c
+++ b/src/mainboard/kontron/ktqm77/early_init.c
@@ -58,7 +58,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c
index e4c854c..c0fece9 100644
--- a/src/mainboard/lenovo/x220/early_init.c
+++ b/src/mainboard/lenovo/x220/early_init.c
@@ -16,7 +16,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/roda/rv11/variants/rv11/early_init.c b/src/mainboard/roda/rv11/variants/rv11/early_init.c
index ada4b9f..4c20ee2 100644
--- a/src/mainboard/roda/rv11/variants/rv11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rv11/early_init.c
@@ -14,7 +14,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/roda/rv11/variants/rw11/early_init.c b/src/mainboard/roda/rv11/variants/rw11/early_init.c
index f56a5e4..c2c9a12 100644
--- a/src/mainboard/roda/rv11/variants/rw11/early_init.c
+++ b/src/mainboard/roda/rv11/variants/rw11/early_init.c
@@ -44,7 +44,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c
index 091cbc5..a3bf7a6 100644
--- a/src/mainboard/samsung/lumpy/early_init.c
+++ b/src/mainboard/samsung/lumpy/early_init.c
@@ -121,7 +121,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c
index f079482..7e95a8b 100644
--- a/src/mainboard/samsung/stumpy/early_init.c
+++ b/src/mainboard/samsung/stumpy/early_init.c
@@ -105,7 +105,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.wdbbar = 0x4000000,
.wdbsize = 0x1000,
.hpet_address = CONFIG_HPET_ADDRESS,
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 39babf5..5b025eb 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -51,7 +51,7 @@
.dmibar = (uintptr_t)DEFAULT_DMIBAR,
.epbar = DEFAULT_EPBAR,
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
- .smbusbar = SMBUS_IO_BASE,
+ .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE,
.hpet_address = HPET_ADDR,
.rcba = (uintptr_t)DEFAULT_RCBA,
.pmbase = DEFAULT_PMBASE,
diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 1ec54b3..e1fe7c8 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -251,7 +251,7 @@
{
const struct device *dev = pcidev_on_root(0x19, 0);
- pei_data->smbusbar = SMBUS_IO_BASE;
+ pei_data->smbusbar = CONFIG_FIXED_SMBUS_IO_BASE;
pei_data->wdbbar = 0x04000000;
pei_data->wdbsize = 0x1000;
pei_data->rcba = (uintptr_t)DEFAULT_RCBABASE;
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 7d8503b..85f20a7 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index ed75505..b7842c0 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -21,11 +21,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index dcd2724..7a00cf4 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -60,7 +60,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig
index 9356a2b..195e715 100644
--- a/src/southbridge/intel/common/Kconfig
+++ b/src/southbridge/intel/common/Kconfig
@@ -97,3 +97,8 @@
config SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
bool
depends on SOUTHBRIDGE_INTEL_COMMON_PMBASE
+
+config FIXED_SMBUS_IO_BASE
+ hex
+ depends on SOUTHBRIDGE_INTEL_COMMON_SMBUS
+ default 0x400
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 6649c33..fc225b0 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -12,7 +12,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h
index cf85274..d5790ae 100644
--- a/src/southbridge/intel/i82801dx/i82801dx.h
+++ b/src/southbridge/intel/i82801dx/i82801dx.h
@@ -94,8 +94,6 @@
#define RTC_FAILED (1 <<2)
-#define SMBUS_IO_BASE 0x400
-
#define PM1_STS 0x00
#define WAK_STS (1 << 15)
#define PCIEXPWAK_STS (1 << 14)
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 48d9d58..55cb372 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -7,7 +7,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index fbb6bf1..86330f8 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -7,11 +7,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
#define DEFAULT_PMBASE 0x0500
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index e1e53c2..6b63959 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -68,7 +68,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index ba0b0c8..6731a02 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h
index 08b94c7..ff94809c 100644
--- a/src/southbridge/intel/i82801ix/i82801ix.h
+++ b/src/southbridge/intel/i82801ix/i82801ix.h
@@ -80,8 +80,6 @@
#define D28Fx_SLCAP 0x54
-#define SMBUS_IO_BASE 0x0400
-
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 883c964..a2df123 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -424,7 +424,7 @@
* 0x00c0 ~ 0x00de....ISA DMA
* 0x00c1 ~ 0x00df....ISA DMA aliases
* 0x00f0.............Coprocessor Error
- * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+ * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
* 0x04d0 - 0x04d1....PIC
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c
index c348ed8..815705d 100644
--- a/src/southbridge/intel/i82801ix/smbus.c
+++ b/src/southbridge/intel/i82801ix/smbus.c
@@ -49,7 +49,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
index 55b9854..c4b82bb 100644
--- a/src/southbridge/intel/i82801jx/early_smbus.c
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -7,7 +7,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h
index a88c19e..0a353de 100644
--- a/src/southbridge/intel/i82801jx/i82801jx.h
+++ b/src/southbridge/intel/i82801jx/i82801jx.h
@@ -83,8 +83,6 @@
#define D28Fx_SLCAP 0x54
-#define SMBUS_IO_BASE 0x0400
-
/* PCI Configuration Space (D31:F3): SMBus */
#define SMB_BASE 0x20
#define HOSTC 0x40
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c
index 2533d8c..fceeb3f 100644
--- a/src/southbridge/intel/i82801jx/lpc.c
+++ b/src/southbridge/intel/i82801jx/lpc.c
@@ -451,7 +451,7 @@
* 0x00c0 ~ 0x00de....ISA DMA
* 0x00c1 ~ 0x00df....ISA DMA aliases
* 0x00f0.............Coprocessor Error
- * (0x0400-0x041f)....SMBus (SMBUS_IO_BASE, during raminit)
+ * (0x0400-0x041f)....SMBus (CONFIG_FIXED_SMBUS_IO_BASE, during raminit)
* 0x04d0 - 0x04d1....PIC
* 0x0500 - 0x057f....PM (DEFAULT_PMBASE)
* 0x0580 - 0x05bf....SB GPIO (DEFAULT_GPIOBASE)
diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c
index 32b64b8..6595635 100644
--- a/src/southbridge/intel/i82801jx/smbus.c
+++ b/src/southbridge/intel/i82801jx/smbus.c
@@ -76,7 +76,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index 7d8503b..85f20a7 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h
index d0f1314..437259c 100644
--- a/src/southbridge/intel/ibexpeak/pch.h
+++ b/src/southbridge/intel/ibexpeak/pch.h
@@ -22,11 +22,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
/* TODO Make sure these don't get changed by stage2 */
#define DEFAULT_GPIOBASE 0x0480
diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 7e9aa57..01001c3 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -59,7 +59,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 7d8503b..85f20a7 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -8,7 +8,7 @@
uintptr_t smbus_base(void)
{
- return SMBUS_IO_BASE;
+ return CONFIG_FIXED_SMBUS_IO_BASE;
}
int smbus_enable_iobar(uintptr_t base)
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index db3d92a..9946944 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -47,11 +47,10 @@
* It does not matter where we put the SMBus I/O base, as long as we
* keep it consistent and don't interfere with other devices. Stage2
* will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * Our solution is to have SMB initialization move the I/O to CONFIG_FIXED_SMBUS_IO_BASE
* again. But handling static BARs is a generic problem that should be
* solved in the device allocator.
*/
-#define SMBUS_IO_BASE 0x0400
#define SMBUS_SLAVE_ADDR 0x24
#if CONFIG(INTEL_LYNXPOINT_LP)
diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c
index 39003f6..22bf75a 100644
--- a/src/southbridge/intel/lynxpoint/smbus.c
+++ b/src/southbridge/intel/lynxpoint/smbus.c
@@ -58,7 +58,7 @@
static void smbus_read_resources(struct device *dev)
{
struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
- res->base = SMBUS_IO_BASE;
+ res->base = CONFIG_FIXED_SMBUS_IO_BASE;
res->size = 32;
res->limit = res->base + res->size - 1;
res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |