soc/intel/braswell: Clean up
Tested with BUILD_TIMELESS=1, Facebook FBG1701 remains unaffected.
Change-Id: I784a5ddc1a8dcbfb960ce970b28b850244a47773
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39663
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/braswell/acpi.c b/src/soc/intel/braswell/acpi.c
index 413b997..765be82 100644
--- a/src/soc/intel/braswell/acpi.c
+++ b/src/soc/intel/braswell/acpi.c
@@ -250,13 +250,13 @@
static acpi_tstate_t soc_tss_table[] = {
{ 100, 1000, 0, 0x00, 0 },
- { 88, 875, 0, 0x1e, 0 },
- { 75, 750, 0, 0x1c, 0 },
- { 63, 625, 0, 0x1a, 0 },
- { 50, 500, 0, 0x18, 0 },
- { 38, 375, 0, 0x16, 0 },
- { 25, 250, 0, 0x14, 0 },
- { 13, 125, 0, 0x12, 0 },
+ { 88, 875, 0, 0x1e, 0 },
+ { 75, 750, 0, 0x1c, 0 },
+ { 63, 625, 0, 0x1a, 0 },
+ { 50, 500, 0, 0x18, 0 },
+ { 38, 375, 0, 0x16, 0 },
+ { 25, 250, 0, 0x14, 0 },
+ { 13, 125, 0, 0x12, 0 },
};
static void generate_t_state_entries(int core, int cores_per_package)
@@ -271,24 +271,23 @@
acpigen_write_TPC("\\TLVL");
/* Write TSS table for MSR access */
- acpigen_write_TSS_package(
- ARRAY_SIZE(soc_tss_table), soc_tss_table);
+ acpigen_write_TSS_package(ARRAY_SIZE(soc_tss_table), soc_tss_table);
}
static int calculate_power(int tdp, int p1_ratio, int ratio)
{
- u32 m;
- u32 power;
+ u32 m, power;
/*
* M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
- *
- * Power = (ratio / p1_ratio) * m * tdp
*/
m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
m = (m * m) / 1000;
+ /*
+ * Power = (ratio / p1_ratio) * m * TDP
+ */
power = ((ratio * 100000 / p1_ratio) / 100);
power *= (m / 100) * (tdp / 1000);
power /= 1000;
@@ -387,8 +386,8 @@
ratio >= ratio_min; ratio -= ratio_step) {
/* Calculate VID for this ratio */
- vid = ((ratio - ratio_min) * vid_range_2) /
- ratio_range_2 + vid_min;
+ vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
+
/* Round up if remainder */
if (((ratio - ratio_min) * vid_range_2) % ratio_range_2)
vid++;
@@ -424,20 +423,16 @@
}
/* Generate processor \_PR.CPUx */
- acpigen_write_processor(
- core, pcontrol_blk, plen);
+ acpigen_write_processor(core, pcontrol_blk, plen);
/* Generate P-state tables */
- generate_p_state_entries(
- core, pattrs->num_cpus);
+ generate_p_state_entries(core, pattrs->num_cpus);
/* Generate C-state tables */
- acpigen_write_CST_package(
- cstate_map, ARRAY_SIZE(cstate_map));
+ acpigen_write_CST_package(cstate_map, ARRAY_SIZE(cstate_map));
/* Generate T-state tables */
- generate_t_state_entries(
- core, pattrs->num_cpus);
+ generate_t_state_entries(core, pattrs->num_cpus);
acpigen_pop_len();
}
@@ -466,8 +461,7 @@
sci_flags |= MP_IRQ_POLARITY_HIGH;
irqovr = (void *)current;
- current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq,
- sci_flags);
+ current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, sci_flags);
return current;
}
@@ -480,8 +474,7 @@
return 0;
}
-unsigned long southcluster_write_acpi_tables(struct device *device,
- unsigned long current,
+unsigned long southcluster_write_acpi_tables(struct device *device, unsigned long current,
struct acpi_rsdp *rsdp)
{
acpi_header_t *ssdt2;
@@ -511,9 +504,9 @@
if (ssdt2->length) {
current += ssdt2->length;
acpi_add_table(rsdp, ssdt2);
- printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2,
- ssdt2->length);
+ printk(BIOS_DEBUG, "ACPI: * SSDT2 @ %p Length %x\n", ssdt2, ssdt2->length);
current = acpi_align_current(current);
+
} else {
ssdt2 = NULL;
printk(BIOS_DEBUG, "ACPI: * SSDT2 not generated.\n");
@@ -537,15 +530,17 @@
if (gnvs) {
acpi_create_gnvs(gnvs);
- /* Fill in the Wifi Region id */
+
+ /* Fill in the Wi-Fi Region ID */
if (CONFIG(HAVE_REGULATORY_DOMAIN))
gnvs->cid1 = wifi_regulatory_domain();
else
gnvs->cid1 = WRDD_DEFAULT_REGULATORY_DOMAIN;
+
/* And tell SMI about it */
smm_setup_structures(gnvs, NULL, NULL);
- /* Add it to DSDT. */
+ /* Add it to DSDT */
acpigen_write_scope("\\");
acpigen_write_name_dword("NVSA", (u32) gnvs);
acpigen_pop_len();
diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c
index 11bff97..aa8df6b 100644
--- a/src/soc/intel/braswell/bootblock/bootblock.c
+++ b/src/soc/intel/braswell/bootblock/bootblock.c
@@ -90,11 +90,8 @@
int rtc_failed = rtc_failure();
if (rtc_failed) {
- printk(BIOS_ERR,
- "RTC Failure detected. Resetting date to %x/%x/%x%x\n",
- COREBOOT_BUILD_MONTH_BCD,
- COREBOOT_BUILD_DAY_BCD,
- 0x20,
+ printk(BIOS_ERR, "RTC Failure detected. Resetting date to %x/%x/%x%x\n",
+ COREBOOT_BUILD_MONTH_BCD, COREBOOT_BUILD_DAY_BCD, 0x20,
COREBOOT_BUILD_YEAR_BCD);
}
@@ -106,10 +103,9 @@
uint32_t reg;
/*
- * Set up the MMCONF range. The register lives in the BUNIT. The
- * IO variant of the config access needs to be used initially to
- * properly configure as the IOSF access registers live in PCI
- * config space.
+ * Set up the MMCONF range. The register lives in the BUNIT. The IO variant of the
+ * config access needs to be used initially to properly configure as the IOSF access
+ * registers live in PCI config space.
*/
reg = 0;
/* Clear the extended register. */
@@ -124,7 +120,7 @@
void bootblock_soc_early_init(void)
{
- /* Allow memory-mapped PCI config access. */
+ /* Allow memory-mapped PCI config access */
setup_mmconfig();
/* Early chipset initialization */
diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c
index e1918d4..90ee850 100644
--- a/src/soc/intel/braswell/chip.c
+++ b/src/soc/intel/braswell/chip.c
@@ -24,8 +24,7 @@
static void pci_domain_set_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
assign_resources(dev->link_list);
}
@@ -47,16 +46,15 @@
static void enable_dev(struct device *dev)
{
- printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n",
- __FILE__, __func__,
+ printk(BIOS_SPEW, "----------\n%s/%s (%s), type: %d\n", __FILE__, __func__,
dev_name(dev), dev->path.type);
+
printk(BIOS_SPEW, "vendor: 0x%04x. device: 0x%04x\n",
pci_read_config16(dev, PCI_VENDOR_ID),
pci_read_config16(dev, PCI_DEVICE_ID));
- printk(BIOS_SPEW, "class: 0x%02x %s\n"
- "subclass: 0x%02x %s\n"
- "prog: 0x%02x\n"
- "revision: 0x%02x\n",
+
+ printk(BIOS_SPEW, "class: 0x%02x %s\nsubclass: 0x%02x %s\n"
+ "prog: 0x%02x\nrevision: 0x%02x\n",
pci_read_config16(dev, PCI_CLASS_DEVICE) >> 8,
get_pci_class_name(dev),
pci_read_config16(dev, PCI_CLASS_DEVICE) & 0xff,
@@ -67,8 +65,10 @@
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN) {
dev->ops = &pci_domain_ops;
+
} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
dev->ops = &cpu_bus_ops;
+
} else if (dev->path.type == DEVICE_PATH_PCI) {
/* Handle south cluster enablement. */
if (PCI_SLOT(dev->path.pci.devfn) > GFX_DEV &&
@@ -88,9 +88,8 @@
struct soc_intel_braswell_config *config;
if (!dev) {
- printk(BIOS_ERR,
- "Error! Device (%s) not found, "
- "soc_silicon_init_params!\n", dev_path(dev));
+ printk(BIOS_ERR, "Error! Device (%s) not found, soc_silicon_init_params!\n",
+ dev_path(dev));
return;
}
@@ -98,83 +97,81 @@
/* Set the parameters for SiliconInit */
printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n");
- params->PcdSdcardMode = config->PcdSdcardMode;
- params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
- params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
- params->PcdEnableAzalia = config->PcdEnableAzalia;
- params->PcdEnableSata = config->PcdEnableSata;
- params->PcdEnableXhci = config->PcdEnableXhci;
- params->PcdEnableLpe = config->PcdEnableLpe;
- params->PcdEnableDma0 = config->PcdEnableDma0;
- params->PcdEnableDma1 = config->PcdEnableDma1;
- params->PcdEnableI2C0 = config->PcdEnableI2C0;
- params->PcdEnableI2C1 = config->PcdEnableI2C1;
- params->PcdEnableI2C2 = config->PcdEnableI2C2;
- params->PcdEnableI2C3 = config->PcdEnableI2C3;
- params->PcdEnableI2C4 = config->PcdEnableI2C4;
- params->PcdEnableI2C5 = config->PcdEnableI2C5;
- params->PcdEnableI2C6 = config->PcdEnableI2C6;
- params->GraphicsConfigPtr = 0;
- params->AzaliaConfigPtr = 0;
- params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
- params->ChvSvidConfig = config->ChvSvidConfig;
- params->DptfDisable = config->DptfDisable;
- params->PcdEmmcMode = config->PcdEmmcMode;
- params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
- params->PcdDispClkSsc = config->PcdDispClkSsc;
- params->PcdSataClkSsc = config->PcdSataClkSsc;
- params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
- params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
- params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn;
- params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf;
+ params->PcdSdcardMode = config->PcdSdcardMode;
+ params->PcdEnableHsuart0 = config->PcdEnableHsuart0;
+ params->PcdEnableHsuart1 = config->PcdEnableHsuart1;
+ params->PcdEnableAzalia = config->PcdEnableAzalia;
+ params->PcdEnableSata = config->PcdEnableSata;
+ params->PcdEnableXhci = config->PcdEnableXhci;
+ params->PcdEnableLpe = config->PcdEnableLpe;
+ params->PcdEnableDma0 = config->PcdEnableDma0;
+ params->PcdEnableDma1 = config->PcdEnableDma1;
+ params->PcdEnableI2C0 = config->PcdEnableI2C0;
+ params->PcdEnableI2C1 = config->PcdEnableI2C1;
+ params->PcdEnableI2C2 = config->PcdEnableI2C2;
+ params->PcdEnableI2C3 = config->PcdEnableI2C3;
+ params->PcdEnableI2C4 = config->PcdEnableI2C4;
+ params->PcdEnableI2C5 = config->PcdEnableI2C5;
+ params->PcdEnableI2C6 = config->PcdEnableI2C6;
+ params->GraphicsConfigPtr = 0;
+ params->AzaliaConfigPtr = 0;
+ params->PunitPwrConfigDisable = config->PunitPwrConfigDisable;
+ params->ChvSvidConfig = config->ChvSvidConfig;
+ params->DptfDisable = config->DptfDisable;
+ params->PcdEmmcMode = config->PcdEmmcMode;
+ params->PcdUsb3ClkSsc = config->PcdUsb3ClkSsc;
+ params->PcdDispClkSsc = config->PcdDispClkSsc;
+ params->PcdSataClkSsc = config->PcdSataClkSsc;
- params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet;
- params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet;
- params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn;
- params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf;
+ params->Usb2Port0PerPortPeTxiSet = config->Usb2Port0PerPortPeTxiSet;
+ params->Usb2Port0PerPortTxiSet = config->Usb2Port0PerPortTxiSet;
+ params->Usb2Port0IUsbTxEmphasisEn = config->Usb2Port0IUsbTxEmphasisEn;
+ params->Usb2Port0PerPortTxPeHalf = config->Usb2Port0PerPortTxPeHalf;
- params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet;
- params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet;
- params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn;
- params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf;
+ params->Usb2Port1PerPortPeTxiSet = config->Usb2Port1PerPortPeTxiSet;
+ params->Usb2Port1PerPortTxiSet = config->Usb2Port1PerPortTxiSet;
+ params->Usb2Port1IUsbTxEmphasisEn = config->Usb2Port1IUsbTxEmphasisEn;
+ params->Usb2Port1PerPortTxPeHalf = config->Usb2Port1PerPortTxPeHalf;
- params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet;
- params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet;
- params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn;
- params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf;
+ params->Usb2Port2PerPortPeTxiSet = config->Usb2Port2PerPortPeTxiSet;
+ params->Usb2Port2PerPortTxiSet = config->Usb2Port2PerPortTxiSet;
+ params->Usb2Port2IUsbTxEmphasisEn = config->Usb2Port2IUsbTxEmphasisEn;
+ params->Usb2Port2PerPortTxPeHalf = config->Usb2Port2PerPortTxPeHalf;
- params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet;
- params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet;
- params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn;
- params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf;
+ params->Usb2Port3PerPortPeTxiSet = config->Usb2Port3PerPortPeTxiSet;
+ params->Usb2Port3PerPortTxiSet = config->Usb2Port3PerPortTxiSet;
+ params->Usb2Port3IUsbTxEmphasisEn = config->Usb2Port3IUsbTxEmphasisEn;
+ params->Usb2Port3PerPortTxPeHalf = config->Usb2Port3PerPortTxPeHalf;
- params->Usb3Lane0Ow2tapgen2deemph3p5 =
- config->Usb3Lane0Ow2tapgen2deemph3p5;
- params->Usb3Lane1Ow2tapgen2deemph3p5 =
- config->Usb3Lane1Ow2tapgen2deemph3p5;
- params->Usb3Lane2Ow2tapgen2deemph3p5 =
- config->Usb3Lane2Ow2tapgen2deemph3p5;
- params->Usb3Lane3Ow2tapgen2deemph3p5 =
- config->Usb3Lane3Ow2tapgen2deemph3p5;
- params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
- params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
- params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
- params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
- params->PcdPchSsicEnable = config->PcdPchSsicEnable;
- params->PcdLogoPtr = config->PcdLogoPtr;
- params->PcdLogoSize = config->PcdLogoSize;
- params->PcdRtcLock = config->PcdRtcLock;
- params->PMIC_I2CBus = config->PMIC_I2CBus;
- params->ISPEnable = config->ISPEnable;
- params->ISPPciDevConfig = config->ISPPciDevConfig;
- params->PcdSdDetectChk = config->PcdSdDetectChk;
- params->I2C0Frequency = config->I2C0Frequency;
- params->I2C1Frequency = config->I2C1Frequency;
- params->I2C2Frequency = config->I2C2Frequency;
- params->I2C3Frequency = config->I2C3Frequency;
- params->I2C4Frequency = config->I2C4Frequency;
- params->I2C5Frequency = config->I2C5Frequency;
- params->I2C6Frequency = config->I2C6Frequency;
+ params->Usb2Port4PerPortPeTxiSet = config->Usb2Port4PerPortPeTxiSet;
+ params->Usb2Port4PerPortTxiSet = config->Usb2Port4PerPortTxiSet;
+ params->Usb2Port4IUsbTxEmphasisEn = config->Usb2Port4IUsbTxEmphasisEn;
+ params->Usb2Port4PerPortTxPeHalf = config->Usb2Port4PerPortTxPeHalf;
+
+ params->Usb3Lane0Ow2tapgen2deemph3p5 = config->Usb3Lane0Ow2tapgen2deemph3p5;
+ params->Usb3Lane1Ow2tapgen2deemph3p5 = config->Usb3Lane1Ow2tapgen2deemph3p5;
+ params->Usb3Lane2Ow2tapgen2deemph3p5 = config->Usb3Lane2Ow2tapgen2deemph3p5;
+ params->Usb3Lane3Ow2tapgen2deemph3p5 = config->Usb3Lane3Ow2tapgen2deemph3p5;
+
+ params->PcdSataInterfaceSpeed = config->PcdSataInterfaceSpeed;
+ params->PcdPchUsbSsicPort = config->PcdPchUsbSsicPort;
+ params->PcdPchUsbHsicPort = config->PcdPchUsbHsicPort;
+ params->PcdPcieRootPortSpeed = config->PcdPcieRootPortSpeed;
+ params->PcdPchSsicEnable = config->PcdPchSsicEnable;
+ params->PcdLogoPtr = config->PcdLogoPtr;
+ params->PcdLogoSize = config->PcdLogoSize;
+ params->PcdRtcLock = config->PcdRtcLock;
+ params->PMIC_I2CBus = config->PMIC_I2CBus;
+ params->ISPEnable = config->ISPEnable;
+ params->ISPPciDevConfig = config->ISPPciDevConfig;
+ params->PcdSdDetectChk = config->PcdSdDetectChk;
+ params->I2C0Frequency = config->I2C0Frequency;
+ params->I2C1Frequency = config->I2C1Frequency;
+ params->I2C2Frequency = config->I2C2Frequency;
+ params->I2C3Frequency = config->I2C3Frequency;
+ params->I2C4Frequency = config->I2C4Frequency;
+ params->I2C5Frequency = config->I2C5Frequency;
+ params->I2C6Frequency = config->I2C6Frequency;
board_silicon_USB2_override(params);
}
@@ -184,48 +181,43 @@
return fsp_load_logo(¶ms->PcdLogoPtr, ¶ms->PcdLogoSize);
}
-void soc_display_silicon_init_params(const SILICON_INIT_UPD *old,
- SILICON_INIT_UPD *new)
+void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, SILICON_INIT_UPD *new)
{
/* Display the parameters for SiliconInit */
printk(BIOS_SPEW, "UPD values for SiliconInit:\n");
- fsp_display_upd_value("PcdSdcardMode", 1, old->PcdSdcardMode,
- new->PcdSdcardMode);
- fsp_display_upd_value("PcdEnableHsuart0", 1, old->PcdEnableHsuart0,
- new->PcdEnableHsuart0);
- fsp_display_upd_value("PcdEnableHsuart1", 1, old->PcdEnableHsuart1,
- new->PcdEnableHsuart1);
- fsp_display_upd_value("PcdEnableAzalia", 1, old->PcdEnableAzalia,
- new->PcdEnableAzalia);
+
+ fsp_display_upd_value("PcdSdcardMode", 1,
+ old->PcdSdcardMode,
+ new->PcdSdcardMode);
+ fsp_display_upd_value("PcdEnableHsuart0", 1,
+ old->PcdEnableHsuart0,
+ new->PcdEnableHsuart0);
+ fsp_display_upd_value("PcdEnableHsuart1", 1,
+ old->PcdEnableHsuart1,
+ new->PcdEnableHsuart1);
+ fsp_display_upd_value("PcdEnableAzalia", 1,
+ old->PcdEnableAzalia,
+ new->PcdEnableAzalia);
fsp_display_upd_value("AzaliaConfigPtr", 4,
- (uint32_t)old->AzaliaConfigPtr,
- (uint32_t)new->AzaliaConfigPtr);
- fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata,
- new->PcdEnableSata);
- fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci,
- new->PcdEnableXhci);
- fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe,
- new->PcdEnableLpe);
- fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0,
- new->PcdEnableDma0);
- fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1,
- new->PcdEnableDma1);
- fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0,
- new->PcdEnableI2C0);
- fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1,
- new->PcdEnableI2C1);
- fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2,
- new->PcdEnableI2C2);
- fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3,
- new->PcdEnableI2C3);
- fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4,
- new->PcdEnableI2C4);
- fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5,
- new->PcdEnableI2C5);
- fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6,
- new->PcdEnableI2C6);
+ (uint32_t)old->AzaliaConfigPtr,
+ (uint32_t)new->AzaliaConfigPtr);
+
+ fsp_display_upd_value("PcdEnableSata", 1, old->PcdEnableSata, new->PcdEnableSata);
+ fsp_display_upd_value("PcdEnableXhci", 1, old->PcdEnableXhci, new->PcdEnableXhci);
+ fsp_display_upd_value("PcdEnableLpe", 1, old->PcdEnableLpe, new->PcdEnableLpe);
+ fsp_display_upd_value("PcdEnableDma0", 1, old->PcdEnableDma0, new->PcdEnableDma0);
+ fsp_display_upd_value("PcdEnableDma1", 1, old->PcdEnableDma1, new->PcdEnableDma1);
+ fsp_display_upd_value("PcdEnableI2C0", 1, old->PcdEnableI2C0, new->PcdEnableI2C0);
+ fsp_display_upd_value("PcdEnableI2C1", 1, old->PcdEnableI2C1, new->PcdEnableI2C1);
+ fsp_display_upd_value("PcdEnableI2C2", 1, old->PcdEnableI2C2, new->PcdEnableI2C2);
+ fsp_display_upd_value("PcdEnableI2C3", 1, old->PcdEnableI2C3, new->PcdEnableI2C3);
+ fsp_display_upd_value("PcdEnableI2C4", 1, old->PcdEnableI2C4, new->PcdEnableI2C4);
+ fsp_display_upd_value("PcdEnableI2C5", 1, old->PcdEnableI2C5, new->PcdEnableI2C5);
+ fsp_display_upd_value("PcdEnableI2C6", 1, old->PcdEnableI2C6, new->PcdEnableI2C6);
+
fsp_display_upd_value("PcdGraphicsConfigPtr", 4,
- old->GraphicsConfigPtr, new->GraphicsConfigPtr);
+ old->GraphicsConfigPtr,
+ new->GraphicsConfigPtr);
fsp_display_upd_value("GpioFamilyInitTablePtr", 4,
(uint32_t)old->GpioFamilyInitTablePtr,
(uint32_t)new->GpioFamilyInitTablePtr);
@@ -233,117 +225,111 @@
(uint32_t)old->GpioPadInitTablePtr,
(uint32_t)new->GpioPadInitTablePtr);
fsp_display_upd_value("PunitPwrConfigDisable", 1,
- old->PunitPwrConfigDisable,
- new->PunitPwrConfigDisable);
- fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig,
- new->ChvSvidConfig);
- fsp_display_upd_value("DptfDisable", 1, old->DptfDisable,
- new->DptfDisable);
- fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode,
- new->PcdEmmcMode);
- fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc,
- new->PcdUsb3ClkSsc);
- fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc,
- new->PcdDispClkSsc);
- fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc,
- new->PcdSataClkSsc);
+ old->PunitPwrConfigDisable,
+ new->PunitPwrConfigDisable);
+
+ fsp_display_upd_value("ChvSvidConfig", 1, old->ChvSvidConfig, new->ChvSvidConfig);
+ fsp_display_upd_value("DptfDisable", 1, old->DptfDisable, new->DptfDisable);
+ fsp_display_upd_value("PcdEmmcMode", 1, old->PcdEmmcMode, new->PcdEmmcMode);
+ fsp_display_upd_value("PcdUsb3ClkSsc", 1, old->PcdUsb3ClkSsc, new->PcdUsb3ClkSsc);
+ fsp_display_upd_value("PcdDispClkSsc", 1, old->PcdDispClkSsc, new->PcdDispClkSsc);
+ fsp_display_upd_value("PcdSataClkSsc", 1, old->PcdSataClkSsc, new->PcdSataClkSsc);
+
fsp_display_upd_value("Usb2Port0PerPortPeTxiSet", 1,
- old->Usb2Port0PerPortPeTxiSet,
- new->Usb2Port0PerPortPeTxiSet);
+ old->Usb2Port0PerPortPeTxiSet,
+ new->Usb2Port0PerPortPeTxiSet);
fsp_display_upd_value("Usb2Port0PerPortTxiSet", 1,
- old->Usb2Port0PerPortTxiSet,
- new->Usb2Port0PerPortTxiSet);
+ old->Usb2Port0PerPortTxiSet,
+ new->Usb2Port0PerPortTxiSet);
fsp_display_upd_value("Usb2Port0IUsbTxEmphasisEn", 1,
- old->Usb2Port0IUsbTxEmphasisEn,
- new->Usb2Port0IUsbTxEmphasisEn);
+ old->Usb2Port0IUsbTxEmphasisEn,
+ new->Usb2Port0IUsbTxEmphasisEn);
fsp_display_upd_value("Usb2Port0PerPortTxPeHalf", 1,
- old->Usb2Port0PerPortTxPeHalf,
- new->Usb2Port0PerPortTxPeHalf);
+ old->Usb2Port0PerPortTxPeHalf,
+ new->Usb2Port0PerPortTxPeHalf);
fsp_display_upd_value("Usb2Port1PerPortPeTxiSet", 1,
- old->Usb2Port1PerPortPeTxiSet,
- new->Usb2Port1PerPortPeTxiSet);
+ old->Usb2Port1PerPortPeTxiSet,
+ new->Usb2Port1PerPortPeTxiSet);
fsp_display_upd_value("Usb2Port1PerPortTxiSet", 1,
- old->Usb2Port1PerPortTxiSet,
- new->Usb2Port1PerPortTxiSet);
+ old->Usb2Port1PerPortTxiSet,
+ new->Usb2Port1PerPortTxiSet);
fsp_display_upd_value("Usb2Port1IUsbTxEmphasisEn", 1,
- old->Usb2Port1IUsbTxEmphasisEn,
- new->Usb2Port1IUsbTxEmphasisEn);
+ old->Usb2Port1IUsbTxEmphasisEn,
+ new->Usb2Port1IUsbTxEmphasisEn);
fsp_display_upd_value("Usb2Port1PerPortTxPeHalf", 1,
- old->Usb2Port1PerPortTxPeHalf,
- new->Usb2Port1PerPortTxPeHalf);
+ old->Usb2Port1PerPortTxPeHalf,
+ new->Usb2Port1PerPortTxPeHalf);
fsp_display_upd_value("Usb2Port2PerPortPeTxiSet", 1,
- old->Usb2Port2PerPortPeTxiSet,
- new->Usb2Port2PerPortPeTxiSet);
+ old->Usb2Port2PerPortPeTxiSet,
+ new->Usb2Port2PerPortPeTxiSet);
fsp_display_upd_value("Usb2Port2PerPortTxiSet", 1,
- old->Usb2Port2PerPortTxiSet,
- new->Usb2Port2PerPortTxiSet);
+ old->Usb2Port2PerPortTxiSet,
+ new->Usb2Port2PerPortTxiSet);
fsp_display_upd_value("Usb2Port2IUsbTxEmphasisEn", 1,
- old->Usb2Port2IUsbTxEmphasisEn,
- new->Usb2Port2IUsbTxEmphasisEn);
+ old->Usb2Port2IUsbTxEmphasisEn,
+ new->Usb2Port2IUsbTxEmphasisEn);
fsp_display_upd_value("Usb2Port2PerPortTxPeHalf", 1,
- old->Usb2Port2PerPortTxPeHalf,
- new->Usb2Port2PerPortTxPeHalf);
+ old->Usb2Port2PerPortTxPeHalf,
+ new->Usb2Port2PerPortTxPeHalf);
fsp_display_upd_value("Usb2Port3PerPortPeTxiSet", 1,
- old->Usb2Port3PerPortPeTxiSet,
- new->Usb2Port3PerPortPeTxiSet);
+ old->Usb2Port3PerPortPeTxiSet,
+ new->Usb2Port3PerPortPeTxiSet);
fsp_display_upd_value("Usb2Port3PerPortTxiSet", 1,
- old->Usb2Port3PerPortTxiSet,
- new->Usb2Port3PerPortTxiSet);
+ old->Usb2Port3PerPortTxiSet,
+ new->Usb2Port3PerPortTxiSet);
fsp_display_upd_value("Usb2Port3IUsbTxEmphasisEn", 1,
- old->Usb2Port3IUsbTxEmphasisEn,
- new->Usb2Port3IUsbTxEmphasisEn);
+ old->Usb2Port3IUsbTxEmphasisEn,
+ new->Usb2Port3IUsbTxEmphasisEn);
fsp_display_upd_value("Usb2Port3PerPortTxPeHalf", 1,
- old->Usb2Port3PerPortTxPeHalf,
- new->Usb2Port3PerPortTxPeHalf);
+ old->Usb2Port3PerPortTxPeHalf,
+ new->Usb2Port3PerPortTxPeHalf);
fsp_display_upd_value("Usb2Port4PerPortPeTxiSet", 1,
- old->Usb2Port4PerPortPeTxiSet,
- new->Usb2Port4PerPortPeTxiSet);
+ old->Usb2Port4PerPortPeTxiSet,
+ new->Usb2Port4PerPortPeTxiSet);
fsp_display_upd_value("Usb2Port4PerPortTxiSet", 1,
- old->Usb2Port4PerPortTxiSet,
- new->Usb2Port4PerPortTxiSet);
+ old->Usb2Port4PerPortTxiSet,
+ new->Usb2Port4PerPortTxiSet);
fsp_display_upd_value("Usb2Port4IUsbTxEmphasisEn", 1,
- old->Usb2Port4IUsbTxEmphasisEn,
- new->Usb2Port4IUsbTxEmphasisEn);
+ old->Usb2Port4IUsbTxEmphasisEn,
+ new->Usb2Port4IUsbTxEmphasisEn);
fsp_display_upd_value("Usb2Port4PerPortTxPeHalf", 1,
- old->Usb2Port4PerPortTxPeHalf,
- new->Usb2Port4PerPortTxPeHalf);
+ old->Usb2Port4PerPortTxPeHalf,
+ new->Usb2Port4PerPortTxPeHalf);
fsp_display_upd_value("Usb3Lane0Ow2tapgen2deemph3p5", 1,
- old->Usb3Lane0Ow2tapgen2deemph3p5,
- new->Usb3Lane0Ow2tapgen2deemph3p5);
+ old->Usb3Lane0Ow2tapgen2deemph3p5,
+ new->Usb3Lane0Ow2tapgen2deemph3p5);
fsp_display_upd_value("Usb3Lane1Ow2tapgen2deemph3p5", 1,
- old->Usb3Lane1Ow2tapgen2deemph3p5,
- new->Usb3Lane1Ow2tapgen2deemph3p5);
+ old->Usb3Lane1Ow2tapgen2deemph3p5,
+ new->Usb3Lane1Ow2tapgen2deemph3p5);
fsp_display_upd_value("Usb3Lane2Ow2tapgen2deemph3p5", 1,
- old->Usb3Lane2Ow2tapgen2deemph3p5,
- new->Usb3Lane2Ow2tapgen2deemph3p5);
+ old->Usb3Lane2Ow2tapgen2deemph3p5,
+ new->Usb3Lane2Ow2tapgen2deemph3p5);
fsp_display_upd_value("Usb3Lane3Ow2tapgen2deemph3p5", 1,
- old->Usb3Lane3Ow2tapgen2deemph3p5,
- new->Usb3Lane3Ow2tapgen2deemph3p5);
+ old->Usb3Lane3Ow2tapgen2deemph3p5,
+ new->Usb3Lane3Ow2tapgen2deemph3p5);
fsp_display_upd_value("PcdSataInterfaceSpeed", 1,
- old->PcdSataInterfaceSpeed,
- new->PcdSataInterfaceSpeed);
+ old->PcdSataInterfaceSpeed,
+ new->PcdSataInterfaceSpeed);
fsp_display_upd_value("PcdPchUsbSsicPort", 1,
- old->PcdPchUsbSsicPort, new->PcdPchUsbSsicPort);
+ old->PcdPchUsbSsicPort,
+ new->PcdPchUsbSsicPort);
fsp_display_upd_value("PcdPchUsbHsicPort", 1,
- old->PcdPchUsbHsicPort, new->PcdPchUsbHsicPort);
+ old->PcdPchUsbHsicPort,
+ new->PcdPchUsbHsicPort);
fsp_display_upd_value("PcdPcieRootPortSpeed", 1,
- old->PcdPcieRootPortSpeed, new->PcdPcieRootPortSpeed);
- fsp_display_upd_value("PcdPchSsicEnable", 1, old->PcdPchSsicEnable,
- new->PcdPchSsicEnable);
- fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr,
- new->PcdLogoPtr);
- fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize,
- new->PcdLogoSize);
- fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock,
- new->PcdRtcLock);
- fsp_display_upd_value("PMIC_I2CBus", 1,
- old->PMIC_I2CBus, new->PMIC_I2CBus);
- fsp_display_upd_value("ISPEnable", 1,
- old->ISPEnable, new->ISPEnable);
- fsp_display_upd_value("ISPPciDevConfig", 1,
- old->ISPPciDevConfig, new->ISPPciDevConfig);
- fsp_display_upd_value("PcdSdDetectChk", 1,
- old->PcdSdDetectChk, new->PcdSdDetectChk);
+ old->PcdPcieRootPortSpeed,
+ new->PcdPcieRootPortSpeed);
+ fsp_display_upd_value("PcdPchSsicEnable", 1,
+ old->PcdPchSsicEnable,
+ new->PcdPchSsicEnable);
+
+ fsp_display_upd_value("PcdLogoPtr", 4, old->PcdLogoPtr, new->PcdLogoPtr);
+ fsp_display_upd_value("PcdLogoSize", 4, old->PcdLogoSize, new->PcdLogoSize);
+ fsp_display_upd_value("PcdRtcLock", 1, old->PcdRtcLock, new->PcdRtcLock);
+ fsp_display_upd_value("PMIC_I2CBus", 1, old->PMIC_I2CBus, new->PMIC_I2CBus);
+ fsp_display_upd_value("ISPEnable", 1, old->ISPEnable, new->ISPEnable);
+ fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig);
+ fsp_display_upd_value("PcdSdDetectChk", 1, old->PcdSdDetectChk, new->PcdSdDetectChk);
}
/* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */
@@ -356,7 +342,7 @@
struct chip_operations soc_intel_braswell_ops = {
CHIP_NAME("Intel Braswell SoC")
.enable_dev = enable_dev,
- .init = soc_init,
+ .init = soc_init,
};
struct pci_operations soc_pci_ops = {
@@ -371,74 +357,74 @@
int SocStepping(void)
{
struct device *dev = pcidev_on_root(LPC_DEV, LPC_FUNC);
- u8 revid = pci_read_config8(dev, 0x8);
+ const u8 revid = pci_read_config8(dev, 0x8);
switch (revid & B_PCH_LPC_RID_STEPPING_MASK) {
case V_PCH_LPC_RID_A0:
- return SocA0;
+ return SocA0;
case V_PCH_LPC_RID_A1:
- return SocA1;
+ return SocA1;
case V_PCH_LPC_RID_A2:
- return SocA2;
+ return SocA2;
case V_PCH_LPC_RID_A3:
- return SocA3;
+ return SocA3;
case V_PCH_LPC_RID_A4:
- return SocA4;
+ return SocA4;
case V_PCH_LPC_RID_A5:
- return SocA5;
+ return SocA5;
case V_PCH_LPC_RID_A6:
- return SocA6;
+ return SocA6;
case V_PCH_LPC_RID_A7:
- return SocA7;
+ return SocA7;
case V_PCH_LPC_RID_B0:
- return SocB0;
+ return SocB0;
case V_PCH_LPC_RID_B1:
- return SocB1;
+ return SocB1;
case V_PCH_LPC_RID_B2:
- return SocB2;
+ return SocB2;
case V_PCH_LPC_RID_B3:
- return SocB3;
+ return SocB3;
case V_PCH_LPC_RID_B4:
- return SocB4;
+ return SocB4;
case V_PCH_LPC_RID_B5:
- return SocB5;
+ return SocB5;
case V_PCH_LPC_RID_B6:
- return SocB6;
+ return SocB6;
case V_PCH_LPC_RID_B7:
- return SocB7;
+ return SocB7;
case V_PCH_LPC_RID_C0:
- return SocC0;
+ return SocC0;
case V_PCH_LPC_RID_C1:
- return SocC1;
+ return SocC1;
case V_PCH_LPC_RID_C2:
- return SocC2;
+ return SocC2;
case V_PCH_LPC_RID_C3:
- return SocC3;
+ return SocC3;
case V_PCH_LPC_RID_C4:
- return SocC4;
+ return SocC4;
case V_PCH_LPC_RID_C5:
- return SocC5;
+ return SocC5;
case V_PCH_LPC_RID_C6:
- return SocC6;
+ return SocC6;
case V_PCH_LPC_RID_C7:
- return SocC7;
+ return SocC7;
case V_PCH_LPC_RID_D0:
- return SocD0;
+ return SocD0;
case V_PCH_LPC_RID_D1:
- return SocD1;
+ return SocD1;
case V_PCH_LPC_RID_D2:
- return SocD2;
+ return SocD2;
case V_PCH_LPC_RID_D3:
- return SocD3;
+ return SocD3;
case V_PCH_LPC_RID_D4:
- return SocD4;
+ return SocD4;
case V_PCH_LPC_RID_D5:
- return SocD5;
+ return SocD5;
case V_PCH_LPC_RID_D6:
- return SocD6;
+ return SocD6;
case V_PCH_LPC_RID_D7:
- return SocD7;
+ return SocD7;
default:
- return SocSteppingMax;
+ return SocSteppingMax;
}
}
diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h
index be95808..026e491 100644
--- a/src/soc/intel/braswell/chip.h
+++ b/src/soc/intel/braswell/chip.h
@@ -58,13 +58,13 @@
enum serirq_mode serirq_mode;
- /* Disable SLP_X stretching after SUS power well loss. */
+ /* Disable SLP_X stretching after SUS power well loss */
int disable_slp_x_stretch_sus_fail;
- /* LPE Audio Clock configuration. */
- enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz */
+ /* LPE Audio Clock configuration */
+ enum lpe_clk_src lpe_codec_clk_src; /* Both are 19.2MHz */
- /* Native SD Card controller - override controller capabilities. */
+ /* Native SD Card controller - override controller capabilities */
uint32_t sdcard_cap_low;
uint32_t sdcard_cap_high;
@@ -74,7 +74,7 @@
int sd_acpi_mode;
int lpe_acpi_mode;
- /* Allow PCIe devices to wake system from suspend. */
+ /* Allow PCIe devices to wake system from suspend */
int pcie_wake_enable;
/* Program USB2_COMPBG register.
@@ -84,94 +84,91 @@
*/
enum usb_comp_bg_value usb_comp_bg;
+ /*
+ * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
+ * These are configuration values that are passed to FSP during MemoryInit.
+ */
+ uint16_t PcdMrcInitTsegSize;
+ uint16_t PcdMrcInitMmioSize;
+ uint8_t PcdMrcInitSpdAddr1;
+ uint8_t PcdMrcInitSpdAddr2;
+ uint8_t PcdIgdDvmt50PreAlloc;
+ uint8_t PcdApertureSize;
+ uint8_t PcdGttSize;
+ uint8_t PcdLegacySegDecode;
+ uint8_t PcdDvfsEnable;
+ uint8_t PcdCaMirrorEn; /* Command Address Mirroring Enabled */
/*
* The following fields come from fsp_vpd.h .aka. VpdHeader.h.
- * These are configuration values that are passed to FSP during
- * MemoryInit.
+ * These are configuration values that are passed to FSP during SiliconInit.
*/
- UINT16 PcdMrcInitTsegSize;
- UINT16 PcdMrcInitMmioSize;
- UINT8 PcdMrcInitSpdAddr1;
- UINT8 PcdMrcInitSpdAddr2;
- UINT8 PcdIgdDvmt50PreAlloc;
- UINT8 PcdApertureSize;
- UINT8 PcdGttSize;
- UINT8 PcdLegacySegDecode;
- UINT8 PcdDvfsEnable;
- UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */
-
- /*
- * The following fields come from fsp_vpd.h .aka. VpdHeader.h.
- * These are configuration values that are passed to FSP during
- * SiliconInit.
- */
- UINT8 PcdSdcardMode;
- UINT8 PcdEnableHsuart0;
- UINT8 PcdEnableHsuart1;
- UINT8 PcdEnableAzalia;
- UINT8 PcdEnableSata;
- UINT8 PcdEnableXhci;
- UINT8 PcdEnableLpe;
- UINT8 PcdEnableDma0;
- UINT8 PcdEnableDma1;
- UINT8 PcdEnableI2C0;
- UINT8 PcdEnableI2C1;
- UINT8 PcdEnableI2C2;
- UINT8 PcdEnableI2C3;
- UINT8 PcdEnableI2C4;
- UINT8 PcdEnableI2C5;
- UINT8 PcdEnableI2C6;
- UINT8 PunitPwrConfigDisable;
- UINT8 ChvSvidConfig;
- UINT8 DptfDisable;
- UINT8 PcdEmmcMode;
- UINT8 PcdUsb3ClkSsc;
- UINT8 PcdDispClkSsc;
- UINT8 PcdSataClkSsc;
- UINT8 Usb2Port0PerPortPeTxiSet;
- UINT8 Usb2Port0PerPortTxiSet;
- UINT8 Usb2Port0IUsbTxEmphasisEn;
- UINT8 Usb2Port0PerPortTxPeHalf;
- UINT8 Usb2Port1PerPortPeTxiSet;
- UINT8 Usb2Port1PerPortTxiSet;
- UINT8 Usb2Port1IUsbTxEmphasisEn;
- UINT8 Usb2Port1PerPortTxPeHalf;
- UINT8 Usb2Port2PerPortPeTxiSet;
- UINT8 Usb2Port2PerPortTxiSet;
- UINT8 Usb2Port2IUsbTxEmphasisEn;
- UINT8 Usb2Port2PerPortTxPeHalf;
- UINT8 Usb2Port3PerPortPeTxiSet;
- UINT8 Usb2Port3PerPortTxiSet;
- UINT8 Usb2Port3IUsbTxEmphasisEn;
- UINT8 Usb2Port3PerPortTxPeHalf;
- UINT8 Usb2Port4PerPortPeTxiSet;
- UINT8 Usb2Port4PerPortTxiSet;
- UINT8 Usb2Port4IUsbTxEmphasisEn;
- UINT8 Usb2Port4PerPortTxPeHalf;
- UINT8 Usb3Lane0Ow2tapgen2deemph3p5;
- UINT8 Usb3Lane1Ow2tapgen2deemph3p5;
- UINT8 Usb3Lane2Ow2tapgen2deemph3p5;
- UINT8 Usb3Lane3Ow2tapgen2deemph3p5;
- UINT8 PcdSataInterfaceSpeed;
- UINT8 PcdPchUsbSsicPort;
- UINT8 PcdPchUsbHsicPort;
- UINT8 PcdPcieRootPortSpeed;
- UINT8 PcdPchSsicEnable;
- UINT32 PcdLogoPtr;
- UINT32 PcdLogoSize;
- UINT8 PcdRtcLock;
- UINT8 PMIC_I2CBus;
- UINT8 ISPEnable;
- UINT8 ISPPciDevConfig;
- UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/
- UINT8 I2C0Frequency; /* 0 - 100Khz, 1 - 400Khz, 2 - 1Mhz */
- UINT8 I2C1Frequency;
- UINT8 I2C2Frequency;
- UINT8 I2C3Frequency;
- UINT8 I2C4Frequency;
- UINT8 I2C5Frequency;
- UINT8 I2C6Frequency;
+ uint8_t PcdSdcardMode;
+ uint8_t PcdEnableHsuart0;
+ uint8_t PcdEnableHsuart1;
+ uint8_t PcdEnableAzalia;
+ uint8_t PcdEnableSata;
+ uint8_t PcdEnableXhci;
+ uint8_t PcdEnableLpe;
+ uint8_t PcdEnableDma0;
+ uint8_t PcdEnableDma1;
+ uint8_t PcdEnableI2C0;
+ uint8_t PcdEnableI2C1;
+ uint8_t PcdEnableI2C2;
+ uint8_t PcdEnableI2C3;
+ uint8_t PcdEnableI2C4;
+ uint8_t PcdEnableI2C5;
+ uint8_t PcdEnableI2C6;
+ uint8_t PunitPwrConfigDisable;
+ uint8_t ChvSvidConfig;
+ uint8_t DptfDisable;
+ uint8_t PcdEmmcMode;
+ uint8_t PcdUsb3ClkSsc;
+ uint8_t PcdDispClkSsc;
+ uint8_t PcdSataClkSsc;
+ uint8_t Usb2Port0PerPortPeTxiSet;
+ uint8_t Usb2Port0PerPortTxiSet;
+ uint8_t Usb2Port0IUsbTxEmphasisEn;
+ uint8_t Usb2Port0PerPortTxPeHalf;
+ uint8_t Usb2Port1PerPortPeTxiSet;
+ uint8_t Usb2Port1PerPortTxiSet;
+ uint8_t Usb2Port1IUsbTxEmphasisEn;
+ uint8_t Usb2Port1PerPortTxPeHalf;
+ uint8_t Usb2Port2PerPortPeTxiSet;
+ uint8_t Usb2Port2PerPortTxiSet;
+ uint8_t Usb2Port2IUsbTxEmphasisEn;
+ uint8_t Usb2Port2PerPortTxPeHalf;
+ uint8_t Usb2Port3PerPortPeTxiSet;
+ uint8_t Usb2Port3PerPortTxiSet;
+ uint8_t Usb2Port3IUsbTxEmphasisEn;
+ uint8_t Usb2Port3PerPortTxPeHalf;
+ uint8_t Usb2Port4PerPortPeTxiSet;
+ uint8_t Usb2Port4PerPortTxiSet;
+ uint8_t Usb2Port4IUsbTxEmphasisEn;
+ uint8_t Usb2Port4PerPortTxPeHalf;
+ uint8_t Usb3Lane0Ow2tapgen2deemph3p5;
+ uint8_t Usb3Lane1Ow2tapgen2deemph3p5;
+ uint8_t Usb3Lane2Ow2tapgen2deemph3p5;
+ uint8_t Usb3Lane3Ow2tapgen2deemph3p5;
+ uint8_t PcdSataInterfaceSpeed;
+ uint8_t PcdPchUsbSsicPort;
+ uint8_t PcdPchUsbHsicPort;
+ uint8_t PcdPcieRootPortSpeed;
+ uint8_t PcdPchSsicEnable;
+ uint32_t PcdLogoPtr;
+ uint32_t PcdLogoSize;
+ uint8_t PcdRtcLock;
+ uint8_t PMIC_I2CBus;
+ uint8_t ISPEnable;
+ uint8_t ISPPciDevConfig;
+ uint8_t PcdSdDetectChk; /* Enable / Disable SD Card Detect Simulation */
+ uint8_t I2C0Frequency; /* 0 - 100KHz, 1 - 400KHz, 2 - 1MHz */
+ uint8_t I2C1Frequency;
+ uint8_t I2C2Frequency;
+ uint8_t I2C3Frequency;
+ uint8_t I2C4Frequency;
+ uint8_t I2C5Frequency;
+ uint8_t I2C6Frequency;
};
#endif /* _SOC_CHIP_H_ */
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index 2d47663..0221478 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -35,8 +35,8 @@
static const struct reg_script core_msr_script[] = {
/* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */
REG_MSR_RMW(MSR_PKG_CST_CONFIG_CONTROL, ~0x3f080f, 0xe0008),
- REG_MSR_RMW(MSR_POWER_MISC,
- ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
+ REG_MSR_RMW(MSR_POWER_MISC, ~(ENABLE_ULFM_AUTOCM_MASK | ENABLE_INDP_AUTOCM_MASK), 0),
+
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
REG_MSR_OR(MSR_POWER_MISC, 0x44),
@@ -53,10 +53,9 @@
setup_lapic();
/*
- * The turbo disable bit is actually scoped at building
- * block level -- not package. For non-bsp cores that are within a
- * building block enable turbo. The cores within the BSP's building
- * block will just see it already enabled and move on.
+ * The turbo disable bit is actually scoped at building block level -- not package.
+ * For non-BSP cores that are within a building block, enable turbo. The cores within
+ * the BSP's building block will just see it already enabled and move on.
*/
if (lapicid())
enable_turbo();
@@ -76,9 +75,9 @@
};
static const struct cpu_device_id cpu_table[] = {
- { X86_VENDOR_INTEL, 0x406C4 },
- { X86_VENDOR_INTEL, 0x406C3 },
- { X86_VENDOR_INTEL, 0x406C2 },
+ { X86_VENDOR_INTEL, 0x406c4 },
+ { X86_VENDOR_INTEL, 0x406c3 },
+ { X86_VENDOR_INTEL, 0x406c2 },
{ 0, 0 },
};
@@ -115,9 +114,8 @@
x86_mtrr_check();
/*
- * Configure the BUNIT to allow dirty cache line evictions in non-SMM
- * mode for the lines that were dirtied while in SMM mode. Otherwise
- * the writes would be silently dropped.
+ * Configure the BUNIT to allow dirty cache line evictions in non-SMM mode for lines
+ * that were dirtied while in SMM mode. Otherwise the writes would be silently dropped.
*/
bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
@@ -190,8 +188,7 @@
intel_microcode_load_unlocked(pattrs->microcode_patch);
}
-static void relocation_handler(int cpu, uintptr_t curr_smbase,
- uintptr_t staggered_smbase)
+static void relocation_handler(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase)
{
struct smm_relocation_params *relo_params = &smm_reloc_params;
em64t100_smm_state_save_area_t *smm_state;
@@ -205,22 +202,21 @@
}
static const struct mp_ops mp_ops = {
- .pre_mp_init = pre_mp_init,
- .get_cpu_count = get_cpu_count,
- .get_smm_info = get_smm_info,
- .get_microcode_info = get_microcode_info,
- .pre_mp_smm_init = smm_southbridge_clear_state,
+ .pre_mp_init = pre_mp_init,
+ .get_cpu_count = get_cpu_count,
+ .get_smm_info = get_smm_info,
+ .get_microcode_info = get_microcode_info,
+ .pre_mp_smm_init = smm_southbridge_clear_state,
.per_cpu_smm_trigger = per_cpu_smm_trigger,
- .relocation_handler = relocation_handler,
- .post_mp_init = smm_southbridge_enable_smi,
+ .relocation_handler = relocation_handler,
+ .post_mp_init = smm_southbridge_enable_smi,
};
void soc_init_cpus(struct device *dev)
{
struct bus *cpu_bus = dev->link_list;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
if (mp_init_with_smm(cpu_bus, &mp_ops))
printk(BIOS_ERR, "MP initialization failure.\n");
diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c
index b24dff5..1eef5fd 100644
--- a/src/soc/intel/braswell/elog.c
+++ b/src/soc/intel/braswell/elog.c
@@ -51,9 +51,9 @@
static void log_wake_events(const struct chipset_power_state *ps)
{
- const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS |
- PCIE_WAKE2_STS | PCIE_WAKE1_STS |
- PCIE_WAKE0_STS;
+ const uint32_t pcie_wake_mask = PCIE_WAKE3_STS | PCIE_WAKE2_STS |
+ PCIE_WAKE1_STS | PCIE_WAKE0_STS | PCI_EXP_STS;
+
uint32_t gpe0_sts;
uint32_t gpio_mask;
int i;
diff --git a/src/soc/intel/braswell/emmc.c b/src/soc/intel/braswell/emmc.c
index 23ada25..58a3fef 100644
--- a/src/soc/intel/braswell/emmc.c
+++ b/src/soc/intel/braswell/emmc.c
@@ -33,8 +33,7 @@
{
struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
printk(BIOS_DEBUG, "eMMC init\n");
reg_script_run_on_dev(dev, emmc_ops);
diff --git a/src/soc/intel/braswell/gfx.c b/src/soc/intel/braswell/gfx.c
index 41b2c6f..ff73955 100644
--- a/src/soc/intel/braswell/gfx.c
+++ b/src/soc/intel/braswell/gfx.c
@@ -32,38 +32,34 @@
static const struct reg_script gfx_post_vbios_script[] = {
/* Set Lock bits */
- REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
+ REG_PCI_RMW32(GGC, 0xffffffff, GGC_GGCLCK),
REG_PCI_RMW32(GSM_BASE, 0xffffffff, GSM_BDSM_LOCK),
REG_PCI_RMW32(GTT_BASE, 0xffffffff, GTT_BGSM_LOCK),
REG_SCRIPT_END
};
-static inline void gfx_run_script(struct device *dev,
- const struct reg_script *ops)
+static inline void gfx_run_script(struct device *dev, const struct reg_script *ops)
{
reg_script_run_on_dev(dev, ops);
}
static void gfx_pre_vbios_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Pre VBIOS Init\n");
gfx_run_script(dev, gpu_pre_vbios_script);
}
static void gfx_post_vbios_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
printk(BIOS_INFO, "GFX: Post VBIOS Init\n");
gfx_run_script(dev, gfx_post_vbios_script);
}
static void gfx_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
if (!CONFIG(RUN_FSP_GOP)) {
/* Pre VBIOS Init */
diff --git a/src/soc/intel/braswell/gpio.c b/src/soc/intel/braswell/gpio.c
index 2ca023f..a6273f3 100644
--- a/src/soc/intel/braswell/gpio.c
+++ b/src/soc/intel/braswell/gpio.c
@@ -57,39 +57,39 @@
/* GPIO Community descriptions */
static const struct gpio_bank gpnorth_community = {
- .gpio_count = GP_NORTH_COUNT,
+ .gpio_count = GP_NORTH_COUNT,
.gpio_to_pad = gpncommunity_gpio_to_pad,
- .pad_base = COMMUNITY_GPNORTH_BASE,
- .has_gpe_en = GPE_CAPABLE,
+ .pad_base = COMMUNITY_GPNORTH_BASE,
+ .has_gpe_en = GPE_CAPABLE,
.has_wake_en = 1,
};
static const struct gpio_bank gpsoutheast_community = {
- .gpio_count = GP_SOUTHEAST_COUNT,
+ .gpio_count = GP_SOUTHEAST_COUNT,
.gpio_to_pad = gpsecommunity_gpio_to_pad,
- .pad_base = COMMUNITY_GPSOUTHEAST_BASE,
- .has_gpe_en = GPE_CAPABLE_NONE,
+ .pad_base = COMMUNITY_GPSOUTHEAST_BASE,
+ .has_gpe_en = GPE_CAPABLE_NONE,
.has_wake_en = 1,
};
static const struct gpio_bank gpsouthwest_community = {
- .gpio_count = GP_SOUTHWEST_COUNT,
+ .gpio_count = GP_SOUTHWEST_COUNT,
.gpio_to_pad = gpswcommunity_gpio_to_pad,
- .pad_base = COMMUNITY_GPSOUTHWEST_BASE,
- .has_gpe_en = GPE_CAPABLE,
+ .pad_base = COMMUNITY_GPSOUTHWEST_BASE,
+ .has_gpe_en = GPE_CAPABLE,
.has_wake_en = 1,
};
static const struct gpio_bank gpeast_community = {
- .gpio_count = GP_EAST_COUNT,
+ .gpio_count = GP_EAST_COUNT,
.gpio_to_pad = gpecommunity_gpio_to_pad,
- .pad_base = COMMUNITY_GPEAST_BASE,
- .has_gpe_en = GPE_CAPABLE_NONE,
+ .pad_base = COMMUNITY_GPEAST_BASE,
+ .has_gpe_en = GPE_CAPABLE_NONE,
.has_wake_en = 1,
};
static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
- const struct soc_gpio_map *n_gpios)
+ const struct soc_gpio_map *n_gpios)
{
const struct soc_gpio_map *n_config;
const struct soc_gpio_map *sw_config;
@@ -104,82 +104,72 @@
for (sw_config = sw_gpios, n_config = n_gpios;
(!north_done || !south_done); sw_config++, n_config++, gpio++) {
- /* when north config is done */
- if ((gpio > GP_NORTH_COUNT) ||
- (n_config->pad_conf0 == GPIO_LIST_END))
+ /* When north config is done */
+ if ((gpio > GP_NORTH_COUNT) || (n_config->pad_conf0 == GPIO_LIST_END))
north_done = 1;
- /* when sw is done */
- if ((gpio > GP_SOUTHWEST_COUNT) ||
- (sw_config->pad_conf0 == GPIO_LIST_END))
+ /* When southwest config is done */
+ if ((gpio > GP_SOUTHWEST_COUNT) || (sw_config->pad_conf0 == GPIO_LIST_END))
south_done = 1;
- /* route north gpios */
+ /* Route north gpios */
if (!north_done) {
/* Int select from 8 to 15 */
int_selection = ((n_config->pad_conf0 >> 28) & 0xf);
+
if (n_config->gpe == SMI) {
- /*
- * Set the corresponding bits (01) as
- * per the interrupt line
- */
+ /* Set the corresponding bits (01) as per the interrupt line */
route_reg |= (1 << ((int_selection - 8) * 2));
- /* reset the higher bit */
- route_reg &=
- ~(1 << ((int_selection - 8) * 2 + 1));
- alt_gpio_smi |= (1 << (int_selection + 8));
+
+ /* Reset the higher bit */
+ route_reg &= ~(1 << ((int_selection - 8) * 2 + 1));
+ alt_gpio_smi |= (1 << (int_selection + 8));
+
} else if (n_config->gpe == SCI) {
- /*
- * Set the corresponding bits as per the
- * interrupt line
- */
- route_reg |=
- (1 << (((int_selection - 8) * 2) + 1));
- /* reset the bit */
+ /* Set the corresponding bits as per the interrupt line */
+ route_reg |= (1 << (((int_selection - 8) * 2) + 1));
+
+ /* Reset the bit */
route_reg &= ~(1 << ((int_selection - 8) * 2));
- gpe0a_en |= (1 << (int_selection + 8));
+ gpe0a_en |= (1 << (int_selection + 8));
}
}
- /* route southwest gpios */
+ /* Route southwest gpios */
if (!south_done) {
/* Int select from 8 to 15 */
int_selection = ((sw_config->pad_conf0 >> 28) & 0xf);
+
if (sw_config->gpe == SMI) {
- /*
- * Set the corresponding bits (10) as
- * per the interrupt line
- */
- route_reg |= (1 << (int_selection * 2));
- route_reg &= ~(1 << (int_selection * 2 + 1));
- alt_gpio_smi |= (1 << (int_selection + 16));
+ /* Set the corresponding bits (10) as per the interrupt line */
+ route_reg |= (1 << (int_selection * 2));
+ route_reg &= ~(1 << (int_selection * 2 + 1));
+ alt_gpio_smi |= (1 << (int_selection + 16));
+
} else if (sw_config->gpe == SCI) {
- /*
- * Set the corresponding bits as
- * per the interrupt line
- */
+ /* Set the corresponding bits as per the interrupt line */
route_reg |= (1 << ((int_selection * 2) + 1));
- /* reset the bit */
+
+ /* Reset the bit */
route_reg &= ~(1 << (int_selection * 2));
- gpe0a_en |= (1 << (int_selection + 16));
+ gpe0a_en |= (1 << (int_selection + 16));
}
}
}
- /* enable gpe bits in GPE0A_EN_REG */
+ /* Enable gpe bits in GPE0A_EN_REG */
outl(gpe0a_en, ACPI_BASE_ADDRESS + GPE0A_EN_REG);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "gpio_rout = %x alt_gpio_smi = %x gpe0a_en = %x\n",
route_reg, alt_gpio_smi, gpe0a_en);
#endif
- /* Save as an smm param */
+ /* Save as an SMM param */
smm_southcluster_save_param(SMM_SAVE_PARAM_GPIO_ROUTE, route_reg);
}
-static void setup_gpios(const struct soc_gpio_map *gpios,
- const struct gpio_bank *community)
+static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank *community)
{
const struct soc_gpio_map *config;
int gpio = 0;
@@ -191,38 +181,31 @@
if (!gpios)
return;
- for (config = gpios; config->pad_conf0 != GPIO_LIST_END;
- config++, gpio++) {
+
+ for (config = gpios; config->pad_conf0 != GPIO_LIST_END; config++, gpio++) {
if (gpio > community->gpio_count)
break;
/* Pad configuration registers */
family = community->gpio_to_pad[gpio] / MAX_FAMILY_PAD_GPIO_NO;
- internal_pad_num = community->gpio_to_pad[gpio] %
- MAX_FAMILY_PAD_GPIO_NO;
+ internal_pad_num = community->gpio_to_pad[gpio] % MAX_FAMILY_PAD_GPIO_NO;
/*
- * Calculate the MMIO Address for specific GPIO pin
- * control register pointed by index.
- * REG = (IOBASE + COMMUNITY_BASE + (0X04400)) +
- * (0X400*FAMILY_NUM) + (8 * PAD_NUM)
+ * Calculate the MMIO Address for GPIO pin control register pointed by index.
+ * REG = IOBASE + COMMUNITY_BASE + 0x4400 + (0x400 * FAMILY_NUM) + (8 * PAD_NUM)
*/
- mmio_addr = FAMILY_PAD_REGS_OFF
- + (FAMILY_PAD_REGS_SIZE * family)
- + (GPIO_REGS_SIZE * internal_pad_num);
+ mmio_addr = FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * family) +
+ (GPIO_REGS_SIZE * internal_pad_num);
reg = community->pad_base + mmio_addr;
- /* get int selection value */
+ /* Get int selection value */
int_selection = ((config->pad_conf0 >> 28) & 0xf);
- /* get int mask register value */
+ /* Get int mask register value */
gpio_int_mask |= (config->int_mask << int_selection);
- /*
- * wake capable programming
- * some communities have 2 wake regs
- */
+ /* Wake capable programming, some communities have 2 wake regs */
if (gpio > 31)
gpio_wake1 |= config->wake_mask << (gpio % 32);
else
@@ -235,50 +218,38 @@
reg, config->pad_conf0, config->pad_conf1,
community->gpio_to_pad[gpio], gpio);
#endif
- /*
- * write pad configurations to conf0 and conf1 register
- */
- write32((void *)(reg + PAD_CONF0_REG),
- config->pad_conf0);
- write32((void *)(reg + PAD_CONF1_REG),
- config->pad_conf1);
+ /* Write pad configurations to conf0 and conf1 register */
+ write32((void *)(reg + PAD_CONF0_REG), config->pad_conf0);
+ write32((void *)(reg + PAD_CONF1_REG), config->pad_conf1);
}
}
#ifdef GPIO_DEBUG
- printk(BIOS_DEBUG,
- "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
+ printk(BIOS_DEBUG, "gpio_wake_mask0 = %x gpio_wake_mask1 = %x gpio_int_mask = %x\n",
gpio_wake0, gpio_wake1, gpio_int_mask);
#endif
/* Wake */
- write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0),
- gpio_wake0);
+ write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG0), gpio_wake0);
- /* wake mask config for communities with 2 regs */
+ /* Wake mask config for communities with 2 regs */
if (community->gpio_count > 32)
- write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1),
- gpio_wake1);
+ write32((void *)(community->pad_base + GPIO_WAKE_MASK_REG1), gpio_wake1);
/* Interrupt */
- write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK),
- gpio_int_mask);
-
+ write32((void *)(community->pad_base + GPIO_INTERRUPT_MASK), gpio_int_mask);
}
void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
{
-
if (config) {
/*
- * Write the default value 0xffffff to the SW
- * write_access_policy_interrupt_reg to allow the SW interrupt
- * mask register to be set
+ * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg
+ * to allow the SW interrupt mask register to be set
*/
- write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108),
- 0xffffffff);
+ write32((void *)(COMMUNITY_GPSOUTHWEST_BASE + 0x108), 0xffffffff);
printk(BIOS_DEBUG, "north\n");
setup_gpios(config->north, &gpnorth_community);
@@ -297,8 +268,8 @@
}
/*
- * Set on die termination feature with pull up value and
- * drive the pad high for TAP_TDO and TAP_TMS
+ * Set on die termination feature with pull up value
+ * and drive the pad high for TAP_TDO and TAP_TMS
*/
if (!enable_xdp_tap)
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c
index 7dccc7b..d2abccc 100644
--- a/src/soc/intel/braswell/gpio_support.c
+++ b/src/soc/intel/braswell/gpio_support.c
@@ -24,10 +24,9 @@
uint16_t gpio_family_number(uint8_t community, uint8_t pad)
{
/*
- * Refer to BSW BIOS Writers Guide, Table "Family Number".
- * BSW has 4 GPIO communities. Each community has up to 7 families and
- * each family contains a range of Pad numbers. The number in the array
- * is the maximum no. of that range.
+ * Refer to BSW BIOS Writers Guide, Table "Family Number". BSW has 4 GPIO communities.
+ * Each community has up to 7 families and each family contains a range of Pad numbers.
+ * The number in the array is the maximum no. of that range.
* For example: East community, family 0, Pad 0~11.
*/
static const uint8_t community_base[GPIO_COMMUNITY_COUNT]
@@ -57,8 +56,7 @@
}
/*
- * Return pad configuration register offset by pad number and which community
- * it is in.
+ * Return pad configuration register offset by pad number and which community it is in.
*/
uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad)
{
@@ -69,12 +67,11 @@
fpad = gpio_family_number(community, pad);
/*
- * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space
- * Registers Addresses" for the Pad configuration register calculation.
+ * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space Registers Addresses"
+ * for the Pad configuration register calculation.
*/
- pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community)
- + FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * (fpad >> 8))
- + (GPIO_REGS_SIZE * (fpad & 0xff)));
+ pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + FAMILY_PAD_REGS_OFF +
+ (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) + (GPIO_REGS_SIZE * (fpad & 0xff)));
return pad_config_reg;
}
@@ -86,17 +83,18 @@
if (gpio_num >= GP_SW_00 && gpio_num <= GP_SW_97) {
comm = GP_SOUTHWEST;
*pad = gpio_num % GP_SOUTHWEST_COUNT;
+
} else if (gpio_num >= GP_NC_00 && gpio_num <= GP_NC_72) {
comm = GP_NORTH;
*pad = gpio_num % GP_SOUTHWEST_COUNT;
+
} else if (gpio_num >= GP_E_00 && gpio_num <= GP_E_26) {
comm = GP_EAST;
- *pad = gpio_num %
- (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT);
+ *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT);
+
} else {
comm = GP_SOUTHEAST;
- *pad = gpio_num % (GP_SOUTHWEST_COUNT +
- GP_NORTH_COUNT + GP_EAST_COUNT);
+ *pad = gpio_num % (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT);
}
return comm;
}
@@ -107,10 +105,8 @@
int pad_num = 0;
uint32_t *pad_config0_reg;
uint32_t *pad_config1_reg;
- int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
- + GP_SOUTHEAST_COUNT;
- if (gpio_num > max_gpio_cnt)
+ if (gpio_num > MAX_GPIO_CNT)
return;
/* Get GPIO Community based on GPIO_NUMBER */
comm = gpio_get_community_num(gpio_num, &pad_num);
@@ -147,10 +143,8 @@
int pad_num = 0;
uint32_t *pad_config0_reg;
u32 pad_value;
- int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT
- + GP_SOUTHEAST_COUNT;
- if (gpio_num > max_gpio_cnt)
+ if (gpio_num > MAX_GPIO_CNT)
return -1;
/* Get GPIO Community based on GPIO_NUMBER */
diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h
index 51c8e12..e40a951 100644
--- a/src/soc/intel/braswell/include/soc/gpio.h
+++ b/src/soc/intel/braswell/include/soc/gpio.h
@@ -133,6 +133,8 @@
#define GP_EAST_COUNT 24
#define GP_SOUTHEAST_COUNT 55
+#define MAX_GPIO_CNT (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + GP_SOUTHEAST_COUNT)
+
/* General */
#define GPIO_REGS_SIZE 8
#define NA 0
diff --git a/src/soc/intel/braswell/lpc_init.c b/src/soc/intel/braswell/lpc_init.c
index bf58074..8b7c1ea 100644
--- a/src/soc/intel/braswell/lpc_init.c
+++ b/src/soc/intel/braswell/lpc_init.c
@@ -50,48 +50,47 @@
static void lpc_gpio_config(u32 cycle)
{
if (cycle == SUSPEND_CYCLE) { /* Suspend cycle */
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_FRAME_MMIO_OFFSET),
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD0_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD1_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD2_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD3_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_CLKRUN_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET),
PAD_CFG0_NATIVE_PD20K(1));
+
} else { /* Resume cycle */
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_FRAME_MMIO_OFFSET),
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_FRAME_MMIO_OFFSET),
PAD_CFG0_NATIVE_M1);
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD0_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD0_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD1_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD1_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD2_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD2_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_AD3_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_AD3_MMIO_OFFSET),
PAD_CFG0_NATIVE_PU20K(1));
- write32((void *)(COMMUNITY_GPSOUTHEAST_BASE +
- LPC_CLKRUN_MMIO_OFFSET),
+
+ write32((void *)(COMMUNITY_GPSOUTHEAST_BASE + LPC_CLKRUN_MMIO_OFFSET),
PAD_CFG0_NATIVE_M1);
}
}
/*
- * configure LPC GPIO lines for low power
+ * Configure LPC GPIO lines for low power
*/
void lpc_set_low_power(void)
{
diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c
index 12d2858..85e698c 100644
--- a/src/soc/intel/braswell/lpe.c
+++ b/src/soc/intel/braswell/lpe.c
@@ -31,7 +31,6 @@
#include <soc/ramstage.h>
#include "chip.h"
-
/*
* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB
* address. Just take 1MiB @ 512MiB.
@@ -58,12 +57,12 @@
static const struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
REG_PCI_OR32(PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
- | PCI_COMMAND_INT_DISABLE),
+ PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INT_DISABLE),
+
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_0x58, LPE_PCICFGCTR1,
- LPE_PCICFGCTR1_PCI_CFG_DIS |
- LPE_PCICFGCTR1_ACPI_INT_EN),
+ LPE_PCICFGCTR1_PCI_CFG_DIS | LPE_PCICFGCTR1_ACPI_INT_EN),
+
REG_SCRIPT_END
};
global_nvs_t *gnvs;
@@ -101,11 +100,13 @@
freq_str = "19.2MHz External Crystal";
reg = CLK_SRC_XTAL;
break;
+
case LPE_CLK_SRC_PLL:
/* PLL driven bit2=1 */
freq_str = "19.2MHz PLL";
reg = CLK_SRC_PLL;
break;
+
default:
reg = CLK_SRC_XTAL;
printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n");
@@ -118,7 +119,7 @@
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
- clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
+ clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
@@ -136,15 +137,13 @@
printk(BIOS_DEBUG, "LPE FW Resource: 0x%08x\n", (u32) res->base);
/* Continue using old way of informing firmware address / size. */
- pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
+ pci_write_config32(dev, FIRMWARE_PCI_REG_BASE, res->base);
pci_write_config32(dev, FIRMWARE_PCI_REG_LENGTH, res->size);
/* Also put the address in MMIO space like on C0 BTM */
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
- write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
- res->base);
- write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
- res->size);
+ write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0), res->base);
+ write32((void *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0), res->size);
}
@@ -152,8 +151,7 @@
{
struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
lpe_stash_firmware_info(dev);
setup_codec_clock(dev);
@@ -168,7 +166,7 @@
pci_dev_read_resources(dev);
/*
- * Allocate the BAR1 resource at index 2 to fulfil the Windows driver
+ * Allocate the BAR1 resource at index 2 to fulfill the Windows driver
* interface requirements even though the PCI device has only one BAR
*/
res = new_resource(dev, PCI_BASE_ADDRESS_2);
@@ -179,8 +177,7 @@
res->align = 12;
res->flags = IORESOURCE_MEM;
- reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE,
- FIRMWARE_PHYS_BASE >> 10,
+ reserved_ram_resource(dev, FIRMWARE_PCI_REG_BASE, FIRMWARE_PHYS_BASE >> 10,
FIRMWARE_PHYS_LENGTH >> 10);
}
diff --git a/src/soc/intel/braswell/lpss.c b/src/soc/intel/braswell/lpss.c
index 6bc4065..b5c4e3d 100644
--- a/src/soc/intel/braswell/lpss.c
+++ b/src/soc/intel/braswell/lpss.c
@@ -27,16 +27,15 @@
#include "chip.h"
-static void dev_enable_acpi_mode(struct device *dev,
- int iosf_reg, int nvs_index)
+static void dev_enable_acpi_mode(struct device *dev, int iosf_reg, int nvs_index)
{
struct reg_script ops[] = {
/* Disable PCI interrupt, enable Memory and Bus Master */
- REG_PCI_OR32(PCI_COMMAND,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)),
+ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1 << 10)),
/* Enable ACPI mode */
REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg,
LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN),
+
REG_SCRIPT_END
};
struct resource *bar;
@@ -65,10 +64,6 @@
reg_script_run_on_dev(dev, ops);
}
-static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
-{
- *iosf_reg = -1;
- *nvs_index = -1;
#define SET_IOSF_REG(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
do { \
@@ -76,6 +71,11 @@
*nvs_index = LPSS_NVS_ ## name_; \
} while (0)
+static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index)
+{
+ *iosf_reg = -1;
+ *nvs_index = -1;
+
switch (dev->path.pci.devfn) {
SET_IOSF_REG(SIO_DMA1);
break;
@@ -108,6 +108,8 @@
}
}
+#define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
+
static void i2c_disable_resets(struct device *dev)
{
/* Release the I2C devices from reset. */
@@ -116,9 +118,6 @@
REG_SCRIPT_END,
};
-#define CASE_I2C(name_) \
- case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
-
switch (dev->path.pci.devfn) {
CASE_I2C(I2C1) :
CASE_I2C(I2C2) :
@@ -140,19 +139,15 @@
struct soc_intel_braswell_config *config = config_of(dev);
int iosf_reg, nvs_index;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
- printk(BIOS_SPEW, "%s - %s\n",
- get_pci_class_name(dev),
- get_pci_subclass_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s - %s\n", get_pci_class_name(dev), get_pci_subclass_name(dev));
dev_ctl_reg(dev, &iosf_reg, &nvs_index);
if (iosf_reg < 0) {
int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn);
- printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n",
- slot, func);
+ printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", slot, func);
return;
}
diff --git a/src/soc/intel/braswell/memmap.c b/src/soc/intel/braswell/memmap.c
index 04e5d7b..28b9e0e 100644
--- a/src/soc/intel/braswell/memmap.c
+++ b/src/soc/intel/braswell/memmap.c
@@ -19,7 +19,7 @@
static size_t smm_region_size(void)
{
u32 smm_size;
- smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF;
+ smm_size = iosf_bunit_read(BUNIT_SMRRH) & 0xFFFF;
smm_size -= iosf_bunit_read(BUNIT_SMRRL) & 0xFFFF;
smm_size = (smm_size + 1) << 20;
return smm_size;
diff --git a/src/soc/intel/braswell/pcie.c b/src/soc/intel/braswell/pcie.c
index 7ab184f..4745be9 100644
--- a/src/soc/intel/braswell/pcie.c
+++ b/src/soc/intel/braswell/pcie.c
@@ -40,8 +40,7 @@
static void pcie_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
}
static const struct reg_script no_dev_behind_port[] = {
@@ -86,14 +85,12 @@
static struct device *port1_dev;
/*
- * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW.
- * For each port initial assumption is that, each port will have
- * devices connected to it. Later we will scan each PORT and if
- * the device is not attached to that port we will update
- * rootports_in_use. If none of the root port is in use we will
- * disable PORT1 otherwise we will keep PORT1 enabled per spec.
- * In future if the Soc has more number of PCIe Root ports then
- * change MAX_ROOT_PORTS_BSW value accordingly.
+ * The SOC has 4 ROOT ports defined with MAX_ROOT_PORTS_BSW. For each port initial
+ * assumption is that, each port will have devices connected to it. Later we will
+ * scan each PORT and if the device is not attached to that port we will update
+ * rootports_in_use. If none of the root port is in use we will disable PORT1
+ * otherwise we will keep PORT1 enabled per spec. In future if the SoC has more
+ * number of PCIe Root ports then change MAX_ROOT_PORTS_BSW value accordingly.
*/
static uint32_t rootports_in_use = MAX_ROOT_PORTS_BSW;
@@ -109,9 +106,9 @@
printk(BIOS_DEBUG, "No PCIe device present.");
/*
- * Defer PORT1 disabling for now. When we are at Last port
- * we will check rootports_in_use and disable PORT1 if none
- * of the port has any device connected
+ * Defer PORT1 disabling for now. When we are at Last port we will check
+ * rootports_in_use and disable PORT1 if none of the ports have any device
+ * connected to it.
*/
if (!is_first_port(dev)) {
reg_script_run_on_dev(dev, no_dev_behind_port);
@@ -119,8 +116,8 @@
} else
port1_dev = dev;
/*
- * If none of the ROOT PORT has devices connected then
- * disable PORT1 else keep the PORT1 enable
+ * If none of the ROOT PORT has devices connected then disable PORT1.
+ * Else, keep the PORT1 enabled.
*/
if (!rootports_in_use) {
reg_script_run_on_dev(port1_dev, no_dev_behind_port);
@@ -136,8 +133,8 @@
static void pcie_enable(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+
if (is_first_port(dev)) {
struct soc_intel_braswell_config *config = config_of(dev);
uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL);
@@ -146,8 +143,7 @@
strpfusecfg = pci_read_config32(dev, STRPFUSECFG);
if (config->pcie_wake_enable)
- smm_southcluster_save_param(
- SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
+ smm_southcluster_save_param(SMM_SAVE_PARAM_PCIE_WAKE_ENABLE, 1);
}
/* Check if device is enabled in strapping. */
diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c
index f218259..9c5079f 100644
--- a/src/soc/intel/braswell/pmutil.c
+++ b/src/soc/intel/braswell/pmutil.c
@@ -53,8 +53,7 @@
return pci_read_config16(get_pcu_dev(), ABASE) & 0xfff8;
}
-static void print_num_status_bits(int num_bits, uint32_t status,
- const char *const bit_names[])
+static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[])
{
int i;
@@ -310,16 +309,16 @@
{
uint32_t alt_gpio_sts;
static const char *const alt_gpio_smi_sts_bits[] = {
- [0] = "SUS_GPIO_0",
- [1] = "SUS_GPIO_1",
- [2] = "SUS_GPIO_2",
- [3] = "SUS_GPIO_3",
- [4] = "SUS_GPIO_4",
- [5] = "SUS_GPIO_5",
- [6] = "SUS_GPIO_6",
- [7] = "SUS_GPIO_7",
- [8] = "CORE_GPIO_0",
- [9] = "CORE_GPIO_1",
+ [0] = "SUS_GPIO_0",
+ [1] = "SUS_GPIO_1",
+ [2] = "SUS_GPIO_2",
+ [3] = "SUS_GPIO_3",
+ [4] = "SUS_GPIO_4",
+ [5] = "SUS_GPIO_5",
+ [6] = "SUS_GPIO_6",
+ [7] = "SUS_GPIO_7",
+ [8] = "CORE_GPIO_0",
+ [9] = "CORE_GPIO_1",
[10] = "CORE_GPIO_2",
[11] = "CORE_GPIO_3",
[12] = "CORE_GPIO_4",
diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c
index 9b0775e..3e1625ff6 100644
--- a/src/soc/intel/braswell/ramstage.c
+++ b/src/soc/intel/braswell/ramstage.c
@@ -87,12 +87,15 @@
if (attrs->revid >= RID_D_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_D_STEPPING_START) / 2;
attrs->stepping += STEP_D1;
+
} else if (attrs->revid >= RID_C_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_C_STEPPING_START) / 2;
attrs->stepping += STEP_C0;
+
} else if (attrs->revid >= RID_B_STEPPING_START) {
attrs->stepping = (attrs->revid - RID_B_STEPPING_START) / 2;
attrs->stepping += STEP_B0;
+
} else {
attrs->stepping = (attrs->revid - RID_A_STEPPING_START) / 2;
attrs->stepping += STEP_A0;
@@ -114,15 +117,15 @@
/* Set IA core speed ratio and voltages */
fill_in_msr(&msr, MSR_IACORE_RATIOS);
- attrs->iacore_ratios[IACORE_MIN] = msr.lo & 0x7f;
- attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
+ attrs->iacore_ratios[IACORE_MIN] = (msr.lo >> 0) & 0x7f;
+ attrs->iacore_ratios[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
attrs->iacore_ratios[IACORE_MAX] = (msr.lo >> 16) & 0x7f;
fill_in_msr(&msr, MSR_IACORE_TURBO_RATIOS);
attrs->iacore_ratios[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
fill_in_msr(&msr, MSR_IACORE_VIDS);
- attrs->iacore_vids[IACORE_MIN] = msr.lo & 0x7f;
- attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
+ attrs->iacore_vids[IACORE_MIN] = (msr.lo >> 0) & 0x7f;
+ attrs->iacore_vids[IACORE_LFM] = (msr.lo >> 8) & 0x7f;
attrs->iacore_vids[IACORE_MAX] = (msr.lo >> 16) & 0x7f;
fill_in_msr(&msr, MSR_IACORE_TURBO_VIDS);
attrs->iacore_vids[IACORE_TURBO] = (msr.lo & 0xff); /* 1 core max */
diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c
index 1a3100c..d8afecd 100644
--- a/src/soc/intel/braswell/romstage/romstage.c
+++ b/src/soc/intel/braswell/romstage/romstage.c
@@ -42,13 +42,14 @@
struct chipset_power_state *fill_power_state(void)
{
- power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
- power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
- power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
+ power_state.pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
+ power_state.pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN);
+ power_state.pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
power_state.gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
- power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
- power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
- power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
+ power_state.gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
+ power_state.tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
+
+ power_state.prsts = read32((void *)(PMC_BASE_ADDRESS + PRSTS));
power_state.gen_pmcon1 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON1));
power_state.gen_pmcon2 = read32((void *)(PMC_BASE_ADDRESS + GEN_PMCON2));
@@ -56,10 +57,13 @@
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
power_state.pm1_sts, power_state.pm1_en, power_state.pm1_cnt);
+
printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n",
power_state.gpe0_sts, power_state.gpe0_en, power_state.tco_sts);
+
printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n",
power_state.prsts, power_state.gen_pmcon1, power_state.gen_pmcon2);
+
printk(BIOS_DEBUG, "prev_sleep_state %d\n", power_state.prev_sleep_state);
return &power_state;
}
@@ -105,8 +109,7 @@
}
/* Initialize the UPD parameters for MemoryInit */
-void soc_memory_init_params(struct romstage_params *params,
- MEMORY_INIT_UPD *upd)
+void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd)
{
const struct device *dev;
const struct soc_intel_braswell_config *config;
@@ -116,24 +119,24 @@
if (!dev) {
printk(BIOS_ERR,
- "Error! Device (PCI:0:%02x.%01x) not found, "
- "soc_memory_init_params!\n", LPC_DEV, LPC_FUNC);
+ "Error! Device (PCI:0:%02x.%01x) not found, soc_memory_init_params!\n",
+ LPC_DEV, LPC_FUNC);
return;
}
config = config_of(dev);
printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n");
- upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ?
- config->PcdMrcInitTsegSize : 0;
- upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
- upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
- upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;
+
+ upd->PcdMrcInitTsegSize = CONFIG(HAVE_SMI_HANDLER) ? config->PcdMrcInitTsegSize : 0;
+ upd->PcdMrcInitMmioSize = config->PcdMrcInitMmioSize;
+ upd->PcdMrcInitSpdAddr1 = config->PcdMrcInitSpdAddr1;
+ upd->PcdMrcInitSpdAddr2 = config->PcdMrcInitSpdAddr2;
upd->PcdIgdDvmt50PreAlloc = config->PcdIgdDvmt50PreAlloc;
- upd->PcdApertureSize = config->PcdApertureSize;
- upd->PcdGttSize = config->PcdGttSize;
- upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
- upd->PcdDvfsEnable = config->PcdDvfsEnable;
- upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
+ upd->PcdApertureSize = config->PcdApertureSize;
+ upd->PcdGttSize = config->PcdGttSize;
+ upd->PcdLegacySegDecode = config->PcdLegacySegDecode;
+ upd->PcdDvfsEnable = config->PcdDvfsEnable;
+ upd->PcdCaMirrorEn = config->PcdCaMirrorEn;
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
@@ -142,27 +145,39 @@
/* Display the parameters for MemoryInit */
printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
fsp_display_upd_value("PcdMrcInitTsegSize", 2,
- old->PcdMrcInitTsegSize, new->PcdMrcInitTsegSize);
+ old->PcdMrcInitTsegSize,
+ new->PcdMrcInitTsegSize);
fsp_display_upd_value("PcdMrcInitMmioSize", 2,
- old->PcdMrcInitMmioSize, new->PcdMrcInitMmioSize);
+ old->PcdMrcInitMmioSize,
+ new->PcdMrcInitMmioSize);
fsp_display_upd_value("PcdMrcInitSpdAddr1", 1,
- old->PcdMrcInitSpdAddr1, new->PcdMrcInitSpdAddr1);
+ old->PcdMrcInitSpdAddr1,
+ new->PcdMrcInitSpdAddr1);
fsp_display_upd_value("PcdMrcInitSpdAddr2", 1,
- old->PcdMrcInitSpdAddr2, new->PcdMrcInitSpdAddr2);
+ old->PcdMrcInitSpdAddr2,
+ new->PcdMrcInitSpdAddr2);
fsp_display_upd_value("PcdMemChannel0Config", 1,
- old->PcdMemChannel0Config, new->PcdMemChannel0Config);
+ old->PcdMemChannel0Config,
+ new->PcdMemChannel0Config);
fsp_display_upd_value("PcdMemChannel1Config", 1,
- old->PcdMemChannel1Config, new->PcdMemChannel1Config);
+ old->PcdMemChannel1Config,
+ new->PcdMemChannel1Config);
fsp_display_upd_value("PcdMemorySpdPtr", 4,
- old->PcdMemorySpdPtr, new->PcdMemorySpdPtr);
+ old->PcdMemorySpdPtr,
+ new->PcdMemorySpdPtr);
fsp_display_upd_value("PcdIgdDvmt50PreAlloc", 1,
- old->PcdIgdDvmt50PreAlloc, new->PcdIgdDvmt50PreAlloc);
+ old->PcdIgdDvmt50PreAlloc,
+ new->PcdIgdDvmt50PreAlloc);
fsp_display_upd_value("PcdApertureSize", 1,
- old->PcdApertureSize, new->PcdApertureSize);
+ old->PcdApertureSize,
+ new->PcdApertureSize);
fsp_display_upd_value("PcdGttSize", 1,
- old->PcdGttSize, new->PcdGttSize);
+ old->PcdGttSize,
+ new->PcdGttSize);
fsp_display_upd_value("PcdLegacySegDecode", 1,
- old->PcdLegacySegDecode, new->PcdLegacySegDecode);
+ old->PcdLegacySegDecode,
+ new->PcdLegacySegDecode);
fsp_display_upd_value("PcdDvfsEnable", 1,
- old->PcdDvfsEnable, new->PcdDvfsEnable);
+ old->PcdDvfsEnable,
+ new->PcdDvfsEnable);
}
diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c
index afd66a0..4e60819 100644
--- a/src/soc/intel/braswell/sata.c
+++ b/src/soc/intel/braswell/sata.c
@@ -26,8 +26,7 @@
static void sata_init(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
}
static void sata_enable(struct device *dev)
diff --git a/src/soc/intel/braswell/sd.c b/src/soc/intel/braswell/sd.c
index 1295ffa..97983f7 100644
--- a/src/soc/intel/braswell/sd.c
+++ b/src/soc/intel/braswell/sd.c
@@ -25,23 +25,21 @@
#include <soc/ramstage.h>
#include "chip.h"
-#define CAP_OVERRIDE_LOW 0xa0
-#define CAP_OVERRIDE_HIGH 0xa4
-# define USE_CAP_OVERRIDES (1 << 31)
+#define CAP_OVERRIDE_LOW 0xa0
+#define CAP_OVERRIDE_HIGH 0xa4
+#define USE_CAP_OVERRIDES (1 << 31)
static void sd_init(struct device *dev)
{
struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) {
printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n");
- pci_write_config32(dev, CAP_OVERRIDE_LOW,
- config->sdcard_cap_low);
- pci_write_config32(dev, CAP_OVERRIDE_HIGH,
- config->sdcard_cap_high | USE_CAP_OVERRIDES);
+ pci_write_config32(dev, CAP_OVERRIDE_LOW, config->sdcard_cap_low);
+ pci_write_config32(dev, CAP_OVERRIDE_HIGH, config->sdcard_cap_high |
+ USE_CAP_OVERRIDES);
}
if (config->sd_acpi_mode)
diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c
index 584ec88..a33c9af 100644
--- a/src/soc/intel/braswell/smihandler.c
+++ b/src/soc/intel/braswell/smihandler.c
@@ -87,8 +87,7 @@
/* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
hdr &= 0x7f;
- if (hdr == PCI_HEADER_TYPE_BRIDGE ||
- hdr == PCI_HEADER_TYPE_CARDBUS) {
+ if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
unsigned int buses;
buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
busmaster_disable_on_bus((buses >> 8) & 0xff);
@@ -100,38 +99,24 @@
static void tristate_gpios(uint32_t val)
{
/* Tri-state eMMC */
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- SDMMC1_CMD_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- SDMMC1_D0_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- SDMMC1_D1_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- SDMMC1_D2_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- SDMMC1_D3_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- MMC1_D4_SD_WE_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- MMC1_D5_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- MMC1_D6_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- MMC1_D7_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHEAST_BASE +
- MMC1_RCLK_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_CMD_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D0_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D1_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D2_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + SDMMC1_D3_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D4_SD_WE_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D5_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D6_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_RCLK_OFFSET, val);
/* Tri-state HDMI */
- write32((void *)COMMUNITY_GPNORTH_BASE +
- HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPNORTH_BASE +
- HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPNORTH_BASE + HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
/* Tri-state CFIO 139 and 140 */
- write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
- CFIO_139_MMIO_OFFSET, val);
- write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
- CFIO_140_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_139_MMIO_OFFSET, val);
+ write32((void *)COMMUNITY_GPSOUTHWEST_BASE + CFIO_140_MMIO_OFFSET, val);
}
@@ -156,11 +141,10 @@
if (slp_typ >= ACPI_S3)
elog_gsmi_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ);
- /* Clear pending GPE events */
+ /* Clear pending GPE events */
clear_gpe_status();
/* Next, do the deed. */
-
switch (slp_typ) {
case ACPI_S0:
printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n");
@@ -183,25 +167,24 @@
/* Disable all GPE */
disable_all_gpe();
- /* also iterates over all bridges on bus 0 */
+ /* Also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
break;
default:
printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n");
break;
}
+
/* Clear pending wake status bit to avoid immediate wake */
- write32((void *)(0xfed88000 + 0x0200),
- read32((void *)(0xfed88000 + 0x0200)));
+ write32((void *)(0xfed88000 + 0x0200), read32((void *)(0xfed88000 + 0x0200)));
/* Tri-state specific GPIOS to avoid leakage during S3/S5 */
if ((slp_typ == ACPI_S3) || (slp_typ == ACPI_S5))
tristate_gpios(PAD_CONTROL_REG0_TRISTATE);
/*
- * Write back to the SLP register to cause the originally intended
- * event again. We need to set BIT13 (SLP_EN) though to make the
- * sleep happen.
+ * Write back to the SLP register to cause the originally intended event again.
+ * We need to set BIT13 (SLP_EN) though to make the sleep happen.
*/
enable_pm1_control(SLP_EN);
@@ -222,9 +205,8 @@
}
/*
- * Look for Synchronous IO SMI and use save state from that
- * core in case we are not running on the same core that
- * initiated the IO transaction.
+ * Look for Synchronous IO SMI and use save state from that core in case
+ * we are not running on the same core that initiated the IO transaction.
*/
static em64t100_smm_state_save_area_t *smi_apmc_find_state_save(uint8_t cmd)
{
@@ -261,8 +243,7 @@
{
u32 *ret, *param;
uint8_t sub_command;
- em64t100_smm_state_save_area_t *io_smi =
- smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
+ em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_ELOG_GSMI);
if (!io_smi)
return;
@@ -281,8 +262,7 @@
static void southbridge_smi_store(void)
{
u8 sub_command, ret;
- em64t100_smm_state_save_area_t *io_smi =
- smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+ em64t100_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE);
uint32_t reg_ebx;
if (!io_smi)
@@ -333,8 +313,7 @@
break;
case APM_CNT_GNVS_UPDATE:
if (smm_initialized) {
- printk(BIOS_DEBUG,
- "SMI#: SMM structures already initialized!\n");
+ printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
return;
}
state = smi_apmc_find_state_save(reg8);
@@ -362,12 +341,9 @@
{
uint16_t pm1_sts = clear_pm1_status();
- /*
- * While OSPM is not active, poweroff immediately
- * on a power button event.
- */
+ /* While OSPM is not active, poweroff immediately on a power button event */
if (pm1_sts & PWRBTN_STS) {
- /* power button pressed */
+ /* Power button pressed */
elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
disable_pm1_control(-1UL);
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT));
@@ -463,8 +439,7 @@
southbridge_smi[i]();
} else {
printk(BIOS_DEBUG,
- "SMI_STS[%d] occurred, but no "
- "handler available.\n", i);
+ "SMI_STS[%d] occurred, but no handler available.\n", i);
}
}
diff --git a/src/soc/intel/braswell/smm.c b/src/soc/intel/braswell/smm.c
index c470f93..ef801bd 100644
--- a/src/soc/intel/braswell/smm.c
+++ b/src/soc/intel/braswell/smm.c
@@ -75,6 +75,7 @@
for (i = 0; i < 16; i++) {
if ((route_reg & ROUTE_MASK) == ROUTE_SMI)
alt_gpio_reg |= (1 << i);
+
route_reg >>= 2;
}
printk(BIOS_DEBUG, "ALT_GPIO_SMI = %08x\n", alt_gpio_reg);
@@ -89,6 +90,7 @@
printk(BIOS_DEBUG, "Enabling SMIs.\n");
if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
pm1_events |= PCIEXPWAK_DIS;
+
enable_pm1(pm1_events);
disable_gpe(PME_B0_EN);
diff --git a/src/soc/intel/braswell/southcluster.c b/src/soc/intel/braswell/southcluster.c
index 7312530..be0d910 100644
--- a/src/soc/intel/braswell/southcluster.c
+++ b/src/soc/intel/braswell/southcluster.c
@@ -42,15 +42,16 @@
static void sc_set_serial_irqs_mode(struct device *dev, enum serirq_mode mode)
{
- u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
+ u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0xf);
switch (mode) {
case SERIRQ_CONTINUOUS:
break;
+
case SERIRQ_OFF:
- write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) &
- ~SIRQEN);
+ write32(ilb_base + ILB_OIC, read32(ilb_base + ILB_OIC) & ~SIRQEN);
break;
+
case SERIRQ_QUIET:
default:
write8(ilb_base + SCNT, read8(ilb_base + SCNT) & ~SCNT_MODE);
@@ -58,19 +59,19 @@
}
}
-static inline void
-add_mmio_resource(struct device *dev, int i, unsigned long addr,
- unsigned long size)
+static inline void add_mmio_resource(struct device *dev, int i, unsigned long addr,
+ unsigned long size)
{
printk(BIOS_SPEW, "%s/%s (%s, 0x%016lx, 0x%016lx)\n",
__FILE__, __func__, dev_name(dev), addr, size);
+
mmio_resource(dev, i, addr >> 10, size >> 10);
}
static void sc_add_mmio_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+
add_mmio_resource(dev, 0xfeb, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE);
add_mmio_resource(dev, PBASE, PMC_BASE_ADDRESS, PMC_BASE_SIZE);
add_mmio_resource(dev, IOBASE, IO_BASE_ADDRESS, IO_BASE_SIZE);
@@ -79,9 +80,9 @@
add_mmio_resource(dev, MPBASE, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE);
add_mmio_resource(dev, PUBASE, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE);
add_mmio_resource(dev, RCBA, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE);
- add_mmio_resource(dev, 0xfff,
- 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB*KiB) + 1,
- (CONFIG_COREBOOT_ROMSIZE_KB*KiB)); /* BIOS ROM */
+ add_mmio_resource(dev, 0xfff, 0xffffffff - (CONFIG_COREBOOT_ROMSIZE_KB * KiB) + 1,
+ (CONFIG_COREBOOT_ROMSIZE_KB * KiB)); /* BIOS ROM */
+
add_mmio_resource(dev, 0xfec, IO_APIC_ADDR, 0x00001000); /* IOAPIC */
}
@@ -99,17 +100,16 @@
}
/*
- * Write PCI config space IRQ assignments. PCI devices have the INT_LINE
- * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing
- * information to operating systems and drivers. The INT_PIN register is
- * generally read only and reports which interrupt pin A - D it uses. The
- * INT_LINE register is configurable and reports which IRQ (generally the
- * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling
- * on devices that are downstream on a PCI bridge into account.
+ * Write PCI config space IRQ assignments. PCI devices have the INT_LINE (0x3c) and INT_PIN
+ * (0x3d) registers which report interrupt routing information to operating systems and drivers.
+ * The INT_PIN register is generally read only and reports which interrupt pin A - D it uses.
+ * The INT_LINE register is configurable and reports which IRQ (generally the PIC IRQs 1 - 15)
+ * it will use. This needs to take interrupt pin swizzling on devices that are downstream on
+ * a PCI bridge into account.
*
- * This function will loop through all enabled PCI devices and program the
- * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it
- * uses. It then configures each interrupt in the pic to be level triggered.
+ * This function will loop through all enabled PCI devices and program the INT_LINE register
+ * with the correct PIC IRQ number for the INT_PIN that it uses. It then configures each
+ * interrupt in the PIC to be level triggered.
*/
static void write_pci_config_irqs(void)
{
@@ -125,16 +125,14 @@
const struct soc_irq_route *ir = &global_soc_irq_route;
if (ir == NULL) {
- printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments"
- " because 'global_braswell_irq_route' structure does"
- " not exist\n");
+ printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments "
+ "because 'global_braswell_irq_route' structure does not exist\n");
return;
}
/*
- * Loop through all enabled devices and program their
- * INT_LINE, INT_PIN registers from values taken from
- * the Interrupt Route registers in the ILB
+ * Loop through all enabled devices and program their INT_LINE, INT_PIN registers from
+ * values taken from the Interrupt Route registers in the ILB
*/
printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n");
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
@@ -164,8 +162,8 @@
if (ir->pcidev[device_num] == 0) {
printk(BIOS_WARNING,
- "Warning: PCI Device %d does not have an IRQ "
- "entry, skipping it\n", device_num);
+ "Warning: PCI Device %d does not have an IRQ entry, "
+ "skipping it\n", device_num);
continue;
}
@@ -178,28 +176,24 @@
if (int_line != PIRQ_PIC_IRQDISABLE) {
/* Set this IRQ to level triggered */
- i8259_configure_irq_trigger(int_line,
- IRQ_LEVEL_TRIGGERED);
+ i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED);
+
/* Set the Interrupt Line register */
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
- int_line);
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
} else {
- /*
- * Set the Interrupt line register as 'unknown' or
- * 'unused'
- */
- pci_write_config8(irq_dev, PCI_INTERRUPT_LINE,
- PIRQ_PIC_UNKNOWN_UNUSED);
+ /* Set the Interrupt line register as 'unknown' or 'unused' */
+ pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, PIRQ_PIC_UNKNOWN_UNUSED);
}
- printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n",
- original_int_pin, pin_to_str(original_int_pin));
+ printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", original_int_pin,
+ pin_to_str(original_int_pin));
+
if (parent_bdf != current_bdf)
- printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n",
- new_int_pin, pin_to_str(new_int_pin));
- printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n"
- "\tINT_LINE\t: 0x%X (IRQ %d)\n",
- 'A' + pirq, int_line, int_line);
+ printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", new_int_pin,
+ pin_to_str(new_int_pin));
+
+ printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n\tINT_LINE\t: 0x%X (IRQ %d)\n",
+ 'A' + pirq, int_line, int_line);
}
printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PIRQ assignments\n");
}
@@ -211,11 +205,10 @@
return 0;
/* Is it entirely contained? */
- if (base >= LPC_DEFAULT_IO_RANGE_LOWER &&
- (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
+ if (base >= LPC_DEFAULT_IO_RANGE_LOWER && (base + size) < LPC_DEFAULT_IO_RANGE_UPPER)
return 1;
- /* This will return not in range for partial overlaps. */
+ /* This will return not in range for partial overlaps */
return 0;
}
@@ -223,8 +216,7 @@
* Note: this function assumes there is no overlap with the default LPC device's
* claimed range: LPC_DEFAULT_IO_RANGE_LOWER -> LPC_DEFAULT_IO_RANGE_UPPER.
*/
-static void sc_add_io_resource(struct device *dev, int base, int size,
- int index)
+static void sc_add_io_resource(struct device *dev, int base, int size, int index)
{
struct resource *res;
@@ -244,8 +236,7 @@
{
struct resource *res;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
/* Add the default claimed IO range for the LPC device. */
res = new_resource(dev, 0);
@@ -262,8 +253,7 @@
static void sc_read_resources(struct device *dev)
{
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
@@ -278,20 +268,19 @@
static void sc_init(struct device *dev)
{
int i;
- const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
- const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
const unsigned long ilb_base = ILB_BASE_ADDRESS;
+ const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
+ const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
+
void *gen_pmcon1 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON1);
const struct soc_irq_route *ir = &global_soc_irq_route;
struct soc_intel_braswell_config *config = config_of(dev);
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
/* Set the value for PCI command register. */
pci_write_config16(dev, PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
- PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
/* Use IRQ9 for SCI Interrupt */
write32((void *)(ilb_base + ACTL), 0);
@@ -302,13 +291,11 @@
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++)
- write8((void *)(pr_base + i*sizeof(ir->pic[i])),
- ir->pic[i]);
+ write8((void *)(pr_base + i*sizeof(ir->pic[i])), ir->pic[i]);
/* Set up the per device PIRQ routing base on static config. */
for (i = 0; i < NUM_IR_DEVS; i++)
- write16((void *)(ir_base + i*sizeof(ir->pcidev[i])),
- ir->pcidev[i]);
+ write16((void *)(ir_base + i*sizeof(ir->pcidev[i])), ir->pcidev[i]);
/* Interrupt 9 should be level triggered (SCI) */
i8259_configure_irq_trigger(9, 1);
@@ -320,11 +307,10 @@
if (config->disable_slp_x_stretch_sus_fail) {
printk(BIOS_DEBUG, "Disabling slp_x stretching.\n");
- write32(gen_pmcon1,
- read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
+ write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP);
+
} else {
- write32(gen_pmcon1,
- read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
+ write32(gen_pmcon1, read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
}
/* Write IRQ assignments to PCI config space */
@@ -347,17 +333,17 @@
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(struct device *dev)
{
- void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
+ void *func_dis = (void *)(PMC_BASE_ADDRESS + FUNC_DIS);
void *func_dis2 = (void *)(PMC_BASE_ADDRESS + FUNC_DIS2);
- uint32_t mask = 0;
+ uint32_t mask = 0;
uint32_t mask2 = 0;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
#define SET_DIS_MASK(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
mask |= name_ ## _DIS
+
#define SET_DIS_MASK2(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \
mask2 |= name_ ## _DIS
@@ -423,13 +409,13 @@
if (mask != 0) {
write32(func_dis, read32(func_dis) | mask);
- /* Ensure posted write hits. */
+ /* Ensure posted write hits */
read32(func_dis);
}
if (mask2 != 0) {
write32(func_dis2, read32(func_dis2) | mask2);
- /* Ensure posted write hits. */
+ /* Ensure posted write hits */
read32(func_dis2);
}
}
@@ -447,23 +433,21 @@
}
/*
- * Parts of the audio subsystem are powered by the HDA device. Therefore, one
- * cannot put HDA into D3Hot. Instead perform this workaround to make some of
- * the audio paths work for LPE audio.
+ * Parts of the audio subsystem are powered by the HDA device. Thus, one cannot put HDA into
+ * D3Hot. Instead, perform this workaround to make some of the audio paths work for LPE audio.
*/
static void hda_work_around(struct device *dev)
{
void *gctl = (void *)(TEMP_BASE_ADDRESS + 0x8);
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
/*
- * Need to set bit 0 of GCTL to take the device out of reset. However,
- * that requires setting up the 64-bit BAR.
+ * Need to set bit 0 of GCTL to take the device out of reset.
+ * However, that requires setting up the 64-bit BAR.
*/
pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0);
@@ -477,8 +461,7 @@
{
unsigned int offset;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
/*
* Parts of the HDA block are used for LPE audio as well.
@@ -497,8 +480,8 @@
}
/*
- * For some reason some of the devices don't have the capability
- * pointer set correctly. Work around this by hard coding the offset.
+ * For some reason some of the devices don't have the capability pointer set correctly.
+ * Work around this by hard coding the offset.
*/
#define DEV_CASE(name_) \
case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC)
@@ -556,8 +539,8 @@
{
uint32_t reg32;
- printk(BIOS_SPEW, "%s/%s (%s)\n",
- __FILE__, __func__, dev_name(dev));
+ printk(BIOS_SPEW, "%s/%s (%s)\n", __FILE__, __func__, dev_name(dev));
+
if (!dev->enabled) {
int slot = PCI_SLOT(dev->path.pci.devfn);
int func = PCI_FUNC(dev->path.pci.devfn);
@@ -566,8 +549,7 @@
/* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND);
- reg32 &= ~(PCI_COMMAND_MASTER |
- PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+ reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Place device in D3Hot */
@@ -588,15 +570,15 @@
}
static struct device_operations device_ops = {
- .read_resources = sc_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = NULL,
- .acpi_inject_dsdt_generator = southcluster_inject_dsdt,
- .write_acpi_tables = southcluster_write_acpi_tables,
- .init = sc_init,
- .enable = southcluster_enable_dev,
- .scan_bus = scan_static_bus,
- .ops_pci = &soc_pci_ops,
+ .read_resources = sc_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = NULL,
+ .acpi_inject_dsdt_generator = southcluster_inject_dsdt,
+ .write_acpi_tables = southcluster_write_acpi_tables,
+ .init = sc_init,
+ .enable = southcluster_enable_dev,
+ .scan_bus = scan_static_bus,
+ .ops_pci = &soc_pci_ops,
};
static const struct pci_driver southcluster __pci_driver = {
@@ -612,21 +594,21 @@
void *gen_pmcon2 = (void *)(PMC_BASE_ADDRESS + GEN_PMCON2);
void *etr = (void *)(PMC_BASE_ADDRESS + ETR);
uint8_t *spi = (uint8_t *)SPI_BASE_ADDRESS;
+
struct vscc_config cfg;
- printk(BIOS_SPEW, "%s/%s (%p)\n",
- __FILE__, __func__, unused);
+ printk(BIOS_SPEW, "%s/%s (%p)\n", __FILE__, __func__, unused);
- /* Set the lock enable on the BIOS control register. */
+ /* Set the lock enable on the BIOS control register */
write32(bcr, read32(bcr) | BCR_LE);
- /* Set BIOS lock down bit controlling boot block size and swapping. */
+ /* Set BIOS lock down bit controlling boot block size and swapping */
write32(gcs, read32(gcs) | BILD);
- /* Lock sleep stretching policy and set SMI lock. */
+ /* Lock sleep stretching policy and set SMI lock */
write32(gen_pmcon2, read32(gen_pmcon2) | SLPSX_STR_POL_LOCK | SMI_LOCK);
- /* Set the CF9 lock. */
+ /* Set the CF9 lock */
write32(etr, read32(etr) | CF9LOCK);
spi_finalize_ops();
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index c822a75..13992d4 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -32,9 +32,10 @@
unsigned int cpu_bus_freq_khz(void)
{
msr_t clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL);
- if ((clk_info.lo & 0xF)
- < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int)))
- return cpu_bus_clk_freq_table[clk_info.lo & 0xF];
+
+ if ((clk_info.lo & 0xf) < (sizeof(cpu_bus_clk_freq_table) / sizeof(unsigned int)))
+ return cpu_bus_clk_freq_table[clk_info.lo & 0xf];
+
return 0;
}
@@ -55,7 +56,7 @@
msr_t perf_ctl;
msr_t msr;
- /* Enable speed step. */
+ /* Enable Intel SpeedStep */
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
wrmsr(IA32_MISC_ENABLE, msr);
@@ -65,19 +66,13 @@
msr.hi = 0;
wrmsr(IA32_MISC_ENABLE, msr);
- /*
- * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
- * the PERF_CTL.
- */
+ /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of the PERF_CTL */
msr = rdmsr(MSR_IACORE_TURBO_RATIOS);
- perf_ctl.lo = (msr.lo & 0x3f0000) >> 8;
+ perf_ctl.lo = (msr.lo & 0x003f0000) >> 8;
- /*
- * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of
- * the PERF_CTL.
- */
+ /* Set guaranteed vid [21:16] from IACORE_VIDS to bits [7:0] of the PERF_CTL */
msr = rdmsr(MSR_IACORE_TURBO_VIDS);
- perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16;
+ perf_ctl.lo |= (msr.lo & 0x007f0000) >> 16;
perf_ctl.hi = 0;
wrmsr(IA32_PERF_CTL, perf_ctl);
diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c
index 60d9969..3a2626f 100644
--- a/src/soc/intel/braswell/xhci.c
+++ b/src/soc/intel/braswell/xhci.c
@@ -35,12 +35,10 @@
if (config->usb_comp_bg) {
struct reg_script ops[] = {
- REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG,
- config->usb_comp_bg),
+ REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, config->usb_comp_bg),
REG_SCRIPT_END
};
- printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n",
- config->usb_comp_bg);
+ printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg);
reg_script_run(ops);
}
}