broadcom: Remove SoC and board support
The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.
* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries
Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/Documentation/util.md b/Documentation/util.md
index 59f2c3b..d76c294 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -18,7 +18,6 @@
`Yacc`
* __board_status__ - Tools to collect logs and upload them to the board
status repository `Bash` `Go`
-* __broadcom__ - Generate Broadcom secure boot image. `C`
* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
file `Python`
* __cbfstool__
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ff21a8..810bb35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -404,12 +404,10 @@
F: src/cpu/allwinner/
F: src/cpu/armltd/
F: src/cpu/ti/
-F: src/soc/broadcom/
F: src/soc/marvell/
F: src/soc/qualcomm/
F: src/soc/samsung/
F: util/arm_boot_tools/
-F: util/broadcom/
F: util/exynos/
F: util/ipqheader/
diff --git a/Makefile.inc b/Makefile.inc
index aaae7bc..1d6a671 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -93,7 +93,7 @@
subdirs-y += src/superio
subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
subdirs-y += src/cpu src/vendorcode
-subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
+subdirs-y += util/cbfstool util/sconfig util/nvramtool
subdirs-y += util/futility util/marvell util/bincfg
subdirs-y += $(wildcard src/arch/*)
subdirs-y += src/mainboard/$(MAINBOARDDIR)
diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig
deleted file mode 100644
index 0453b5e..0000000
--- a/src/mainboard/google/purin/Kconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_PURIN
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
- select BOARD_ROMSIZE_KB_2048
- select COMMON_CBFS_SPI_WRAPPER
- select MAINBOARD_HAS_CHROMEOS
- select SOC_BROADCOM_CYGNUS
- select SPI_FLASH
- select SPI_FLASH_SPANSION
- select SPI_FLASH_STMICRO # required for the reference board BCM958305K
- select MAINBOARD_HAS_I2C_TPM_GENERIC
- select MAINBOARD_HAS_TPM1
-
-config VBOOT
- select VBOOT_VBNV_FLASH
-
-config MAINBOARD_DIR
- string
- default google/purin
-
-config MAINBOARD_PART_NUMBER
- string
- default "Purin"
-
-config MAINBOARD_VENDOR
- string
- default "Google"
-
-config DRAM_SIZE_MB
- int
- default 256
-
-config GBB_HWID
- string
- depends on CHROMEOS
- default "Purin TEST 1"
-endif # BOARD_GOOGLE_PURIN
diff --git a/src/mainboard/google/purin/Kconfig.name b/src/mainboard/google/purin/Kconfig.name
deleted file mode 100644
index db960087..0000000
--- a/src/mainboard/google/purin/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_PURIN
- bool "Purin"
diff --git a/src/mainboard/google/purin/Makefile.inc b/src/mainboard/google/purin/Makefile.inc
deleted file mode 100644
index 5f13a8b..0000000
--- a/src/mainboard/google/purin/Makefile.inc
+++ /dev/null
@@ -1,36 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt
deleted file mode 100644
index 878db18..0000000
--- a/src/mainboard/google/purin/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Purin Broadcom Cygnus reference board
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/purin/boardid.c b/src/mainboard/google/purin/boardid.c
deleted file mode 100644
index 901d837..0000000
--- a/src/mainboard/google/purin/boardid.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-
-uint32_t board_id(void)
-{
- return -1;
-}
diff --git a/src/mainboard/google/purin/bootblock.c b/src/mainboard/google/purin/bootblock.c
deleted file mode 100644
index 18c1f5f..0000000
--- a/src/mainboard/google/purin/bootblock.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 20145Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-
-void bootblock_mainboard_init(void)
-{
-}
diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c
deleted file mode 100644
index 5e7cdfe..0000000
--- a/src/mainboard/google/purin/chromeos.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-}
-
-int get_recovery_mode_switch(void)
-{
- return 0;
-}
-
-int get_write_protect_state(void)
-{
- return 0;
-}
diff --git a/src/mainboard/google/purin/chromeos.fmd b/src/mainboard/google/purin/chromeos.fmd
deleted file mode 100644
index 3f4ca84..0000000
--- a/src/mainboard/google/purin/chromeos.fmd
+++ /dev/null
@@ -1,32 +0,0 @@
-FLASH@0x0 0x200000 {
- WP_RO@0x0 0x100000 {
- RO_SECTION@0x0 0xf0000 {
- BOOTBLOCK@0 128K
- COREBOOT(CBFS)@0x20000 0x60000
- FMAP@0x80000 0x1000
- GBB@0x81000 0x6ef00
- RO_FRID@0xeff00 0x100
- }
- RO_VPD@0xf0000 0x10000
- }
- RW_SECTION_A@0x100000 0x58000 {
- VBLOCK_A@0x0 0x2000
- FW_MAIN_A(CBFS)@0x2000 0x55f00
- RW_FWID_A@0x57f00 0x100
- }
- RW_SHARED@0x158000 0x4000 {
- SHARED_DATA@0x0 0x4000
- }
- RW_ELOG@0x15c000 0x4000
- RW_GPT@0x160000 0x20000 {
- RW_GPT_PRIMARY@0x0 0x10000
- RW_GPT_SECONDARY@0x10000 0x10000
- }
- RW_SECTION_B@0x180000 0x58000 {
- VBLOCK_B@0x0 0x2000
- FW_MAIN_B(CBFS)@0x2000 0x55f00
- RW_FWID_B@0x57f00 0x100
- }
- RW_VPD@0x1d8000 0x8000
- RW_NVRAM@0x1e0000 0x10000
-}
diff --git a/src/mainboard/google/purin/devicetree.cb b/src/mainboard/google/purin/devicetree.cb
deleted file mode 100644
index 6ef5c3b..0000000
--- a/src/mainboard/google/purin/devicetree.cb
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/broadcom/cygnus
- device cpu_cluster 0 on end
-end
diff --git a/src/mainboard/google/purin/mainboard.c b/src/mainboard/google/purin/mainboard.c
deleted file mode 100644
index bc7b545..0000000
--- a/src/mainboard/google/purin/mainboard.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <boot/coreboot_tables.h>
-#include <symbols.h>
-
-static void mainboard_init(struct device *dev)
-{
-}
-
-static void mainboard_enable(struct device *dev)
-{
- dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
- .enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
- struct lb_range *dma;
-
- dma = (struct lb_range *)lb_new_record(header);
- dma->tag = LB_TAB_DMA;
- dma->size = sizeof(*dma);
- dma->range_start = (uintptr_t)_dma_coherent;
- dma->range_size = _dma_coherent_size;
-}
diff --git a/src/mainboard/google/purin/memlayout.ld b/src/mainboard/google/purin/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/purin/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c
deleted file mode 100644
index 51a2187..0000000
--- a/src/mainboard/google/purin/reset.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <reset.h>
-
-void do_board_reset(void)
-{
-}
diff --git a/src/soc/broadcom/Kconfig b/src/soc/broadcom/Kconfig
deleted file mode 100644
index 18c46c1..0000000
--- a/src/soc/broadcom/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-# Load all chipsets
-source "src/soc/broadcom/*/Kconfig"
diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig
deleted file mode 100644
index e2f97e4..0000000
--- a/src/soc/broadcom/cygnus/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-config SOC_BROADCOM_CYGNUS
- bool
- default n
- select ARCH_BOOTBLOCK_ARMV7
- select ARCH_RAMSTAGE_ARMV7
- select ARCH_ROMSTAGE_ARMV7
- select ARCH_VERSTAGE_ARMV7
- select BOOTBLOCK_CONSOLE
- select GENERIC_UDELAY
- select HAVE_MONOTONIC_TIMER
- select HAVE_UART_SPECIAL
- select GENERIC_GPIO_LIB
-
-if SOC_BROADCOM_CYGNUS
-
-config VBOOT
- select VBOOT_STARTS_IN_BOOTBLOCK
- select VBOOT_SEPARATE_VERSTAGE
- select VBOOT_RETURN_FROM_VERSTAGE
-
-config CONSOLE_SERIAL_UART_ADDRESS
- hex
- depends on DRIVERS_UART
- default 0x18023000
-
-config CYGNUS_DDR333
- def_bool n
-
-config CYGNUS_DDR400
- def_bool n
-
-config CYGNUS_DDR533
- def_bool n
-
-config CYGNUS_DDR667
- def_bool n
-
-config CYGNUS_DDR800
- bool "DDR Speed at 800MHz"
- default y
-
-config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
- bool "Enable DDR auto self-refresh"
- default y
- help
- Warning: M0 expects that auto self-refresh is enabled. Modify
- with caution.
-
-
-config CYGNUS_SHMOO_REUSE_DDR_32BIT
- bool "Indicate if DDR width is 32-bit"
- default n
-
-config CYGNUS_SDRAM_TEST_DDR
- bool "Run a write-read test on DDR after initialization"
- default n
-
-config CYGNUS_PRINT_SHMOO_DEBUG
- bool "Print debug info for shmoo"
- default n
-
-config CYGNUS_GPIO_TEST
- bool "Run a test on gpio"
- default n
-
-endif
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
deleted file mode 100644
index 21c5806..0000000
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ /dev/null
@@ -1,100 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y)
-
-bootblock-y += bootblock.c
-bootblock-y += cbmem.c
-bootblock-y += i2c.c
-bootblock-y += timer.c
-bootblock-y += tz.c
-bootblock-y += hw_init.c
-bootblock-$(CONFIG_SPI_FLASH) += spi.c
-ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
-bootblock-y += ns16550.c
-endif
-
-verstage-y += i2c.c
-verstage-y += timer.c
-verstage-$(CONFIG_SPI_FLASH) += spi.c
-verstage-y += ns16550.c
-
-romstage-y += cbmem.c
-romstage-y += i2c.c
-romstage-y += timer.c
-romstage-y += romstage.c
-romstage-y += sdram.c
-romstage-$(CONFIG_SPI_FLASH) += spi.c
-romstage-y += ns16550.c
-romstage-y += ddr_init.c
-romstage-y += ddr_init_table.c
-romstage-y += shmoo_and28.c
-romstage-y += phy_reg_access.c
-romstage-y += ydc_ddr_bist.c
-romstage-y += timer.c
-romstage-y += gpio.c
-romstage-y += iomux.c
-
-ramstage-y += cbmem.c
-ramstage-y += i2c.c
-ramstage-y += sdram.c
-ramstage-y += soc.c
-ramstage-y += timer.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
-ramstage-y += ns16550.c
-ramstage-y += usb.c
-
-CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
-
-ifneq ($(V),1)
-redirect := > /dev/null
-endif
-
-# Options used in the command line:
-# -out: path of the output file
-# -config: path to the file containing unauth header
-# -hmac: path to the file containing hmac for sha256
-# -bl: boot image file, ie. input file
-#
-# Authenticated header parameters:
-#
-# SBIConfiguration /* Indicates SBI config */
-# SYMMETRIC 0x0040
-#
-# CustomerID; /* Customer ID */
-# TYPE bits [31-28]
-# PRODUCTION 0x6
-# DEVELOPMENT 0x9
-# CUSTOMER_ID bits [27-0]
-#
-# ProductID; /* Product ID */
-#
-# CustomerRevisionID; /* Customer Revision ID */
-#
-# SBIUsage /* Boot Image Usage */
-# NONE 0 /* All purposes */
-# SLEEP 1
-# DEEP_SLEEP 2
-# EXCEPTION 4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
- $(objutil)/broadcom/secimage/secimage \
- util/broadcom/unauth.cfg \
- util/broadcom/khmacsha256
- @printf " SIGN $(subst $(obj)/,,$(@))\n"
- $(objutil)/broadcom/secimage/secimage -out $@ \
- -config util/broadcom/unauth.cfg \
- -hmac util/broadcom/khmacsha256 -bl $<
-
-endif
diff --git a/src/soc/broadcom/cygnus/bootblock.c b/src/soc/broadcom/cygnus/bootblock.c
deleted file mode 100644
index d24895e..0000000
--- a/src/soc/broadcom/cygnus/bootblock.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <bootblock_common.h>
-#include <stddef.h>
-#include <symbols.h>
-#include <soc/hw_init.h>
-
-void bootblock_soc_init(void)
-{
- /*
- * not only for speed but for preventing the CPU from crashing.
- * the CPU is not happy when cache is cleaned without mmu turned on.
- */
- mmu_init();
- mmu_config_range(0, 4096, DCACHE_OFF);
- mmu_config_range_kb((uintptr_t)_sram/KiB, _sram_size/KiB,
- DCACHE_WRITETHROUGH);
- dcache_mmu_enable();
-
- hw_init();
-}
diff --git a/src/soc/broadcom/cygnus/cbmem.c b/src/soc/broadcom/cygnus/cbmem.c
deleted file mode 100644
index 544303b..0000000
--- a/src/soc/broadcom/cygnus/cbmem.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stddef.h>
-#include <symbols.h>
-#include <soc/sdram.h>
-
-void *cbmem_top(void)
-{
- return _dram + sdram_size_mb()*MiB;
-}
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
deleted file mode 100644
index e00ae91..0000000
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ /dev/null
@@ -1,1672 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#include <delay.h>
-#include <console/console.h>
-#include <soc/config.h>
-#include <soc/reg_utils.h>
-
-#define DDR_CTL_TYPE_1 1
-#define DDR_DRAM_TYPE_DDR3L 31
-
-extern unsigned int ddr_init_tab[];
-#ifdef DDR2_SUPPORT
-extern unsigned int ddr2_init_tab[];
-extern unsigned int ddr2_init_tab_400[];
-extern unsigned int ddr2_init_tab_667[];
-extern unsigned int ddr2_init_tab_800[];
-extern unsigned int ddr2_init_tab_1066[];
-extern unsigned int ddr2_mode_reg_tab[];
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
-#define CYGNUS_DRAM_FREQ 333
-extern unsigned int ddr3_init_tab_667[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
-#define CYGNUS_DRAM_FREQ 400
-extern unsigned int ddr3_init_tab_800[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
-#define CYGNUS_DRAM_FREQ 533
-extern unsigned int ddr3_init_tab_1066[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
-#define CYGNUS_DRAM_FREQ 667
-extern unsigned int ddr3_init_tab_1333[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-#define CYGNUS_DRAM_FREQ 800
-extern unsigned int ddr3_init_tab_1600[];
-#endif
-
-#define __udelay udelay
-
-/* Local function prototype */
-uint32_t change_ddr_clock(uint32_t clk);
-void dump_phy_regs(void);
-void ddr_init_regs(unsigned int * tblptr);
-void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr);
-void ddr_phy_wl_regs_ovrd(unsigned int * tblptr);
-int is_ddr_32bit(void);
-uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit);
-int cygnus_phy_powerup(void);
-void ddr_init2(void);
-void PRE_SRX(void);
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-void PRE_SRX(void)
-{
- uint32_t readvalue = 0;
-
- // Disable low power receivers: bit 0 of the byte lane STATIC_PAD_CTL register
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL,
- (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
-
- // Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1)
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL,
- (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
-
- // Byte lane 0 power up
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
- (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
-
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
- (readvalue & 0xffff800f));
-
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
- (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
-
- // Byte lane 1 power up
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
- (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
-
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
- (readvalue & 0xffff800f));
-
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
- (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
-
- // Turn on PHY_CONTROL AUTO_OEB C not required
- // Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a
-
- printk(BIOS_INFO, "\n....PLL power up.\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
- ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
-
- // PLL out of reset
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
- ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
- printk(BIOS_INFO, "\n....poll lock..\n");
- // Poll lock
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
- while ((readvalue & 0x1) == 0x0)
- {
- printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue);
- readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
- }
- printk(BIOS_INFO, "\n....after while..\n");
-
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
- ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
-
- printk(BIOS_INFO, "\n....remove hold..\n");
- // Remove hold
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
- ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
- printk(BIOS_INFO, "\n....restore dac..\n");
-
- // Restore DAC
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
- printk(BIOS_INFO, "\n....set iddq bit..\n");
-
- // Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers.
- // Do NOT assert any other bits in the idle control register. (This step can be done during init on power up.)
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
- ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
- printk(BIOS_INFO, "\n....idle pad enable 0..\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0);
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0);
- printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n");
- reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
- (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
- ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
-}
-
-#endif
-
-#if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7)
-void iproc_ddr_ovrd_ecc_lane(void)
-{
- uint32_t val;
-
-#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F)) /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN);
- val = SET_OVR_STEP(val & 0xff);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_DATA_DLY);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_DATA_DLY, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_CONTROL, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_IDLE_PAD_CONTROL);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_DRIVE_PAD_CTL);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_DRIVE_PAD_CTL, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_WR_PREAMBLE_MODE);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE, val);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
- __udelay(200);
- reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_FIFO_CLEAR, 0x1);
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
- __udelay(200);
-}
-
-uint32_t iproc_read_ecc_syndrome(void)
-{
- volatile uint32_t syndrome = 0;
- /* Place uncorrectible as bits 7:0, and correctible as 15:8 */
- syndrome = ((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 3) & 0x1) |
- (((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 5) & 0x1));
- return(syndrome);
-}
-
-void iproc_clear_ecc_syndrome(void)
-{
- uint32_t val;
-
- /* Clear the interrupts, bits 6:3 */
- reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, (1 << 5) | (1<< 3));
- __udelay(1000);
-}
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit)
-{
- uint32_t ndiv, mdiv, pdiv, ddrclk, data;
-
- data = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_DIVIDERS);
-
- ndiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R;
- ndiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH) - 1;
-
- pdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R;
- pdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH) - 1;
-
- mdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R;
- mdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH) - 1;
-
- /* read ndiv pdiv and mdiv */
- ddrclk = (25 * ndiv * 2 * pdiv) / mdiv;
- printk(BIOS_INFO, "%s DDR PHY PLL divisor: ndiv(0x%x) mdiv(0x%x) ddrclk(0x%x)\n", __FUNCTION__, ndiv, mdiv, ddrclk);
-
- return(ddrclk);
-}
-
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-
-int cygnus_phy_powerup(void)
-{
- int data;
- int count = 15;
-
- data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
-
- if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
- {
- /* Step 1: POWER ON */
- data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
- data |= 0x8;// assert power ON
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
- __udelay(2);
-
- /* Step 2: POWER OK */
- data |= 0x10;// assert power OK
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
- while (count--)
- __udelay(2);
-
- }
- else
- {
- printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 1\n");
- }
-
- /* Step 3: DFI normal mode */
- data &= ~(0x04);// remove DFI isolation
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-
- /* Step 4: Enable register access */
- data &= ~(0x02);// remove PHY register isolation
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
- data &= ~(0x01);// remove PLL isolation
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
- count = 20;
- while (count--)
- __udelay(2);
-
- if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
- {
- /* Step 5: release reset */
- data |= 0x20;// de-assert reset
- reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
- }
- else
- {
- printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 2\n");
- }
- while ((reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x08) != 0x08) {
- //poll DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb
- }
-
- return 0;
-}
-
-#endif
-
-uint32_t change_ddr_clock(uint32_t clk)
-{
- return(0);
-}
-
-void dump_phy_regs(void)
-{
- int i;
- printk(BIOS_DEBUG, "\n PHY register dump: Control registers\n");
- for (i = 0; i <= 0x94; i+=4)
- {
- printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
- *(volatile uint32_t *)(DDR_PHY_CONTROL_REGS_REVISION + i));
- }
-
- printk(BIOS_DEBUG, "\n PHY register dump: Wordlane0 registers\n");
- for (i = 0; i <= 0xc5; i+=4)
- {
- printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
- *(volatile uint32_t *)(DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P + i));
- }
-
- return;
-}
-
-void ddr_init_regs(unsigned int * tblptr)
-{
- unsigned int offset = *tblptr;
- unsigned int *addr = (unsigned int *)DDR_DENALI_CTL_00;
-
- while (offset != 0xffffffff) {
- ++tblptr;
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
- addr[offset] = *tblptr;
-#else
- addr[offset] = swap_u32(*tblptr);
-#endif
- ++tblptr;
- offset = *tblptr;
- }
-}
-
-void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr)
-{
- unsigned int offset = *tblptr;
- unsigned int *addr = (unsigned int *)DDR_PHY_CONTROL_REGS_REVISION;
- unsigned int val;
-
- while (offset != 0xffffffff) {
- ++tblptr;
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
- addr[offset/4] = *tblptr;
-#else
- addr[offset/4] = swap_u32(*tblptr);
-#endif
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
- if (val) ;
- ++tblptr;
- offset = *tblptr;
- }
-}
-
-void ddr_phy_wl_regs_ovrd(unsigned int * tblptr)
-{
-}
-
-/*DDR_SHMOO_RELATED_CHANGE*/
-
-#ifdef CONFIG_RUN_DDR_SHMOO
-int ReWriteModeRegisters(void)
-{
- int nRet = 0;
- int j = 100;
-
- reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89, 1 << 18);
-
- /* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */
- reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25));
-
- /* Trigger Mode Register Write(MRW) sequence */
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43, 1 << 25);
-
- do {
- if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {
- break;
- }
- --j;
- } while (j);
-
- if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {
- printk(BIOS_ERR, "Error: DRAM mode registers write failed\n");
- nRet = 1;
- };
-
- return nRet;
-}
-#endif /* CONFIG_RUN_DDR_SHMOO */
-
-
-int is_ddr_32bit(void)
-{
- int ddr32 = 0;
-
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)
- ddr32=1;
-#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */
-
- return ddr32;
-}
-
-
-static uint32_t get_ddr_clock(uint32_t sku_id, int ddr_type)
-{
-#ifdef CYGNUS_DRAM_FREQ
- return CYGNUS_DRAM_FREQ;
-#else
- #error Please set DDR frequency (CYGNUS_DRAM_FREQ must be set)
-#endif
-}
-
-#if defined(CONFIG_SHMOO_REUSE) || defined(CONFIG_SHMOO_AND28_REUSE)
-
-#define RAND_MAGIC_1 0x0000444BUL
-#define RAND_MAGIC_2 0x88740000UL
-#define RAND_MAGIC_3 69069UL
-#define RAND_SEED 0x5301beef
-#define RAND_SEED_2 ((RAND_SEED << 21) + (RAND_SEED << 14) + (RAND_SEED << 7))
-#define RAND_C_INIT (((RAND_SEED_2 + RAND_MAGIC_1) << 1) + 1)
-#define RAND_T_INIT ((RAND_SEED_2 << (RAND_SEED_2 & 0xF)) + RAND_MAGIC_2)
-
-static int simple_memory_test(void *start, uint32_t len)
-{
- register uint32_t rand_c_value, rand_t_value, rand_value;
- register uint32_t i;
- register volatile uint32_t *paddr;
-
- len /= 4;
- paddr = (volatile uint32_t *)start;
- rand_c_value = RAND_C_INIT;
- rand_t_value = RAND_T_INIT;
- for (i=0; i<len; i++, paddr++) {
- rand_c_value *= RAND_MAGIC_3;
- rand_t_value ^= rand_t_value >> 15;
- rand_t_value ^= rand_t_value << 17;
- rand_value = rand_t_value ^ rand_c_value;
- *paddr = rand_value;
- }
-
- paddr = (volatile uint32_t *)start;
- rand_c_value = RAND_C_INIT;
- rand_t_value = RAND_T_INIT;
- for (i=0; i<len; i++, paddr++) {
- rand_c_value *= RAND_MAGIC_3;
- rand_t_value ^= rand_t_value >> 15;
- rand_t_value ^= rand_t_value << 17;
- rand_value = rand_t_value ^ rand_c_value;
- if (*paddr != rand_value) {
- return -1;
- }
- }
-
- return 0;
-}
-
-#endif /* CONFIG_SHMOO_REUSE || CONFIG_SHMOO_AND28_REUSE */
-
-#if defined(CONFIG_RUN_DDR_SHMOO2) && defined(CONFIG_SHMOO_REUSE)
-
-#define SHMOO_HEADER_MAGIC "SHMO"
-#define SHMOO_MIN_BLOCK_SIZE 0x10000
-
-static const uint16_t ddr_phy_ctl_regs[] = {
- 0x030,
- 0x034,
- 0x06c
-};
-
-static const uint16_t ddr_phy_wl_regs[] = {
- 0x000,
- 0x004,
- 0x008,
- 0x00c,
- 0x010,
- 0x014,
- 0x018,
- 0x01c,
- 0x020,
- 0x024,
- 0x028,
- 0x02c,
- 0x030,
- 0x034,
- 0x038,
- 0x03c,
- 0x040,
- 0x044,
- 0x048,
- 0x04c,
- 0x050,
- 0x054,
- 0x058,
- 0x05c,
- 0x060,
- 0x064,
- 0x068,
- 0x06c,
- 0x070,
- 0x074,
- 0x0a4,
- 0x0a8,
- 0x0ac,
- 0x0b0,
- 0x0b4,
- 0x0b8,
- 0x0bc,
- 0x0c0,
- 0x0c4,
- 0x0c8,
- 0x0cc,
- 0x0d0,
- 0x0d4,
- 0x0d8,
- 0x0dc,
- 0x0e0,
- 0x0e4,
- 0x0e8,
- 0x0ec,
- 0x0f0,
- 0x0f4,
- 0x0f8,
- 0x0fc,
- 0x100,
- 0x104,
- 0x108,
- 0x10c,
- 0x110,
- 0x114,
- 0x118,
- 0x11c,
- 0x120,
- 0x124,
- 0x128,
- 0x12c,
- 0x130,
- 0x134,
- 0x138,
- 0x13c,
- 0x140,
- 0x144,
- 0x148,
- 0x14c,
- 0x150,
- 0x154,
- 0x158,
- 0x15c,
- 0x160,
- 0x164,
- 0x168,
- 0x16c,
- 0x1a0,
- 0x1a4,
- 0x1a8,
- 0x1ac,
- 0x1b0
-};
-#if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7)
-static const uint16_t ddr_phy_eccl_regs[] = {
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N_BASE,
- DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE,
- DDR_PHY_ECC_LANE_READ_DATA_DLY_BASE,
- DDR_PHY_ECC_LANE_READ_CONTROL_BASE,
- DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL_BASE,
- DDR_PHY_ECC_LANE_DRIVE_PAD_CTL_BASE,
- DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE_BASE,
-};
-#endif
-#if defined(CONFIG_IPROC_NAND) && defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
- nand_info_t *nand;
- int ret = 0;
- uint32_t offset = CONFIG_SHMOO_REUSE_NAND_OFFSET;
- uint32_t end = offset + CONFIG_SHMOO_REUSE_NAND_RANGE;
- uint32_t blksize;
-
- /* Get flash handle */
- nand = &nand_info[0];
- if (nand->size < offset || nand->writesize == 0 || nand->erasesize == 0) {
- printk(BIOS_ERR, "Failed to initialize NAND flash for saving Shmoo values!\n");
- return -1;
- }
-
- /* For NAND with bad blocks, we always erase all blocks in the range */
- {
- nand_erase_options_t opts;
- memset(&opts, 0, sizeof(opts));
- opts.offset = offset / nand->erasesize * nand->erasesize;
- opts.length = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / nand->erasesize * nand->erasesize + 1;
- opts.quiet = 1;
- ret = nand_erase_opts(nand, &opts);
- if (ret) {
- printk(BIOS_ERR, "NAND flash erase failed, error=%d\n", ret);
- return ret;
- }
- }
-
- /* Write data */
- blksize = nand->erasesize > SHMOO_MIN_BLOCK_SIZE?
- nand->erasesize : SHMOO_MIN_BLOCK_SIZE;
- while (offset < end) {
- if (nand_block_isbad(nand, offset)) {
- offset += blksize;
- continue;
- }
- ret = nand_write(nand, offset, (size_t *)&length, (u_char *)buf);
- if (ret) {
- printk(BIOS_ERR, "NAND flash write failed, error=%d\n", ret);
- }
- break;
- }
-
- return ret;
-}
-
-#elif defined(CONFIG_SPI_FLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_IS_IN_SPI_FLASH
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
- struct spi_flash flash;
- int erase = 0;
- volatile uint32_t *flptr;
- int i, j, ret = 0;
- uint32_t offset = CONFIG_SHMOO_REUSE_QSPI_OFFSET;
-
- /* Check if erasing is required */
- flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + offset / 4 * 4);
- j = (length - 1) / 4 + 1;
- for (i=0; i<j; i++, flptr++) {
- if (*flptr != 0xFFFFFFFF) {
- erase = 1;
- break;
- }
- }
-
- /* Probe flash */
- if (spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, &flash)) {
- printk(BIOS_ERR, "Failed to initialize SPI flash for saving Shmoo values!\n");
- return -1;
- }
-
- /* Erase if necessary */
- if (erase) {
- ret = spi_flash_erase(
- &flash,
- offset / flash->sector_size * flash->sector_size,
- flash->sector_size
- );
- if (ret) {
- printk(BIOS_ERR, "SPI flash erase failed, error=%d\n", ret);
- return ret;
- }
- }
-
- /* Write data */
- ret = spi_flash_write(&flash, offset, length, buf);
- if (ret) {
- printk(BIOS_ERR, "SPI flash write failed, error=%d\n", ret);
- }
-
- return ret;
-}
-
-#elif defined(CONFIG_ENV_IS_IN_FLASH)
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
- int erase = 0;
- volatile uint32_t *flptr, shmoo_start;
- int i, j, ret = 0;
- uint32_t offset = CONFIG_SHMOO_REUSE_NOR_OFFSET;
- int sect_len;
-
- /* Check if erasing is required */
- flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + offset / 4 * 4);
- shmoo_start = flptr;
- j = (length - 1) / 4 + 1;
- for (i=0; i<j; i++, flptr++) {
- if (*flptr != 0xFFFFFFFF) {
- erase = 1;
- break;
- }
- }
-
- sect_len = (((length / 0x20000) + 1)*0x20000 - 1);
- /* Erase if necessary */
- if (erase) {
- ret = flash_sect_erase((ulong)shmoo_start, (ulong)shmoo_start + sect_len);
- if (ret) {
- printk(BIOS_ERR, "NOR flash erase failed, error=%d, start addr: 0x%x, end addr: 0x%x\n",
- ret, (ulong)shmoo_start, (ulong)shmoo_start + sect_len);
- return ret;
- }
- }
-
- /* Write data */
- ret = flash_write((char *)buf, (ulong)shmoo_start, length);
-
- if (ret) {
- printk(BIOS_ERR, "NOR flash write failed, error=%d\n", ret);
- }
-
-
- return ret;
-
-}
-#else
- #error Flash (SPI or NAND) must be enabled
-#endif
-
-/* Return flash pointer; or NULL if validation failed */
-static volatile uint32_t *validate_flash_shmoo_values(struct shmoo_signature *psig, int *ppairs)
-{
- uint32_t dev_id, sku_id, ddr_type, ddr_clk;
- volatile uint32_t *ptr;
- volatile uint32_t *flptr;
- struct shmoo_signature sig;
- uint32_t checksum, pairs, length;
- uint32_t chksum;
- int offset;
- int i;
- int numpairs = 1;
-
- if (is_ddr_32bit()) {
- numpairs = 2;
- }
-
- /* Calculate required length (register/value pair) */
- pairs =
- sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]) +
- sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]) * numpairs;
-#ifdef CONFIG_IPROC_DDR_ECC
- pairs += sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]);
-#endif
-
- if (ppairs != NULL) {
- *ppairs = pairs;
- }
-
-#if defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND
- /* Read SHMOO data from NAND */
- flptr = (volatile uint32_t *)(IPROC_NAND_MEM_BASE + CONFIG_SHMOO_REUSE_NAND_OFFSET);
- offset = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / SHMOO_MIN_BLOCK_SIZE * SHMOO_MIN_BLOCK_SIZE;
-#elif defined(CONFIG_ENV_IS_IN_FLASH)
- /* Read SHMOO data from NOR */
- flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + CONFIG_SHMOO_REUSE_NOR_OFFSET);
- offset = 0;
-#else
- /* Read SHMOO data from SPI */
- flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + CONFIG_SHMOO_REUSE_QSPI_OFFSET);
- offset = 0;
-#endif
-
- /* Get chip type and DDR type/clock */
- dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff;
- sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
- ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1;
- ddr_clk = get_ddr_clock(sku_id, ddr_type);
-
- /* Construct signature */
- memcpy(sig.magic, SHMOO_HEADER_MAGIC, 4);
- sig.dev_id = dev_id;
- sig.sku_id = sku_id;
- sig.ddr_type = ddr_type;
- sig.ddr_clock = ddr_clk;
-
- /* Provide signature data to caller */
- if (psig) {
- memcpy(psig, &sig, sizeof(sig));
- }
-
- /* Check signature (in min-blocks from bottom) */
- while (offset >= 0) {
- ptr = flptr + offset;
- if (!shmoo_sigmemcmp(&sig,(void *)ptr)) {
- break;
- }
- offset -= SHMOO_MIN_BLOCK_SIZE;
- }
- if (offset < 0) {
- printk(BIOS_ERR, " Signature mismatch ");
- return NULL;
- }
- ptr += 3;
-
- /* Verify checksum */
- checksum = *ptr++;
- length = *ptr++;
- if (pairs != length) {
- /* Pair count unmatched */
- printk(BIOS_ERR, " Pair count mismatch pairs %x length %x",pairs, length);
- return NULL;
- }
- chksum = 0;
- for (i=0; i<length * 2; i++, ptr++) {
- chksum += *ptr;
- }
- if (chksum != checksum) {
- printk(BIOS_ERR, " Checksum mismatch cksum: %x checksum:%x",chksum,checksum);
- return NULL;
- }
-
- return flptr + offset;
-}
-
-static int try_restore_shmoo(void)
-{
- int invalid = 0;
- struct shmoo_signature sig;
- volatile uint32_t *flptr;
- volatile uint32_t *reg;
- uint32_t val;
- int pairs, i;
-
- /* Validate values in flash */
- printk(BIOS_INFO, "Validate Shmoo parameters stored in flash ..... ");
- flptr = validate_flash_shmoo_values(&sig, &pairs);
- if (flptr == NULL) {
- printk(BIOS_ERR, "failed\n");
- return 1;
- }
- printk(BIOS_INFO, "OK\n");
-
- /* Check if user wants to skip restoring and run Shmoo */
- if (CONFIG_SHMOO_REUSE_DELAY_MSECS > 0) {
- char c = 0;
- unsigned long start;
- printk(BIOS_INFO, "Press Ctrl-C to run Shmoo ..... ");
- start = get_timer(0);
- while (get_timer(start) <= CONFIG_SHMOO_REUSE_DELAY_MSECS) {
- if (tstc()) {
- c = getc();
- if (c == 0x03) {
- printk(BIOS_INFO, "Pressed.\n");
- printk(BIOS_INFO, "Do you want to run the Shmoo? [y/N] ");
- for (;;) {
- c = getc();
- if (c == 'y' || c == 'Y') {
- printk(BIOS_INFO, "Y\n");
- invalid = 1;
- break;
- } else if (c == '\r' || c == 'n' || c == 'N') {
- if (c != '\r')
- printk(BIOS_INFO, "N\n");
- break;
- }
- }
- break;
- } else {
- c = 0;
- }
- }
- }
- if (c == 0)
- printk(BIOS_INFO, "skipped\n");
- }
-
- if (invalid) {
- return 1;
- }
-
- /* Restore values from flash */
- printk(BIOS_INFO, "Restoring Shmoo parameters from flash ..... ");
- flptr += 5;
- for (i=0; i<pairs; i++) {
- reg = (uint32_t *)(*flptr++);
- val = (uint32_t *)(*flptr++);
- if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
- || (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
-#endif
-#ifdef CONFIG_IPROC_DDR_ECC
- || (((uint32_t)reg >= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE)) && ((uint32_t)reg <= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE)))
-#endif
- ) {
- val |= (1 << 17); /* Force Override */
- }
- // printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg);
- reg32_write(reg, val);
-
- reg32_read(reg); /* Dummy read back */
- }
- printk(BIOS_INFO, "done\n");
-
- /* Perform memory test to see if the parameters work */
- if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
- printk(BIOS_INFO, "Running simple memory test ..... ");
- i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
- CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
- if (i) {
- printk(BIOS_ERR, "failed!\n");
- return 1;
- }
- printk(BIOS_INFO, "OK\n");
- }
-
- return 0;
-}
-
-#define SHMOO_REG_BUFFER_SIZE 100;
-static uint32_t shmoo_reg_buffer[SHMOO_REG_BUFFER_SIZE];
-
-void iproc_save_shmoo_values(void)
-{
- uint32_t *buffer, *ptr;
- volatile uint32_t *flptr;
- uint32_t reg, val;
- struct shmoo_signature sig;
- int pairs, length;
- uint32_t chksum;
- int i;
-
- /* Check if flash already contains valid data */
- flptr = validate_flash_shmoo_values(&sig, &pairs);
- if (flptr != NULL) {
- /* Check if the flash data are the same as current DDR PHY values */
- flptr += 5;
- for (i=0; i<pairs; i++) {
- reg = *flptr++;
- val = *flptr++;
- if (val != reg32_read(reg)) {
- break;
- }
-
- }
- if (i == pairs) {
- /* No difference found; Saving skipped */
- return;
- }
- }
-
- /* Calculate size of buffer */
- length = 12 +
- sizeof(uint32_t) * 2 +
- sizeof(uint32_t) * pairs * 2;
-
- /* Allocate buffer */
- if (length > size(uint32_t) * SHMOO_REG_BUFFER_SIZE) {
- printk(BIOS_INFO, "Error pre-allocated shmoo register buffer is not large enough!\n");
- return;
- }
-
- buffer = shmoo_reg_buffer;
- ptr = buffer;
-
- /* Fill signature */
- shmoo_sig2mem(&sig,ptr);
- ptr += 5;
-
- /* Copy registers and values to buffer */
- chksum = 0;
- for (i=0; i<sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]); i++) {
- reg = (uint32_t)DDR_PHY_CONTROL_REGS_REVISION + ddr_phy_ctl_regs[i];
- *ptr++ = reg;
- chksum += reg;
- // val = *(volatile uint32_t *)reg;
- val = reg32_read((volatile uint32_t *)reg);
- *ptr++ = val;
- chksum += val;
- }
- for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
- reg = (uint32_t)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
- *ptr++ = reg;
- chksum += reg;
- // val = *(volatile uint32_t *)reg;
- val = reg32_read((volatile uint32_t *)reg);
- *ptr++ = val;
- chksum += val;
- }
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
- if (is_ddr_32bit()) {
- for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
- reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
- *ptr++ = reg;
- chksum += reg;
- // val = *(volatile uint32_t *)reg;
- val = reg32_read((volatile uint32_t *)reg);
- *ptr++ = val;
- chksum += val;
- }
- }
-#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) */
-#ifdef CONFIG_IPROC_DDR_ECC
- for (i=0; i<sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); i++) {
- reg = (uint32_t)DDR_DENALI_CTL_00 + ddr_phy_eccl_regs[i];
- *ptr++ = reg;
- chksum += reg;
- // val = *(volatile uint32_t *)reg;
- val = reg32_read((volatile uint32_t *)reg);
- *ptr++ = val;
- chksum += val;
- }
-#endif
-
- /* Fill checksum and length */
- buffer[3] = chksum;
- buffer[4] = pairs;
-
- /* Write to flash */
- printk(BIOS_INFO, "Writing Shmoo values into flash .....\n");
- i = write_shmoo_to_flash(buffer, length);
-
- /* Free buffer */
-// free(buffer);
-}
-
-#endif /* CONFIG_RUN_DDR_SHMOO2 && CONFIG_SHMOO_REUSE */
-
-#include "soc/ddr_bist.h"
-#include "soc/shmoo_and28/shmoo_and28.h"
-
-#ifdef CONFIG_IPROC_DDR_ECC
-static int clear_ddr(uint32_t offset, uint32_t size)
-{
- unsigned long start;
- unsigned int i, val;
-
- reg32_write((uint32_t *)DDR_BistConfig,
- reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
-
- for (i = 0; i < 1000; i++)
- ;
-
-#if !defined(CONFIG_IPROC_P7)
- reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);
-#endif
-
- reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000002);
- reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000003);
- reg32_write((volatile uint32_t *)DDR_BistConfig, 0x0000C003);
- reg32_write((volatile uint32_t *)DDR_BistGeneralConfigurations, 0x00000020);
-
- val = 255 << DDR_BistConfigurations__WriteWeight_R |
- 0 << DDR_BistConfigurations__ReadWeight_R |
- 1 << DDR_BistConfigurations__ConsAddr8Banks;
-
- reg32_write((volatile uint32_t *)DDR_BistConfigurations, val);
-
-
- reg32_write((volatile uint32_t *)DDR_BistStartAddress, offset);
- reg32_write((volatile uint32_t *)DDR_BistEndAddress, (1 << DDR_BistEndAddress__BistEndAddress_WIDTH) - 1);
- reg32_write((volatile uint32_t *)DDR_BistNumberOfActions, (size + 31) / 32);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord0, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord1, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord2, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord3, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord4, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord5, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord6, 0);
- reg32_write((volatile uint32_t *)DDR_BistPatternWord7, 0);
-
- reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__IndWrRdAddrMode);
-
- reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
-
- start = get_timer(0);
- while (get_timer(start) <= 10000) {
- if (reg32_read((volatile uint32_t *)DDR_BistStatuses) & (1 << DDR_BistStatuses__BistFinished))
- break;
- }
- /* Clear BIST_EN bit */
- reg32_clear_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
-
- if ((get_timer(start) <= 10000) &&
- (!reg32_read((volatile uint32_t *)DDR_BistErrorOccurred)))
- {
- printk(BIOS_INFO, "clear_ddr: OK\n");
- return(0);
- }
- printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start));
- if (reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
- printk(BIOS_ERR, "clear_ddr: Error occurred\n");
- return(1);
-}
-#endif /* CONFIG_IPROC_DDR_ECC */
-
-#if defined(CONFIG_SHMOO_AND28_REUSE)
-extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para);
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-static int simple_ddr_crc32_check(void)
-{
- return 0;
- register uint32_t crc_mcu = 0;
- register uint32_t crc = 0, offset = 0;
- register volatile uint32_t *buf = (uint32_t *)0x60000000;
- register uint32_t len = 0x00100000;//in word
-
- printk(BIOS_INFO, "Checking simple DDR CRC, word start 0x%p, len 0x%08x...\n", buf, len);
-
- for (offset=0; offset<len; offset++)
- {
- crc ^= *buf++;
- }
-
- crc_mcu = reg32_read((volatile uint32_t *)0x03012A00);
-
- if (crc != crc_mcu)
- {
- printk(BIOS_ERR, "DDR CRC NOT match, old=0x%08x, new=0x%08x!\n", crc_mcu, crc);
- return -1;
- }
- else
- {
- printk(BIOS_INFO, "DDR CRC 0x%08x, match!\n", crc);
- return 0;
- }
-}
-#endif
-
-void ddr_init2(void)
-{
- int i;
- volatile unsigned int val;
- int ddr_type;
- uint32_t status, sku_id, ddr_clk, dev_id = 0;
- uint32_t unit = 0;
- uint32_t skip_shmoo = 0;
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS) & 0x3;
- skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1;
-
- if (pwrctli0==2)
- {
- goto wakeup;
- }
- else if (pwrctli0==3)
- {
- skip_shmoo = 1;
- reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1);
- }
-#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
-
- dev_id = dev_id;
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- and28_shmoo_dram_info_t sdi;
- and28_shmoo_config_param_t config_param;
-#endif
-
-#if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff;
-#else
- dev_id = 0x5800;
- cygnus_phy_powerup();
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f;
-#else
- sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
-#endif
- /* See if it is KATANA2, KATANA2 doesn't have right chip ID in ChipcommonA_ChipID */
- if (((sku_id & 0xfff0) == 0xa450) || ((sku_id & 0xfff0) == 0xb450) || sku_id == 0xb248) {
- dev_id = 56450; /* KATANA2 */
- }
-
- printk(BIOS_INFO, "DEV ID = 0x%x\n", dev_id);
-
- printk(BIOS_INFO, "SKU ID = 0x%x\n", sku_id);
-
-#if defined(CONFIG_IPROC_P7)
- val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x3;
- if (val == 0) {
- ddr_type = 1;
- } else if (val == 1) {
- ddr_type = 2;
- } else {
- printk(BIOS_ERR, "Unsupported DDR type: %d\n", val);
- goto done;
- }
- printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4);
-#elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- ddr_type = 1;
-#else
- ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1;
- printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type) ? 3 : 2);
-#endif /* defined(CONFIG_IPROC_P7) */
-
- ddr_clk = get_ddr_clock(sku_id, ddr_type);
- printk(BIOS_INFO, "MEMC 0 DDR speed = %dMHz\n", ddr_clk);
-
- status = change_ddr_clock(ddr_clk);
- if (status) {
- printk(BIOS_INFO, "CRU LCPLL configuratioin failed\n");
- goto done;
- }
-
-#if defined(CONFIG_IPROC_P7)
- val = reg32_read((volatile uint32_t *)CRU_ddrphy_pwr_ctrl);
-
- /* assert power ON */
- val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwronin_phy;
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* assert power OK */
- __udelay(10);
- val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwrokin_phy;
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* remove DFI isolation */
- __udelay(150);
- val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_dfi);
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* remove PHY register isolation */
- val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_regs);
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* remove PLL isolation */
- val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_pll);
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* de-assert reset */
- __udelay(200);
- val |= 1 << CRU_ddrphy_pwr_ctrl__i_hw_reset_n;
- reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
- /* Wait for PHY power up */
- for (i=0; i < 0x19000; i++) {
- val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
- if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb)))
- break;
- }
- if (i == 0x19000) {
- printk(BIOS_ERR, "DDR PHY not power up\n");
- goto done;
- }
-#endif /* defined(CONFIG_IPROC_P7) */
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7)
- /* Get the DDR S1 and S2 out of reset */
- reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0);
- reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
-
- __udelay(1000);
- reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0);
- /* Set the ddr_ck to 400 MHz, 2x memc clock */
- reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
-
- if (pwrctli0==3)
- {
- printk(BIOS_INFO, "\n PRE_SRX call\n");
- PRE_SRX();
- }
-#else
- reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0);
- reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
- /* Set the ddr_ck to 400 MHz, 2x memc clock */
- reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
-#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */
-
-#if defined(CONFIG_IPROC_P7)
- if (is_ddr_32bit()) {
- reg32_write_masked(
- (volatile uint32_t *)DDR_S2_IDM_IO_CONTROL_DIRECT,
- 1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b,
- 1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b
- );
- }
-
- /* Wait for PHY ready */
- for (i=0; i < 0x19000; i++) {
- val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
- if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_ready)))
- break; /* DDR PHY is up */
- }
-
- if (i == 0x19000) {
- printk(BIOS_ERR, "DDR PLL not locked\n");
- goto done;
- }
-
- /* Get the DDR S0 out of reset */
- reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0);
-#endif /* defined(CONFIG_IPROC_P7) */
-
- /* Wait for DDR PHY up */
- for (i=0; i < 0x19000; i++) {
- val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
- if (val != 0) {
- printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
- break; /* DDR PHY is up */
- }
- }
-
- if (i == 0x19000) {
- printk(BIOS_ERR, "DDR PHY is not up\n");
- return;
- }
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- if (!skip_shmoo)
- {
- printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
- /* Cygnus clock speed:
- *
- * clock rate
- * 400 800
- * 533 1066
- * 667 1333
- * 800 1600
- */
- sdi.data_rate_mbps = (ddr_clk == 667) ? 1333 : ((ddr_clk == 333) ? 667 : (ddr_clk << 1));
- sdi.ref_clk_mhz = 50;
- sdi.ctl_type = DDR_CTL_TYPE_1;
- sdi.dram_type = DDR_DRAM_TYPE_DDR3L;
- sdi.dram_bitmap = 0x00000001;
- sdi.interface_bitwidth = SDI_INTERFACE_BITWIDTH;
- sdi.num_columns = SDI_NUM_COLUMNS;
- sdi.num_rows = SDI_NUM_ROWS;
- sdi.num_banks = SDI_NUM_BANKS;
- sdi.refi = 7800;
- sdi.command_parity_latency = 0;
- sdi.sim_system_mode = 0;
- printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
- soc_and28_shmoo_dram_info_set(unit, &sdi);
- }
- else
- {
- printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 1\n");
- }
-#else
-#error "DRAM config is not set"
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- if (!skip_shmoo)
- {
- printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n");
- if (soc_and28_shmoo_phy_init(unit, 0) != SOC_E_NONE) {
-
- printk(BIOS_ERR, "DDR PHY initialization failed\n");
- goto done;
- }
- }
- else
- {
- printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 2\n");
- }
-#endif
-
-#ifdef CONFIG_RUN_DDR_SHMOO
- printk(BIOS_DEBUG, "PHY register dump after DDR PHY init\n");
- dump_phy_regs();
-#endif
-
- printk(BIOS_INFO, "Programming controller register\n");
- ddr_init_regs(ddr_init_tab);
-
- ddr_type = 1;
- if (ddr_type) {
- /* DDR3 */
- switch(ddr_clk) {
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
- case 333:
- ddr_init_regs(ddr3_init_tab_667);
- break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
- case 400:
- ddr_init_regs(ddr3_init_tab_800);
- break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
- case 533:
- ddr_init_regs(ddr3_init_tab_1066);
- break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
- case 667:
- ddr_init_regs(ddr3_init_tab_1333);
- break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
- case 800:
- ddr_init_regs(ddr3_init_tab_1600);
- break;
-#endif
- }
- }
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE)
-#if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff)
- /* Enable auto self-refresh */
- reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
-
- reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58,
- DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
-#else
- #error DDR_AUTO_SELF_REFRESH_IDLE_COUNT out of range
-#endif
-#else
- /* Disable auto-self refresh */
- reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57,
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
- 0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
- reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58,
- 0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
-#endif
-
- /* Start the DDR */
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- if (!skip_shmoo)
- {
- while (!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100));
- printk(BIOS_INFO, "ddr_init2: MemC initialization complete\n");
-
- reg32_set_bits((unsigned int *)DDR_DENALI_CTL_177, 0x00100);
- reg32_write((unsigned int *)DDR_BistConfig, 0x00000002);
- reg32_write((unsigned int *)DDR_BistConfig, 0x00000003);
- reg32_write((unsigned int *)DDR_BistConfig, 0x0000C003);
- reg32_write((unsigned int *)DDR_BistGeneralConfigurations, 0x00000020);
-
- printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_ctl\n");
- #if defined(CONFIG_SHMOO_AND28_REUSE)
- if (is_shmoo_data_valid()) {
- restore_shmoo_config(&config_param);
- soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RESTORE, &config_param);
-
- #if defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH)
- /* Perform memory test to see if the stored SHMMO values work */
- if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
- /* Release DDR to AXI for memory testing */
- reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
-
- printk(BIOS_INFO, "Running simple memory test ..... ");
- i = simple_memory_test(
- (void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
- CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
- if (i) {
- printk(BIOS_ERR, "failed!\n");
-
- /* Connect DDR controller to BIST for SHMOO */
- reg32_set_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
-
- /* Perform full SHMOO since stored values don't work */
- soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
- } else {
- printk(BIOS_INFO, "OK\n");
- }
- }
- #endif /* defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH) */
-
- } else {
- soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
- }
- #else
- soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
- #endif /* CONFIG_SHMOO_AND28_REUSE */
- }
-#endif
- else
- {
- printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 3\n");
- }
-
-#if defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC)
- printk(BIOS_INFO, "Enabling DDR ECC correcting and reporting\n");
-
- /* Clear DDR ECC interrupts if any */
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_177,
- DDR_DENALI_CTL_177_ECC_MASK);
-
- /* Disable auto corruption */
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_148,
- 1 << DDR_DENALI_CTL_148__ECC_DISABLE_W_UC_ERR);
-
- /* Enable ECC correction and reporting */
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_146,
- 1 << DDR_DENALI_CTL_146__ECC_EN);
-
- /* Initialize DDR so that uninitialized reads won't report ecc error */
- clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE);
-#elif defined(CONFIG_IPROC_DDR_ECC)
- printk(BIOS_INFO, "Enabling DDR ECC reporting\n");
- /* Clear DDR interrupts if any */
- *(unsigned int *)(DDR_DENALI_CTL_213) = 0x00FFFFFF;
- __udelay(1000);
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_67, 0x01); //Disable auto correction
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 0x01); //Enable ECC
-
- clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE);
- printk(BIOS_INFO, "Enabling DDR ECC correction\n");
- reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 1 << 1); //Enable ECC correction
-#endif /* defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC) */
-
- /* Release DDR slave port to AXI */
- reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
- printk(BIOS_INFO, "DDR Interface Ready\n");
-
- //dump_phy_regs();
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
- /* SRX */
- if (skip_shmoo)
- {
- // Enter Self refresh (dummy), to keep Denali happy
- reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505);
-
- __udelay(200);
- printk(BIOS_INFO, "\nDDR self refresh exit\n");
-
- // Assert DFI request from PHY to mask any interaction with MEMC
- reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0xe0);
- reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0);
-
- // Exit Self refresh
- reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x09050505);
- }
-
- /* Clear iHOST flag */
- reg32_write((unsigned int *)CRMU_IHOST_POR_WAKEUP_FLAG, 0x0);
- printk(BIOS_INFO, "IHOST POR WAKEUP FLAG cleared\n");
-
-// iproc_dump_ddr_regs();
-
- if (pwrctli0==0)
- goto done;
-
-wakeup:
- printk(BIOS_INFO, "Wakeup from %s\n", pwrctli0==2 ? "SLEEP":"DEEPSLEEP");
-
- if (pwrctli0==3)
- {
- __udelay(10000);
- if (simple_ddr_crc32_check()<0)
- {
- printk(BIOS_INFO, "Die...\n");
- while (1);
- }
- }
-
- /* CRMU_IHOST_SW_PERSISTENT_REG4 = 0x03024c64 */
- asm(
- "movw r3, #0x4c64\n"
- "movt r3, #0x0302\n"
- "ldr r5, [r3]\n"
- "mov lr, #0\n"
- "mov pc, r5\n");
-#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
-
-done:
- /* Reclaim everything we have previously allocated for temporary usage. */
-// free_heap();
- return;
-}
diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c
deleted file mode 100644
index 20eb5e6..0000000
--- a/src/soc/broadcom/cygnus/ddr_init_table.c
+++ /dev/null
@@ -1,1810 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-const unsigned int ddr_init_tab[] = {
- 0xffffffff
- };
-
-#ifdef DDR2_SUPPORT
-const unsigned int ddr2_init_tab[] = {
- 0, 0x00000400,
- 3, 0x00000043,
- 4, 0x000000a7,
- 5, 0x0a040a02,
- 6, 0x04020404,
- 7, 0x05030e14,
- 8, 0x030e1404,
- 9, 0x04020305,
- 10, 0x03005b26,
- 11, 0x04020303,
- 12, 0x03005b26,
- 13, 0x01000003,
- 16, 0x030000c8,
- 17, 0x00860000,
- 18, 0x05050086,
- 20, 0x00002301,
- 21, 0x00230a24,
- 22, 0x00050a24,
- 23, 0x00000200,
- 24, 0x000a0002,
- 25, 0x0002000a,
- 26, 0x00020008,
- 27, 0x00c80008,
- 28, 0x00c80027,
- 29, 0x00000027,
- 30, 0x03000001,
- 31, 0x00030303,
- 44, 0x00085300,
- 45, 0x00000004,
- 46, 0x00040853,
- 48, 0x08530000,
- 49, 0x00000004,
- 50, 0x00040853,
- 52, 0x08530000,
- 53, 0x00000004,
- 54, 0x00040853,
- 56, 0x08530000,
- 57, 0x00000004,
- 58, 0x00040853,
- 82, 0x01030101,
- 108, 0x02020101,
- 109, 0x08080404,
- 110, 0x03020200,
- 111, 0x01000202,
- 128, 0x001d1d00,
- 129, 0x1d1d0001,
- 133, 0x00011d1d,
- 134, 0x00011d1d,
- 137, 0x001d1d00,
- 138, 0x1d1d0001,
- 142, 0x00011d1d,
- 143, 0x00011d1d,
- 146, 0x001d1d00,
- 147, 0x1d1d0001,
- 169, 0x0a240000,
- 172, 0x00000a24,
- 173, 0x000032b4,
- 174, 0x0a240404,
- 177, 0x00000a24,
- 178, 0x000032b4,
- 179, 0x02020404,
- 186, 0x15070303,
- 202, 0x0001046b,
- 203, 0x0001046b,
- 206, 0x01030301,
- 207, 0x00000001,
- 0xffffffff
-};
-
-const unsigned int ddr2_init_tab_400[] = {
- 0, 0x00000400,
- 1, 0x00000000,
- 3, 0x00000050,
- 4, 0x000000c8,
- 5, 0x0c050c02,
- 6, 0x04020405,
- 7, 0x05031015,
- 8, 0x03101504,
- 9, 0x05020305,
- 10, 0x03006d60,
- 11, 0x05020303,
- 12, 0x03006d60,
- 13, 0x01000003,
- 14, 0x05061001,
- 15, 0x000b0b06,
- 16, 0x030000c8,
- 17, 0x00a01212,
- 18, 0x060600a0,
- 19, 0x00000000,
- 20, 0x00003001,
- 21, 0x00300c2d,
- 22, 0x00050c2d,
- 23, 0x00000200,
- 24, 0x000a0002,
- 25, 0x0002000a,
- 26, 0x00020008,
- 27, 0x00c80008,
- 28, 0x00c80037,
- 29, 0x00000037,
- 30, 0x03000001,
- 31, 0x00030303,
- 32, 0x00000000,
- 35, 0x00000000,
- 36, 0x01000000,
- 37, 0x10000000,
- 38, 0x00100400,
- 39, 0x00000400,
- 40, 0x00000100,
- 41, 0x00000000,
- 42, 0x00000001,
- 43, 0x00000000,
- 44, 0x000a6300,
- 45, 0x00000004,
- 46, 0x00040a63,
- 47, 0x00000000,
- 48, 0x0a630000,
- 49, 0x00000004,
- 50, 0x00040a63,
- 51, 0x00000000,
- 52, 0x0a630000,
- 53, 0x00000004,
- 54, 0x00040a63,
- 55, 0x00000000,
- 56, 0x0a630000,
- 57, 0x00000004,
- 58, 0x00040a63,
- 59, 0x00000000,
- 60, 0x00000000,
- 61, 0x00010100,
- 62, 0x00000000,
- 63, 0x00000000,
- 64, 0x00000000,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 78, 0x01000200,
- 79, 0x02000040,
- 80, 0x00400100,
- 81, 0x00000200,
- 82, 0x01030001,
- 83, 0x01ffff0a,
- 84, 0x01010101,
- 85, 0x03010101,
- 86, 0x01000003,
- 87, 0x0000010c,
- 88, 0x00010000,
- 89, 0x00000000,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000000,
- 99, 0x00000000,
- 100, 0x00000000,
- 101, 0x00000000,
- 102, 0x00000000,
- 103, 0x00000000,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x02020101,
- 109, 0x08080404,
- 110, 0x03020200,
- 111, 0x01000202,
- 112, 0x00000200,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 116, 0x19000000,
- 117, 0x00000028,
- 118, 0x00000000,
- 119, 0x00010001,
- 120, 0x00010001,
- 121, 0x00010001,
- 122, 0x00010001,
- 123, 0x00010001,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x001c1c00,
- 129, 0x1c1c0001,
- 130, 0x00000001,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00011c1c,
- 134, 0x00011c1c,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x001c1c00,
- 138, 0x1c1c0001,
- 139, 0x00000001,
- 140, 0x00000000,
- 141, 0x00000000,
- 142, 0x00011c1c,
- 143, 0x00011c1c,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x001c1c00,
- 147, 0x1c1c0001,
- 148, 0xffff0001,
- 149, 0x00ffff00,
- 150, 0x0000ffff,
- 151, 0x00000000,
- 152, 0x03030303,
- 153, 0x03030303,
- 156, 0x02006400,
- 157, 0x02020202,
- 158, 0x02020202,
- 160, 0x01020202,
- 161, 0x01010064,
- 162, 0x01010101,
- 163, 0x01010101,
- 165, 0x00020101,
- 166, 0x00000064,
- 167, 0x00000000,
- 168, 0x000a0a00,
- 169, 0x0c2d0000,
- 170, 0x02000200,
- 171, 0x02000200,
- 172, 0x00000c2d,
- 173, 0x00003ce1,
- 174, 0x0c2d0505,
- 175, 0x02000200,
- 176, 0x02000200,
- 177, 0x00000c2d,
- 178, 0x00003ce1,
- 179, 0x02020505,
- 180, 0x80000100,
- 181, 0x04070303,
- 182, 0x0000000a,
- 183, 0x00000000,
- 184, 0x00000000,
- 185, 0x0010ffff,
- 186, 0x16070303,
- 187, 0x0000000f,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 194, 0x00000204,
- 195, 0x00000000,
- 196, 0x00000000,
- 197, 0x00000000,
- 198, 0x00000000,
- 199, 0x00000000,
- 200, 0x00000000,
- 201, 0x00000000,
- 202, 0x00000050,
- 203, 0x00000050,
- 204, 0x00000000,
- 205, 0x00000040,
- 206, 0x01030301,
- 207, 0x00000001,
- 0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
-const unsigned int ddr3_init_tab_667[] = {
- 0, 0x00000600,
- 1, 0x00000000,
- 2, 0x00000000,
- 3, 0x00000000,
- 4, 0x00000000,
- 5, 0x00000000,
- 6, 0x00000000,
- 7, 0x00000400,
- 8, 0x00000000,
- 9, 0x00000000,
- 10, 0x00000000,
- 11, 0x00000004,
- 12, 0x00000000,
- 13, 0x00000000,
- 15, 0x0001046b,
- 16, 0x00028b0b,
- 17, 0x00000000,
- 18, 0x02000000,
- 19, 0x00050a00,
- 20, 0x00000000,
- 21, 0x00050a00,
- 22, 0x00000000,
- 23, 0x05040400,
- 24, 0x0c110004,
- 25, 0x0a050404,
- 26, 0x11000405,
- 27, 0x0504040c,
- 28, 0x0404040a,
- 29, 0x005b680c,
- 30, 0x040c0303,
- 31, 0x000c0404,
- 32, 0x03005b68,
- 33, 0x05000c03,
- 34, 0x00050505,
- 35, 0x010c0032,
- 41, 0x00000000,
- 43, 0x00570100,
- 44, 0x00000a20,
- 45, 0x00000057,
- 46, 0x00000a20,
- 47, 0x00000005,
- 48, 0x00030003,
- 49, 0x000a000a,
- 50, 0x00000000,
- 51, 0x00000000,
- 52, 0x02000000,
- 53, 0x0200005a,
- 54, 0x0000005a,
- 55, 0x05000001,
- 56, 0x00050505,
- 57, 0x00000000,
- 58, 0x00000000,
- 59, 0x00010000,
- 60, 0x10040010,
- 62, 0x00000200,
- 63, 0x00000000,
- 64, 0x00000001,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 82, 0x00000000,
- 85, 0x00000046,
- 86, 0x00000000,
- 89, 0x00000000,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000210,
- 99, 0x00000046,
- 100, 0x00000000,
- 101, 0x00000210,
- 102, 0x00000046,
- 103, 0x00000000,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x00000000,
- 109, 0x00000000,
- 110, 0x00000000,
- 111, 0x00000000,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 118, 0x00000000,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x00000000,
- 129, 0x00000000,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00000000,
- 134, 0x00000000,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x00000000,
- 138, 0x00000000,
- 140, 0x01000000,
- 141, 0x00000001,
- 142, 0x00000000,
- 143, 0x00000000,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x00000000,
- 147, 0x00000000,
- 151, 0x00000000,
- 154, 0x00000000,
- 155, 0x00000000,
- 159, 0x00400100,
- 164, 0x0a020001,
- 167, 0x01010101,
- 169, 0x00000c03,
- 172, 0x01000000,
- 173, 0x00000100,
- 174, 0x00000000,
- 177, 0x00000000,
- 178, 0x00000000,
- 179, 0x00000000,
- 183, 0x00000000,
- 184, 0x00000000,
- 186, 0x00000000,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 195, 0x00000000,
- 196, 0x01010200,
- 197, 0x00000002,
- 198, 0x06040400,
- 199, 0x00000106,
- 200, 0x00000000,
- 201, 0x02020002,
- 202, 0x02020101,
- 203, 0x02000102,
- 204, 0x00000000,
- 206, 0x00000000,
- 207, 0x00000000,
- 208, 0x00000000,
- 209, 0x0000280d,
- 210, 0x00010000,
- 211, 0x00010000,
- 212, 0x00000003,
- 213, 0x00000000,
- 214, 0x00000000,
- 215, 0x00000000,
- 216, 0x00000000,
- 217, 0x00000000,
- 218, 0x00000000,
- 219, 0x00000000,
- 220, 0x00000000,
- 221, 0x01000000,
- 222, 0x00000001,
- 223, 0x00000100,
- 224, 0x00030300,
- 225, 0x0556AA00,
- 226, 0x000aa955,
- 227, 0x000aa955,
- 228, 0x000556aa,
- 229, 0x000556aa,
- 230, 0x000aa955,
- 231, 0x000aa955,
- 232, 0x030556aa,
- 233, 0x01000001,
- 234, 0x00010300,
- 235, 0x00676700,
- 236, 0x00676700,
- 237, 0x00676700,
- 238, 0x00676700,
- 239, 0x00676700,
- 240, 0x00676700,
- 241, 0x00676700,
- 242, 0x00676700,
- 243, 0x00676700,
- 244, 0x00000000,
- 245, 0x01000000,
- 246, 0x00000001,
- 247, 0x00000101,
- 248, 0x00010100,
- 249, 0x03000000,
- 250, 0x03030303,
- 251, 0x00030303,
- 252, 0x02020064,
- 253, 0x02020202,
- 254, 0x00010202,
- 255, 0x01010064,
- 256, 0x01010101,
- 257, 0x00020101,
- 258, 0x00000064,
- 259, 0x00000000,
- 260, 0x000d0d00,
- 261, 0x00000000,
- 262, 0x00001440,
- 263, 0x02000200,
- 264, 0x02000200,
- 265, 0x00001440,
- 266, 0x00006540,
- 267, 0x00000505,
- 268, 0x00001440,
- 269, 0x02000200,
- 270, 0x02000200,
- 271, 0x00001440,
- 272, 0x00006540,
- 273, 0x02020505,
- 274, 0x000a0100,
- 275, 0x0000000a,
- 276, 0x00000000,
- 277, 0x00000000,
- 278, 0x00000f0a,
- 279, 0x00000000,
- 280, 0x00000000,
- 281, 0x00000000,
- 282, 0x00000000,
- 283, 0x00000000,
- 284, 0x00000103,
- 285, 0x00010003,
- 286, 0x00000003,
- 287, 0x00000000,
- 288, 0x00000000,
- 289, 0x00000000,
- 290, 0x04010000,
- 291, 0x00040404,
- 292, 0x00000000,
- 293, 0x00000000,
- 294, 0x00000000,
- 295, 0x00000000,
- 296, 0x00000000,
- 297, 0x00000000,
- 298, 0x00000000,
- 299, 0x00000000,
- 300, 0x00000000,
- 301, 0x00000000,
- 302, 0x00000000,
- 303, 0x00000000,
- 304, 0x00000000,
- 305, 0x00000000,
- 0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
-const unsigned int ddr3_init_tab_800[] = {
- 14, 0x01000000,
- 36, 0x0a140a0a,
- 37, 0x0100000a,
- 38, 0x0c0c0101,
- 39, 0x00060603,
- 40, 0x00010100,
- 42, 0x00000000,
- 61, 0x00000400,
- 78, 0x00000000,
- 79, 0x00000000,
- 80, 0x00000000,
- 81, 0x00000000,
- 83, 0x00000000,
- 84, 0x00000420,
- 87, 0x00000420,
- 88, 0x00000046,
- 112, 0x00000000,
- 116, 0x00000000,
- 117, 0x00000000,
- 119, 0x00000000,
- 120, 0x00000000,
- 121, 0x00000000,
- 122, 0x00000000,
- 123, 0x00000000,
- 130, 0x00000000,
- 139, 0x00000000,
- 148, 0x00000000,
- 149, 0x00000000,
- 150, 0x00000000,
- 152, 0x00000000,
- 153, 0x00000000,
- 156, 0x00000000,
- 157, 0x01000200,
- 158, 0x02000040,
- 160, 0x00000200,
- 161, 0x00000040,
- 162, 0x00000000,
- 163, 0x01000000,
- 165, 0x0101ffff,
- 166, 0x01010101,
- 168, 0x00000103,
- 170, 0x00000001,
- 171, 0x00000000,
- 175, 0x00000000,
- 176, 0x00000000,
- 180, 0x00000000,
- 181, 0x00000000,
- 182, 0x00000000,
- 185, 0x00000000,
- 187, 0x00000000,
- 194, 0x00000000,
- 205, 0x00000000,
- 0, 0x00000600,
- 1, 0x00000000,
- 2, 0x00000000,
- 3, 0x00000000,
- 4, 0x00000000,
- 5, 0x00000000,
- 6, 0x00000000,
- 7, 0x00000400,
- 8, 0x00000000,
- 9, 0x00000000,
- 10, 0x00000000,
- 11, 0x00000004,
- 12, 0x00000000,
- 13, 0x00000000,
- 15, 0x00013880,
- 16, 0x00030d40,
- 17, 0x00000000,
- 18, 0x02000000,
- 19, 0x00050c00,
- 20, 0x00000000,
- 21, 0x00050c00,
- 22, 0x00000000,
- 23, 0x05040400,
- 24, 0x0e140004,
- 25, 0x0c060404,
- 26, 0x14000405,
- 27, 0x0604040e,
- 28, 0x0404040c,
- 29, 0x006db00c,
- 30, 0x040c0303,
- 31, 0x000c0404,
- 32, 0x03006db0,
- 33, 0x06000c03,
- 34, 0x00060606,
- 35, 0x010c003c,
- 41, 0x00000000,
- 43, 0x00680100,
- 44, 0x00000c28,
- 45, 0x00000068,
- 46, 0x00000c28,
- 47, 0x00000005,
- 48, 0x00030003,
- 49, 0x000a000a,
- 50, 0x00000000,
- 51, 0x00000000,
- 52, 0x02000000,
- 53, 0x0200006c,
- 54, 0x0000006c,
- 55, 0x05000001,
- 56, 0x00050505,
- 57, 0x00000000,
- 58, 0x00000000,
- 59, 0x00010000,
- 60, 0x10040010,
- 62, 0x00000200,
- 63, 0x00000000,
- 64, 0x00000001,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 82, 0x00000000,
- 85, 0x00000046,
- 86, 0x00000000,
- 89, 0x00000000,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000420,
- 99, 0x00000046,
- 100, 0x00000000,
- 101, 0x00000420,
- 102, 0x00000046,
- 103, 0x00000000,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x00000000,
- 109, 0x00000000,
- 110, 0x00000000,
- 111, 0x00000000,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 118, 0x00000000,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x00000000,
- 129, 0x00000000,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00000000,
- 134, 0x00000000,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x00000000,
- 138, 0x00000000,
- 140, 0x01000000,
- 141, 0x00000001,
- 142, 0x00000000,
- 143, 0x00000000,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x00000000, // disable ECC
- 147, 0x00000000,
- 151, 0x00000000,
- 154, 0x00000000,
- 155, 0x00000000,
- 159, 0x00400100,
- 164, 0x0a020001,
- 167, 0x01010101,
- 169, 0x00000c03,
- 172, 0x01000000,
- 173, 0x00000100,
- 174, 0x00000000,
- 177, 0x00000000,
- 178, 0x00000000,
- 179, 0x00000000,
- 183, 0x00000000,
- 184, 0x00000000,
- 186, 0x00000000,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 195, 0x00000000,
- 196, 0x01010200,
- 197, 0x00000002,
- 198, 0x06040400,
- 199, 0x00000106,
- 200, 0x01010000,
- 201, 0x02020002,
- 202, 0x02020101,
- 203, 0x02000102,
- 204, 0x00000000,
- 206, 0x00000000,
- 207, 0x00000000,
- 208, 0x00000000,
- 209, 0x0000280d,
- 210, 0x00010000,
- 211, 0x00010000,
- 212, 0x00000003,
- 213, 0x00000000,
- 214, 0x00000000,
- 215, 0x00000000,
- 216, 0x00000000,
- 217, 0x00000000,
- 218, 0x00000000,
- 219, 0x00000000,
- 220, 0x00000000,
- 221, 0x01000000,
- 222, 0x00000001,
- 223, 0x00000100,
- 224, 0x00030300,
- 225, 0x0556AA00,
- 226, 0x000aa955,
- 227, 0x000aa955,
- 228, 0x000556aa,
- 229, 0x000556aa,
- 230, 0x000aa955,
- 231, 0x000aa955,
- 232, 0x030556aa,
- 233, 0x01000001,
- 234, 0x00010300,
- 235, 0x00676700,
- 236, 0x00676700,
- 237, 0x00676700,
- 238, 0x00676700,
- 239, 0x00676700,
- 240, 0x00676700,
- 241, 0x00676700,
- 242, 0x00676700,
- 243, 0x00676700,
- 244, 0x00000000,
- 245, 0x01000000,
- 246, 0x00000001,
- 247, 0x00000101,
- 248, 0x00010100,
- 249, 0x03000000,
- 250, 0x03030303,
- 251, 0x00030303,
- 252, 0x02020064,
- 253, 0x02020202,
- 254, 0x00010202,
- 255, 0x01010064,
- 256, 0x01010101,
- 257, 0x00020101,
- 258, 0x00000064,
- 259, 0x00000000,
- 260, 0x000d0d00,
- 261, 0x00000000,
- 262, 0x00001850,
- 263, 0x02000200,
- 264, 0x02000200,
- 265, 0x00001850,
- 266, 0x00007990,
- 267, 0x00000505,
- 268, 0x00001850,
- 269, 0x02000200,
- 270, 0x02000200,
- 271, 0x00001850,
- 272, 0x00007990,
- 273, 0x02020505,
- 274, 0x000a0100,
- 275, 0x0000000a,
- 276, 0x00000000,
- 277, 0x00000000,
- 278, 0x00000f0a,
- 279, 0x00000000,
- 280, 0x00000000,
- 281, 0x00000000,
- 282, 0x00000000,
- 283, 0x00000000,
- 284, 0x00000103,
- 285, 0x00010003,
- 286, 0x00000003,
- 287, 0x00000000,
- 288, 0x00000000,
- 289, 0x00000000,
- 290, 0x05000000,
- 291, 0x00040504,
- 292, 0x00000000,
- 293, 0x00000000,
- 294, 0x00000000,
- 295, 0x00000000,
- 296, 0x00000000,
- 297, 0x00000000,
- 298, 0x00000000,
- 299, 0x00000000,
- 300, 0x00000000,
- 301, 0x00000000,
- 302, 0x00000000,
- 303, 0x00000000,
- 304, 0x00000000,
- 305, 0x00000000,
- 0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
-const unsigned int ddr3_init_tab_1066[] = {
- 14, 0x01000000,
- 36, 0x0a140a0a,
- 37, 0x0100000a,
- 38, 0x10100101,
- 39, 0x00080803,
- 40, 0x00010100,
- 42, 0x00000000,
- 61, 0x00000400,
- 78, 0x00000000,
- 79, 0x00000000,
- 80, 0x00000000,
- 81, 0x00000000,
- 83, 0x00000000,
- 84, 0x00000840,
- 87, 0x00000840,
- 88, 0x00000046,
- 112, 0x00000000,
- 116, 0x00000000,
- 117, 0x00000000,
- 119, 0x00000000,
- 120, 0x00000000,
- 121, 0x00000000,
- 122, 0x00000000,
- 123, 0x00000000,
- 130, 0x00000000,
- 139, 0x00000000,
- 148, 0x00000000,
- 149, 0x00000000,
- 150, 0x00000000,
- 152, 0x00000000,
- 153, 0x00000000,
- 156, 0x00000000,
- 157, 0x01000200,
- 158, 0x02000040,
- 160, 0x00000200,
- 161, 0x00000040,
- 162, 0x00000000,
- 163, 0x01000000,
- 165, 0x0101ffff,
- 166, 0x01010101,
- 168, 0x00000103,
- 170, 0x00000001,
- 171, 0x00000000,
- 175, 0x00000000,
- 176, 0x00000000,
- 180, 0x00000000,
- 181, 0x00000000,
- 182, 0x00000000,
- 185, 0x00000000,
- 187, 0x00000000,
- 194, 0x00000000,
- 205, 0x00000000,
- 0, 0x00000600,
- 1, 0x00000000,
- 2, 0x00000000,
- 3, 0x00000000,
- 4, 0x00000000,
- 5, 0x00000000,
- 6, 0x00000000,
- 7, 0x00000600,
- 8, 0x00000000,
- 9, 0x00000000,
- 10, 0x00000000,
- 11, 0x00000006,
- 12, 0x00000000,
- 13, 0x00000000,
- 15, 0x00019f8f,
- 16, 0x00040ee6,
- 17, 0x00000000,
- 18, 0x02000000,
- 19, 0x00061000,
- 20, 0x00000000,
- 21, 0x00061000,
- 22, 0x00000000,
- 23, 0x05040400,
- 24, 0x131a0004,
- 25, 0x10080404,
- 26, 0x1a000405,
- 27, 0x08040413,
- 28, 0x04040410,
- 29, 0x0091dc0c,
- 30, 0x040c0303,
- 31, 0x000c0404,
- 32, 0x030091dc,
- 33, 0x08000c03,
- 34, 0x00080808,
- 35, 0x010c0050,
- 41, 0x00000000,
- 43, 0x008b0100,
- 44, 0x0000102c,
- 45, 0x0000008b,
- 46, 0x0000102c,
- 47, 0x00000005,
- 48, 0x00040004,
- 49, 0x000d000d,
- 50, 0x00000000,
- 51, 0x00000000,
- 52, 0x02000000,
- 53, 0x02000090,
- 54, 0x00000090,
- 55, 0x06000001,
- 56, 0x00060606,
- 57, 0x00000000,
- 58, 0x00000000,
- 59, 0x00010000,
- 60, 0x10040010,
- 62, 0x00000200,
- 63, 0x00000000,
- 64, 0x00000001,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 82, 0x00000000,
- 85, 0x00000046,
- 86, 0x00000008,
- 89, 0x00000008,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000840,
- 99, 0x00000046,
- 100, 0x00000008,
- 101, 0x00000840,
- 102, 0x00000046,
- 103, 0x00000008,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x00000000,
- 109, 0x00000000,
- 110, 0x00000000,
- 111, 0x00000000,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 118, 0x00000000,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x00000000,
- 129, 0x00000000,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00000000,
- 134, 0x00000000,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x00000000,
- 138, 0x00000000,
- 140, 0x01000000,
- 141, 0x00000001,
- 142, 0x00000000,
- 143, 0x00000000,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x00000000, // disable ECC
- 147, 0x00000000,
- 151, 0x00000000,
- 154, 0x00000000,
- 155, 0x00000000,
- 159, 0x00400100,
- 164, 0x0a020001,
- 167, 0x01010101,
- 169, 0x00000c03,
- 172, 0x01000000,
- 173, 0x00000100,
- 174, 0x00000000,
- 177, 0x00000000,
- 178, 0x00000000,
- 179, 0x00000000,
- 183, 0x00000000,
- 184, 0x00000000,
- 186, 0x00000000,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 195, 0x00000000,
- 196, 0x01010200,
- 197, 0x00000002,
- 198, 0x06050500,
- 199, 0x00000106,
- 200, 0x02020000,
- 201, 0x02020002,
- 202, 0x02020101,
- 203, 0x02000102,
- 204, 0x00000000,
- 206, 0x00000000,
- 207, 0x00000000,
- 208, 0x00000000,
- 209, 0x0000280d,
- 210, 0x00010000,
- 211, 0x00010000,
- 212, 0x00000003,
- 213, 0x00000000,
- 214, 0x00000000,
- 215, 0x00000000,
- 216, 0x00000000,
- 217, 0x00000000,
- 218, 0x00000000,
- 219, 0x00000000,
- 220, 0x00000000,
- 221, 0x01000000,
- 222, 0x00000001,
- 223, 0x00000100,
- 224, 0x00030300,
- 225, 0x0556AA00,
- 226, 0x000aa955,
- 227, 0x000aa955,
- 228, 0x000556aa,
- 229, 0x000556aa,
- 230, 0x000aa955,
- 231, 0x000aa955,
- 232, 0x030556aa,
- 233, 0x01000001,
- 234, 0x00010300,
- 235, 0x00676700,
- 236, 0x00676700,
- 237, 0x00676700,
- 238, 0x00676700,
- 239, 0x00676700,
- 240, 0x00676700,
- 241, 0x00676700,
- 242, 0x00676700,
- 243, 0x00676700,
- 244, 0x00000000,
- 245, 0x01000000,
- 246, 0x00000001,
- 247, 0x00000101,
- 248, 0x00010100,
- 249, 0x03000000,
- 250, 0x03030303,
- 251, 0x00030303,
- 252, 0x02020064,
- 253, 0x02020202,
- 254, 0x00010202,
- 255, 0x01010064,
- 256, 0x01010101,
- 257, 0x00020101,
- 258, 0x00000064,
- 259, 0x00000000,
- 260, 0x000d0d00,
- 261, 0x00000000,
- 262, 0x00002058,
- 263, 0x02000200,
- 264, 0x02000200,
- 265, 0x00002058,
- 266, 0x0000a1b8,
- 267, 0x00000607,
- 268, 0x00002058,
- 269, 0x02000200,
- 270, 0x02000200,
- 271, 0x00002058,
- 272, 0x0000a1b8,
- 273, 0x02020607,
- 274, 0x000a0100,
- 275, 0x0000000a,
- 276, 0x00000000,
- 277, 0x00000000,
- 278, 0x00000f0a,
- 279, 0x00000000,
- 280, 0x00000000,
- 281, 0x00000000,
- 282, 0x00000000,
- 283, 0x00000000,
- 284, 0x00000103,
- 285, 0x00010003,
- 286, 0x00000003,
- 287, 0x00000000,
- 288, 0x00000000,
- 289, 0x00000000,
- 290, 0x07000000,
- 291, 0x00050705,
- 292, 0x00000000,
- 293, 0x00000000,
- 294, 0x00000000,
- 295, 0x00000000,
- 296, 0x00000000,
- 297, 0x00000000,
- 298, 0x00000000,
- 299, 0x00000000,
- 300, 0x00000000,
- 301, 0x00000000,
- 302, 0x00000000,
- 303, 0x00000000,
- 304, 0x00000000,
- 305, 0x00000000,
- 0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
-const unsigned int ddr3_init_tab_1333[] = {
- 14, 0x01000000,
- 36, 0x0a140a0a,
- 37, 0x0100000a,
- 38, 0x14140101,
- 39, 0x000a0a03,
- 40, 0x00010100,
- 42, 0x00000000,
- 61, 0x00000400,
- 78, 0x00000000,
- 79, 0x00000000,
- 80, 0x00000000,
- 81, 0x00000000,
- 83, 0x00000000,
- 84, 0x00000a50,
- 87, 0x00000a50,
- 88, 0x00000046,
- 112, 0x00000000,
- 116, 0x00000000,
- 117, 0x00000000,
- 119, 0x00000000,
- 120, 0x00000000,
- 121, 0x00000000,
- 122, 0x00000000,
- 123, 0x00000000,
- 130, 0x00000000,
- 139, 0x00000000,
- 148, 0x00000000,
- 149, 0x00000000,
- 150, 0x00000000,
- 152, 0x00000000,
- 153, 0x00000000,
- 156, 0x00000000,
- 157, 0x01000200,
- 158, 0x02000040,
- 160, 0x00000200,
- 161, 0x00000040,
- 162, 0x00000000,
- 163, 0x01000000,
- 165, 0x0101ffff,
- 166, 0x01010101,
- 168, 0x00000103,
- 170, 0x00000001,
- 171, 0x00000000,
- 175, 0x00000000,
- 176, 0x00000000,
- 180, 0x00000000,
- 181, 0x00000000,
- 182, 0x00000000,
- 185, 0x00000000,
- 187, 0x00000000,
- 194, 0x00000000,
- 205, 0x00000000,
- 0, 0x00000600,
- 1, 0x00000000,
- 2, 0x00000000,
- 3, 0x00000000,
- 4, 0x00000000,
- 5, 0x00000000,
- 6, 0x00000000,
- 7, 0x00000700,
- 8, 0x00000000,
- 9, 0x00000000,
- 10, 0x00000000,
- 11, 0x00000007,
- 12, 0x00000000,
- 13, 0x00000000,
- 15, 0x000208d6,
- 16, 0x00051616,
- 17, 0x00000000,
- 18, 0x02000000,
- 19, 0x00071200,
- 20, 0x00000000,
- 21, 0x00071200,
- 22, 0x00000000,
- 23, 0x05040400,
- 24, 0x18210004,
- 25, 0x140a0505,
- 26, 0x21000405,
- 27, 0x0a050518,
- 28, 0x04050514,
- 29, 0x00b6d00c,
- 30, 0x050c0404,
- 31, 0x000c0405,
- 32, 0x0400b6d0,
- 33, 0x0a000c04,
- 34, 0x000a0a0a,
- 35, 0x010c0064,
- 41, 0x00000000,
- 43, 0x00ae0100,
- 44, 0x00001448,
- 45, 0x000000ae,
- 46, 0x00001448,
- 47, 0x00000005,
- 48, 0x00040004,
- 49, 0x00100010,
- 50, 0x00000000,
- 51, 0x00000000,
- 52, 0x02000000,
- 53, 0x020000b4,
- 54, 0x000000b4,
- 55, 0x07000001,
- 56, 0x00070707,
- 57, 0x00000000,
- 58, 0x00000000,
- 59, 0x00010000,
- 60, 0x10040010,
- 62, 0x00000200,
- 63, 0x00000000,
- 64, 0x00000001,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 82, 0x00000000,
- 85, 0x00000046,
- 86, 0x00000010,
- 89, 0x00000010,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000a50,
- 99, 0x00000046,
- 100, 0x00000010,
- 101, 0x00000a50,
- 102, 0x00000046,
- 103, 0x00000010,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x00000000,
- 109, 0x00000000,
- 110, 0x00000000,
- 111, 0x00000000,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 118, 0x00000000,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x00000000,
- 129, 0x00000000,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00000000,
- 134, 0x00000000,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x00000000,
- 138, 0x00000000,
- 140, 0x01000000,
- 141, 0x00000001,
- 142, 0x00000000,
- 143, 0x00000000,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x00000000, //disable ECC
- 147, 0x00000000,
- 151, 0x00000000,
- 154, 0x00000000,
- 155, 0x00000000,
- 159, 0x00400100,
- 164, 0x0a020001,
- 167, 0x01010101,
- 169, 0x00000c03,
- 172, 0x01000000,
- 173, 0x00000100,
- 174, 0x00000000,
- 177, 0x00000000,
- 178, 0x00000000,
- 179, 0x00000000,
- 183, 0x00000000,
- 184, 0x00000000,
- 186, 0x00000000,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 195, 0x00000000,
- 196, 0x01010200,
- 197, 0x00000002,
- 198, 0x06060600,
- 199, 0x00000106,
- 200, 0x02020000,
- 201, 0x02020002,
- 202, 0x02020101,
- 203, 0x02000102,
- 204, 0x00000000,
- 206, 0x00000000,
- 207, 0x00000000,
- 208, 0x00000000,
- 209, 0x0000280d,
- 210, 0x00010000,
- 211, 0x00010000,
- 212, 0x00000003,
- 213, 0x00000000,
- 214, 0x00000000,
- 215, 0x00000000,
- 216, 0x00000000,
- 217, 0x00000000,
- 218, 0x00000000,
- 219, 0x00000000,
- 220, 0x00000000,
- 221, 0x01000000,
- 222, 0x00000001,
- 223, 0x00000100,
- 224, 0x00030300,
- 225, 0x0556AA00,
- 226, 0x000aa955,
- 227, 0x000aa955,
- 228, 0x000556aa,
- 229, 0x000556aa,
- 230, 0x000aa955,
- 231, 0x000aa955,
- 232, 0x030556aa,
- 233, 0x01000001,
- 234, 0x00010300,
- 235, 0x00676700,
- 236, 0x00676700,
- 237, 0x00676700,
- 238, 0x00676700,
- 239, 0x00676700,
- 240, 0x00676700,
- 241, 0x00676700,
- 242, 0x00676700,
- 243, 0x00676700,
- 244, 0x00000000,
- 245, 0x01000000,
- 246, 0x00000001,
- 247, 0x00000101,
- 248, 0x00010100,
- 249, 0x03000000,
- 250, 0x03030303,
- 251, 0x00030303,
- 252, 0x02020064,
- 253, 0x02020202,
- 254, 0x00010202,
- 255, 0x01010064,
- 256, 0x01010101,
- 257, 0x00020101,
- 258, 0x00000064,
- 259, 0x00000000,
- 260, 0x000e0e00,
- 261, 0x00000000,
- 262, 0x00002890,
- 263, 0x02000200,
- 264, 0x02000200,
- 265, 0x00002890,
- 266, 0x0000cad0,
- 267, 0x00000708,
- 268, 0x00002890,
- 269, 0x02000200,
- 270, 0x02000200,
- 271, 0x00002890,
- 272, 0x0000cad0,
- 273, 0x02020708,
- 274, 0x000a0100,
- 275, 0x0000000a,
- 276, 0x00000000,
- 277, 0x00000000,
- 278, 0x00000f0a,
- 279, 0x00000000,
- 280, 0x00000000,
- 281, 0x00000000,
- 282, 0x00000000,
- 283, 0x00000000,
- 284, 0x00000103,
- 285, 0x00010003,
- 286, 0x00000003,
- 287, 0x00000000,
- 288, 0x00000000,
- 289, 0x00000000,
- 290, 0x08000000,
- 291, 0x00060806,
- 292, 0x00000000,
- 293, 0x00000000,
- 294, 0x00000000,
- 295, 0x00000000,
- 296, 0x00000000,
- 297, 0x00000000,
- 298, 0x00000000,
- 299, 0x00000000,
- 300, 0x00000000,
- 301, 0x00000000,
- 302, 0x00000000,
- 303, 0x00000000,
- 304, 0x00000000,
- 305, 0x00000000,
- 0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-const unsigned int ddr3_init_tab_1600[] = {
- 14, 0x01000000,
- 36, 0x0a140a0a,
- 37, 0x0100000a,
- 38, 0x17170101,
- 39, 0x000b0b03,
- 40, 0x00010100,
- 42, 0x00000000,
- 61, 0x00000400,
- 78, 0x00000000,
- 79, 0x00000000,
- 80, 0x00000000,
- 81, 0x00000000,
- 83, 0x00000000,
- 84, 0x00000c70,
- 87, 0x00000c70,
- 88, 0x00000046,
- 112, 0x00000000,
- 116, 0x00000000,
- 117, 0x00000000,
- 119, 0x00000000,
- 120, 0x00000000,
- 121, 0x00000000,
- 122, 0x00000000,
- 123, 0x00000000,
- 130, 0x00000000,
- 139, 0x00000000,
- 148, 0x00000000,
- 149, 0x00000000,
- 150, 0x00000000,
- 152, 0x00000000,
- 153, 0x00000000,
- 156, 0x00000000,
- 157, 0x01000200,
- 158, 0x02000040,
- 160, 0x00000200,
- 161, 0x00000040,
- 162, 0x00000000,
- 163, 0x01000000,
- 165, 0x0101ffff,
- 166, 0x01010101,
- 168, 0x00000103,
- 170, 0x00000001,
- 171, 0x00000000,
- 175, 0x00000000,
- 176, 0x00000000,
- 180, 0x00000000,
- 181, 0x00000000,
- 182, 0x00000000,
- 185, 0x00000000,
- 187, 0x00000000,
- 194, 0x00000000,
- 205, 0x00000000,
- 0, 0x00000600,
- 1, 0x00000000,
- 2, 0x00000000,
- 3, 0x00000000,
- 4, 0x00000000,
- 5, 0x00000000,
- 6, 0x00000000,
- 7, 0x00000800,
- 8, 0x00000000,
- 9, 0x00000000,
- 10, 0x00000000,
- 11, 0x00000008,
- 12, 0x00000000,
- 13, 0x00000000,
- 15, 0x00027100,
- 16, 0x00061a80,
- 17, 0x00000000,
- 18, 0x02000000,
- 19, 0x00081600,
- 20, 0x00000000,
- 21, 0x00081600,
- 22, 0x00000000,
- 23, 0x05040400,
- 24, 0x1c270005,
- 25, 0x180b0606,
- 26, 0x27000505,
- 27, 0x0b06061c,
- 28, 0x04060618,
- 29, 0x00db600c,
- 30, 0x060c0404,
- 31, 0x000c0406,
- 32, 0x0400db60,
- 33, 0x0b000c04,
- 34, 0x000c0b0c,
- 35, 0x010c0078,
- 41, 0x00000000,
- 43, 0x00d00100,
- 44, 0x00001858,
- 45, 0x000000d0,
- 46, 0x00001858,
- 47, 0x00000005,
- 48, 0x00050005,
- 49, 0x00140014,
- 50, 0x00000000,
- 51, 0x00000000,
- 52, 0x02000000,
- 53, 0x020000d8,
- 54, 0x000000d8,
- 55, 0x08000001,
- 56, 0x00080808,
- 57, 0x00000000,
- 58, 0x00000000,
- 59, 0x00010000,
- 60, 0x10040010,
- 62, 0x00000200,
- 63, 0x00000000,
- 64, 0x00000001,
- 65, 0x00000000,
- 66, 0x00000000,
- 67, 0x00000000,
- 68, 0x00000000,
- 69, 0x00000000,
- 70, 0x00000000,
- 71, 0x00000000,
- 72, 0x00000000,
- 73, 0x00000000,
- 74, 0x00000000,
- 75, 0x00000000,
- 76, 0x00000000,
- 77, 0x00000000,
- 82, 0x00000000,
- 85, 0x00000046,
- 86, 0x00000018,
- 89, 0x00000018,
- 90, 0x00000000,
- 91, 0x00000000,
- 92, 0x00000000,
- 93, 0x00000000,
- 94, 0x00000000,
- 95, 0x00000000,
- 96, 0x00000000,
- 97, 0x00000000,
- 98, 0x00000c70,
- 99, 0x00000046,
- 100, 0x00000018,
- 101, 0x00000c70,
- 102, 0x00000046,
- 103, 0x00000018,
- 104, 0x00000000,
- 105, 0x00000000,
- 106, 0x00000000,
- 107, 0x00000000,
- 108, 0x00000000,
- 109, 0x00000000,
- 110, 0x00000000,
- 111, 0x00000000,
- 113, 0x00000000,
- 114, 0x00000000,
- 115, 0x00000000,
- 118, 0x00000000,
- 124, 0x00000000,
- 125, 0x00000000,
- 126, 0x00000000,
- 127, 0x00000000,
- 128, 0x00000000,
- 129, 0x00000000,
- 131, 0x00000000,
- 132, 0x00000000,
- 133, 0x00000000,
- 134, 0x00000000,
- 135, 0x00000000,
- 136, 0x00000000,
- 137, 0x00000000,
- 138, 0x00000000,
- 140, 0x01000000,
- 141, 0x00000001,
- 142, 0x00000000,
- 143, 0x00000000,
- 144, 0x00000000,
- 145, 0x00000000,
- 146, 0x00000000, //disable ECC
- 147, 0x00000000,
- 151, 0x00000000,
- 154, 0x00000000,
- 155, 0x00000000,
- 159, 0x00400100,
- 164, 0x0a020001,
- 167, 0x01010101,
- 169, 0x00000c03,
- 172, 0x01000000,
- 173, 0x00000100,
- 174, 0x00000000,
- 177, 0x00000000,
- 178, 0x00000000,
- 179, 0x00000000,
- 183, 0x00000000,
- 184, 0x00000000,
- 186, 0x00000000,
- 188, 0x00000000,
- 189, 0x00000000,
- 190, 0x00000000,
- 191, 0x00000000,
- 192, 0x00000000,
- 193, 0x00000000,
- 195, 0x00000000,
- 196, 0x01010200,
- 197, 0x00000002,
- 198, 0x06070700,
- 199, 0x00000106,
- 200, 0x03030000,
- 201, 0x02020002,
- 202, 0x02020101,
- 203, 0x02000102,
- 204, 0x00000000,
- 206, 0x00000000,
- 207, 0x00000000,
- 208, 0x00000000,
- 209, 0x0000280d,
- 210, 0x00010000,
- 211, 0x00010000,
- 212, 0x00000003,
- 213, 0x00000000,
- 214, 0x00000000,
- 215, 0x00000000,
- 216, 0x00000000,
- 217, 0x00000000,
- 218, 0x00000000,
- 219, 0x00000000,
- 220, 0x00000000,
- 221, 0x01000000,
- 222, 0x00000001,
- 223, 0x00000100,
- 224, 0x00030300,
- 225, 0x0556AA00,
- 226, 0x000aa955,
- 227, 0x000aa955,
- 228, 0x000556aa,
- 229, 0x000556aa,
- 230, 0x000aa955,
- 231, 0x000aa955,
- 232, 0x030556aa,
- 233, 0x01000001,
- 234, 0x00010300,
- 235, 0x00676700,
- 236, 0x00676700,
- 237, 0x00676700,
- 238, 0x00676700,
- 239, 0x00676700,
- 240, 0x00676700,
- 241, 0x00676700,
- 242, 0x00676700,
- 243, 0x00676700,
- 244, 0x00000000,
- 245, 0x01000000,
- 246, 0x00000001,
- 247, 0x00000101,
- 248, 0x00010100,
- 249, 0x03000000,
- 250, 0x03030303,
- 251, 0x00030303,
- 252, 0x02020064,
- 253, 0x02020202,
- 254, 0x00010202,
- 255, 0x01010064,
- 256, 0x01010101,
- 257, 0x00020101,
- 258, 0x00000064,
- 259, 0x00000000,
- 260, 0x000e0e00,
- 261, 0x00000000,
- 262, 0x000030b0,
- 263, 0x02000200,
- 264, 0x02000200,
- 265, 0x000030b0,
- 266, 0x0000f370,
- 267, 0x0000080a,
- 268, 0x000030b0,
- 269, 0x02000200,
- 270, 0x02000200,
- 271, 0x000030b0,
- 272, 0x0000f370,
- 273, 0x0202080a,
- 274, 0x000a0100,
- 275, 0x0000000a,
- 276, 0x00000000,
- 277, 0x00000000,
- 278, 0x00000f0a,
- 279, 0x00000000,
- 280, 0x00000000,
- 281, 0x00000000,
- 282, 0x00000000,
- 283, 0x00000000,
- 284, 0x00000103,
- 285, 0x00010003,
- 286, 0x00000003,
- 287, 0x00000000,
- 288, 0x00000000,
- 289, 0x00000000,
- 290, 0x0a000000,
- 291, 0x00070a07,
- 292, 0x00000000,
- 293, 0x00000000,
- 294, 0x00000000,
- 295, 0x00000000,
- 296, 0x00000000,
- 297, 0x00000000,
- 298, 0x00000000,
- 299, 0x00000000,
- 300, 0x00000000,
- 301, 0x00000000,
- 302, 0x00000000,
- 303, 0x00000000,
- 304, 0x00000000,
- 305, 0x00000000,
- 0xffffffff
-};
-#endif
-
-#ifdef DDR2_SUPPORT
-const unsigned int ddr2_mode_reg_tab[] = {
- 0x0320,
- 0x0046,
- 0x0000,
- 0x0000
-};
-#endif
diff --git a/src/soc/broadcom/cygnus/gpio.c b/src/soc/broadcom/cygnus/gpio.c
deleted file mode 100644
index 9c4ef24..0000000
--- a/src/soc/broadcom/cygnus/gpio.c
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-#include <delay.h>
-
-#define dev_dbg(chip, fmt, args...) printk(BIOS_DEBUG, "[%s] " fmt, \
- chip->label, args)
-
-#define CYGNUS_GPIO_DATA_IN_OFFSET 0x00
-#define CYGNUS_GPIO_DATA_OUT_OFFSET 0x04
-#define CYGNUS_GPIO_OUT_EN_OFFSET 0x08
-#define CYGNUS_GPIO_IN_TYPE_OFFSET 0x0c
-#define CYGNUS_GPIO_INT_DE_OFFSET 0x10
-#define CYGNUS_GPIO_INT_EDGE_OFFSET 0x14
-#define CYGNUS_GPIO_INT_MSK_OFFSET 0x18
-#define CYGNUS_GPIO_INT_STAT_OFFSET 0x1c
-#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
-#define CYGNUS_GPIO_INT_CLR_OFFSET 0x24
-#define CYGNUS_GPIO_PAD_RES_OFFSET 0x34
-#define CYGNUS_GPIO_RES_EN_OFFSET 0x38
-
-/* drive strength control for ASIU GPIO */
-#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
-
-/* drive strength control for CCM/CRMU (AON) GPIO */
-#define CYGNUS_GPIO_DRV0_CTRL_OFFSET 0x00
-
-#define GPIO_BANK_SIZE 0x200
-#define NGPIOS_PER_BANK 32
-#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
-
-#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
-#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
-
-#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
-#define GPIO_DRV_STRENGTH_BITS 3
-#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
-
-/*
- * Cygnus GPIO core
- *
- * @base: I/O register base for Cygnus GPIO controller
- * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
- * has the PINCONF support implemented outside of the GPIO block
- * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
- * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
- * that can be individually muxed to GPIO
- * @pctl_priv: pointer to pinctrl handle
- */
-struct cygnus_gpio {
- void *base;
- void *io_ctrl;
- const char *label;
- int gpio_base;
- u16 ngpio;
- unsigned num_banks;
- int pinmux_is_supported;
- void *pctl_priv;
-};
-
-/*
- * GPIO cores table
- *
- * Cygnus has 3 gpio cores. The tables contains descriptors of those cores.
- */
-struct cygnus_gpio cygnus_gpio_table[] = {
- {
- .base = (void *)0x03024800,
- .io_ctrl = (void *)0x03024008,
- .label = "gpio_crmu",
- .gpio_base = 170,
- .ngpio = 6,
- },
- {
- .base = (void *)0x1800a000,
- .io_ctrl = (void *)0x0301d164,
- .label = "gpio_ccm",
- .gpio_base = 0,
- .ngpio = 24,
- },
- {
- .base = (void *)0x180a5000,
- .label = "gpio_asiu",
- .gpio_base = 24,
- .ngpio = 146,
- .pinmux_is_supported = 1
- }
-};
-
-/*
- * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
- * pinctrl pin space
- */
-struct cygnus_gpio_pin_range {
- unsigned offset;
- unsigned pin_base;
- unsigned num_pins;
-};
-
-#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
-
-/*
- * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins.
- * This is for ASIU gpio. The offset is based on ASIU gpios.
- */
-static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
- CYGNUS_PINRANGE(0, 42, 1),
- CYGNUS_PINRANGE(1, 44, 3),
- CYGNUS_PINRANGE(4, 48, 1),
- CYGNUS_PINRANGE(5, 50, 3),
- CYGNUS_PINRANGE(8, 126, 1),
- CYGNUS_PINRANGE(9, 155, 1),
- CYGNUS_PINRANGE(10, 152, 1),
- CYGNUS_PINRANGE(11, 154, 1),
- CYGNUS_PINRANGE(12, 153, 1),
- CYGNUS_PINRANGE(13, 127, 3),
- CYGNUS_PINRANGE(16, 140, 1),
- CYGNUS_PINRANGE(17, 145, 7),
- CYGNUS_PINRANGE(24, 130, 10),
- CYGNUS_PINRANGE(34, 141, 4),
- CYGNUS_PINRANGE(38, 54, 1),
- CYGNUS_PINRANGE(39, 56, 3),
- CYGNUS_PINRANGE(42, 60, 3),
- CYGNUS_PINRANGE(45, 64, 3),
- CYGNUS_PINRANGE(48, 68, 2),
- CYGNUS_PINRANGE(50, 84, 6),
- CYGNUS_PINRANGE(56, 94, 6),
- CYGNUS_PINRANGE(62, 72, 1),
- CYGNUS_PINRANGE(63, 70, 1),
- CYGNUS_PINRANGE(64, 80, 1),
- CYGNUS_PINRANGE(65, 74, 3),
- CYGNUS_PINRANGE(68, 78, 1),
- CYGNUS_PINRANGE(69, 82, 1),
- CYGNUS_PINRANGE(70, 156, 17),
- CYGNUS_PINRANGE(87, 104, 12),
- CYGNUS_PINRANGE(99, 102, 2),
- CYGNUS_PINRANGE(101, 90, 4),
- CYGNUS_PINRANGE(105, 116, 10),
- CYGNUS_PINRANGE(123, 11, 1),
- CYGNUS_PINRANGE(124, 38, 4),
- CYGNUS_PINRANGE(128, 43, 1),
- CYGNUS_PINRANGE(129, 47, 1),
- CYGNUS_PINRANGE(130, 49, 1),
- CYGNUS_PINRANGE(131, 53, 1),
- CYGNUS_PINRANGE(132, 55, 1),
- CYGNUS_PINRANGE(133, 59, 1),
- CYGNUS_PINRANGE(134, 63, 1),
- CYGNUS_PINRANGE(135, 67, 1),
- CYGNUS_PINRANGE(136, 71, 1),
- CYGNUS_PINRANGE(137, 73, 1),
- CYGNUS_PINRANGE(138, 77, 1),
- CYGNUS_PINRANGE(139, 79, 1),
- CYGNUS_PINRANGE(140, 81, 1),
- CYGNUS_PINRANGE(141, 83, 1),
- CYGNUS_PINRANGE(142, 10, 1)
-};
-
-static unsigned cygnus_gpio_to_pin(unsigned gpio)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
- const struct cygnus_gpio_pin_range *range = cygnus_gpio_pintable
- + i;
-
- if ((gpio < range->offset) ||
- (gpio >= (range->offset + range->num_pins)))
- continue;
-
- return range->pin_base + (gpio - range->offset);
- }
- return -1;
-}
-
-static struct cygnus_gpio *cygnus_get_gpio_core(unsigned gpio,
- unsigned *gpio_offset)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
- struct cygnus_gpio *chip = cygnus_gpio_table + i;
-
- if ((gpio < chip->gpio_base) ||
- (gpio >= (chip->gpio_base + chip->ngpio)))
- continue;
-
- *gpio_offset = gpio - chip->gpio_base;
- return chip;
- }
-
- return NULL;
-}
-
-static u32 cygnus_readl(struct cygnus_gpio *chip, unsigned int offset)
-{
- return read32(chip->base + offset);
-}
-
-static void cygnus_writel(struct cygnus_gpio *chip, unsigned int offset,
- u32 val)
-{
- write32(chip->base + offset, val);
-}
-
-/**
- * cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
- * Cygnus GPIO register
- *
- * @cygnus_gpio: Cygnus GPIO device
- * @reg: register offset
- * @gpio: GPIO pin
- * @set: set or clear. 1 - set; 0 -clear
- */
-static void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
- unsigned gpio, int set)
-{
- unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
- unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
- u32 val;
-
- val = cygnus_readl(chip, offset);
- if (set)
- val |= BIT(shift);
- else
- val &= ~BIT(shift);
- cygnus_writel(chip, offset, val);
-}
-
-static int cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
- unsigned gpio)
-{
- unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
- unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
- u32 val;
-
- val = cygnus_readl(chip, offset) & BIT(shift);
- if (val)
- return 1;
- else
- return 0;
-}
-
-/*
- * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
- */
-static int cygnus_gpio_request(struct cygnus_gpio *chip, unsigned offset)
-{
- /* not all Cygnus GPIO pins can be muxed individually */
- if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
- return 0;
-
- return cygnus_gpio_request_enable(chip->pctl_priv,
- cygnus_gpio_to_pin(offset));
-}
-
-static void cygnus_gpio_free(struct cygnus_gpio *chip, unsigned offset)
-{
- if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
- return;
-
- cygnus_gpio_disable_free(chip->pctl_priv, cygnus_gpio_to_pin(offset));
-}
-
-static int cygnus_gpio_direction_input(struct cygnus_gpio *chip, unsigned gpio)
-{
- cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 0);
-
- dev_dbg(chip, "gpio:%u set input\n", gpio);
-
- return 0;
-}
-
-static int cygnus_gpio_direction_output(struct cygnus_gpio *chip, unsigned gpio,
- int value)
-{
- cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 1);
- cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
-
- dev_dbg(chip, "gpio:%u set output, value:%d\n", gpio, value);
-
- return 0;
-}
-
-static void cygnus_gpio_set(struct cygnus_gpio *chip, unsigned gpio, int value)
-{
- cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
-
- dev_dbg(chip, "gpio:%u set, value:%d\n", gpio, value);
-}
-
-static int cygnus_gpio_get(struct cygnus_gpio *chip, unsigned gpio)
-{
- return cygnus_get_bit(chip, CYGNUS_GPIO_DATA_IN_OFFSET, gpio);
-}
-
-static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
- int disable, int pull_up)
-{
- if (disable) {
- cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 0);
- } else {
- cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, pull_up);
- cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 1);
- }
-
- dev_dbg(chip, "gpio:%u set pullup:%d\n", gpio, pull_up);
-
- return 0;
-}
-
-#define CYGNUS_GPIO_TEST_AON_GPIO0 170
-#define CYGNUS_GPIO_TEST_SPI2_MISO 69
-#define CYGNUS_GPIO_TEST_DELAY_S 3
-
-static void cygnus_gpio_test(void)
-{
- gpio_t gpio_in;
- gpio_t gpio_out;
- unsigned val;
-
- printk(BIOS_INFO, "Start gpio test...\n");
-
- gpio_in = CYGNUS_GPIO_TEST_AON_GPIO0; /* AON_GPIO0 */
- gpio_input(gpio_in);
- gpio_input_pulldown(gpio_in);
- printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
-
- gpio_in = CYGNUS_GPIO_TEST_SPI2_MISO; /* SPI2_MISO */
- gpio_input(gpio_in);
- gpio_input_pullup(gpio_in);
- printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
- val = 0;
- gpio_out = CYGNUS_GPIO_TEST_SPI2_MISO;
-
- gpio_output(gpio_out, val);
- printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
- delay(CYGNUS_GPIO_TEST_DELAY_S);
-
- val = 1;
- gpio_set(gpio_out, val);
- printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
- delay(CYGNUS_GPIO_TEST_DELAY_S);
-
- val = 0;
- gpio_set(gpio_out, val);
- printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
- delay(CYGNUS_GPIO_TEST_DELAY_S);
-
- val = 1;
- gpio_set(gpio_out, val);
- printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
- delay(CYGNUS_GPIO_TEST_DELAY_S);
-
- val = 0;
- gpio_set(gpio_out, val);
- printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
- delay(CYGNUS_GPIO_TEST_DELAY_S);
-
- gpio_free(CYGNUS_GPIO_TEST_AON_GPIO0);
- gpio_free(CYGNUS_GPIO_TEST_SPI2_MISO);
- printk(BIOS_INFO, "Gpio test completed...\n");
-}
-
-void gpio_init(void)
-{
- int i;
-
- printk(BIOS_INFO, "Setting up the gpio...\n");
-
- for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
- struct cygnus_gpio *chip = cygnus_gpio_table + i;
-
- chip->num_banks = (chip->ngpio+NGPIOS_PER_BANK - 1)
- / NGPIOS_PER_BANK;
- if (chip->pinmux_is_supported)
- chip->pctl_priv = cygnus_pinmux_init();
- }
-
- if (IS_ENABLED(CONFIG_CYGNUS_GPIO_TEST))
- cygnus_gpio_test();
-}
-
-void gpio_free(gpio_t gpio)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- cygnus_gpio_free(chip, gpio_num);
-}
-
-void gpio_input(gpio_t gpio)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- if (cygnus_gpio_request(chip, gpio_num) != 0) {
- printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
- return;
- }
- cygnus_gpio_direction_input(chip, gpio_num);
-}
-
-void gpio_input_pulldown(gpio_t gpio)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- cygnus_gpio_set_pull(chip, gpio_num, 0, 0);
-}
-
-void gpio_input_pullup(gpio_t gpio)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- cygnus_gpio_set_pull(chip, gpio_num, 0, 1);
-}
-
-int gpio_get(gpio_t gpio)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return -1;
- }
-
- return cygnus_gpio_get(chip, gpio_num);
-}
-
-void gpio_set(gpio_t gpio, int value)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- cygnus_gpio_set(chip, gpio_num, value);
-}
-
-void gpio_output(gpio_t gpio, int value)
-{
- struct cygnus_gpio *chip;
- unsigned gpio_num;
-
- chip = cygnus_get_gpio_core(gpio, &gpio_num);
- if (chip == NULL) {
- dev_dbg(chip, "unable to find chip for gpio %d", gpio);
- return;
- }
-
- if (cygnus_gpio_request(chip, gpio_num) != 0) {
- printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
- return;
- }
- cygnus_gpio_direction_output(chip, gpio_num, value);
-}
diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c
deleted file mode 100644
index ce5592f..0000000
--- a/src/soc/broadcom/cygnus/hw_init.c
+++ /dev/null
@@ -1,759 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <delay.h>
-#include <console/console.h>
-#include <soc/tz.h>
-#include <soc/hw_init.h>
-
-/*****************************************************************************
- * TrustZone
- *****************************************************************************/
-#define IHOST_SCU_SECURE_ACCESS 0x19020054
-
-#define SMAU_NIC_IDM_TZ_BASE 0x180150a0
-#define SMAU_DDR_TZ_BASE 0x18015200
-#define SMAU_FLASH0_TZ_BASE 0x18015300
-#define SMAU_FLASH1_TZ_BASE 0x18015308
-#define SMAU_FLASH2_TZ_BASE 0x18015310
-#define SMAU_FLASH3_TZ_BASE 0x18015318
-#define SMAU_TZ_BASE_ENABLE 0x00000001
-
-#define CRMU_IPROC_ADDR_RANGE0_LOW 0x03024c30
-#define CRMU_IPROC_ADDR_RANGE0_HIGH 0x03024c34
-#define CRMU_ADDR_MASK 0xffffff00
-#define CRMU_ADDR_VALID 0x00000001
-#define CRMU_ADDR_START 0x03010000
-#define CRMU_ADDR_END 0x03100000
-
-static void scu_ns_config(void)
-{
- /*
- * Enable NS SCU access to ARM global timer, private timer, and
- * components
- */
- write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF);
-}
-
-static void smau_ns_config(void)
-{
- unsigned int val;
-
- /* Disable SMAU NIC IDM TZ */
- val = read32((void *)SMAU_NIC_IDM_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_NIC_IDM_TZ_BASE, val);
-
- /*
- * Disable DDR TZ base
- *
- * This means the entire DDR is marked as NONSECURE (NS)
- *
- * NOTE: In the future, multiple regions of DDR may need to be marked
- * as SECURE for secure OS and other TZ usages
- */
- val = read32((void *)SMAU_DDR_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_DDR_TZ_BASE, val);
-
-
- /*
- * Disable flash TZ support
- *
- * The entire flash is currently marked as NS
- *
- * NOTE: In the future, multiple regions of flash may need to be marked
- * as SECURE for secure OS and other TZ firmware/data storage
- */
-
- /* Flash 0: ROM */
- val = read32((void *)SMAU_FLASH0_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_FLASH0_TZ_BASE, val);
-
- /* Flash 1: QSPI */
- val = read32((void *)SMAU_FLASH1_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_FLASH1_TZ_BASE, val);
-
- /* Flash 2: NAND */
- val = read32((void *)SMAU_FLASH2_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_FLASH2_TZ_BASE, val);
-
- /* Flash 3: PNOR */
- val = read32((void *)SMAU_FLASH3_TZ_BASE);
- val &= ~SMAU_TZ_BASE_ENABLE;
- write32((void *)SMAU_FLASH3_TZ_BASE, val);
-}
-
-static void crmu_ns_config(void)
-{
-
- /*
- * Currently opens up the entire CRMU to allow iPROC NS access
- *
- * NOTE: In the future, we might want to protect particular CRMU
- * sub-blocks to allow SECURE access only. That can be done by
- * programming the CRMU IPROC address range registers. Up to 4 access
- * windows can be created
- */
- write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,
- (CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
- write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH,
- (CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
-}
-
-static void tz_init(void)
-{
- /* Configure the Cygnus for non-secure access */
- /* ARM Cortex A9 SCU NS access configuration */
- scu_ns_config();
-
- /* SMAU NS related configurations */
- smau_ns_config();
-
- /* CRMU NS related configurations */
- crmu_ns_config();
-
- /*
- * Configure multiple masters and slaves to run in NS
- */
- tz_set_non_virtual_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
- tz_set_periph_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
- tz_set_masters_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
- tz_set_wrapper_security(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- TZ_STATE_NON_SECURE);
- tz_set_cfg_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-
- tz_set_ext_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-
- /* configure sec peripherals to be accessed from non-secure world */
- tz_set_sec_periphs_security(0xFFFFFFFF &
- ~(CYGNUS_sec_periph_APBz_sotp |
- CYGNUS_sec_periph_APBz_tzpc),
- TZ_STATE_NON_SECURE);
-
- /* default sram to non-secure */
- tz_set_sram_sec_region(0);
-}
-
-/*****************************************************************************
- * DMAC
- *****************************************************************************/
-#define DMAC_M0_IDM_RESET_CONTROL 0x1810f800
-#define DMAC_RESET_MASK 0x00000001
-#define DMAC_RESET_TIMEOUT 1000
-
-static void dmac_init(void)
-{
- unsigned int val, timeout;
-
- /* bring the DMAC block out of reset */
- val = read32((void *)DMAC_M0_IDM_RESET_CONTROL);
- val |= DMAC_RESET_MASK;
- write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
- udelay(10);
- val &= ~DMAC_RESET_MASK;
- write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
-
- timeout = 0;
- while (read32((void *)DMAC_M0_IDM_RESET_CONTROL) & DMAC_RESET_MASK) {
- udelay(1);
- if (timeout++ > DMAC_RESET_TIMEOUT)
- die("Failed to bring PL330 DMAC out of reset\n");
- }
-}
-
-/*****************************************************************************
- * Neon
- *****************************************************************************/
-#define CRU_CONTROL 0x1800e000
-#define CRU_CONTROL_NEON_RESET_N 0x00000040
-
-#define CRU_IHOST_PWRDWN_EN 0x1800e004
-#define CRU_IHOST_PWRDWN_EN_CLAMPON_NEON 0x00100000
-#define CRU_IHOST_PWRDWN_EN_PWRON_NEON 0x00200000
-#define CRU_IHOST_PWRDWN_EN_PWROK_NEON 0x00400000
-
-#define CRU_IHOST_PWRDWN_STATUS 0x1800e008
-#define CRU_IHOST_PWRDWN_STATUS_PWRON_NEON 0x00200000
-#define CRU_IHOST_PWRDWN_STATUS_PWROK_NEON 0x00400000
-
-#define CRU_STATUS_DELAY_US 1
-#define CRU_MAX_RETRY_COUNT 10
-#define CRU_RETRY_INTVL_US 1
-
-static void neon_init(void)
-{
- unsigned int i, val;
-
- /* put Neon into reset */
- val = read32((void *)CRU_CONTROL);
- val &= ~CRU_CONTROL_NEON_RESET_N;
- write32((void *)CRU_CONTROL, val);
-
- /* assert the power on register bit */
- val = read32((void *)CRU_IHOST_PWRDWN_EN);
- val |= CRU_IHOST_PWRDWN_EN_PWRON_NEON;
- write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
- /* wait for power on */
- i = 0;
- while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
- CRU_IHOST_PWRDWN_STATUS_PWRON_NEON)) {
- udelay(CRU_RETRY_INTVL_US);
- if (i++ >= CRU_MAX_RETRY_COUNT)
- die("Failed to ack NEON power on\n");
- }
-
- udelay(CRU_STATUS_DELAY_US);
-
- /* assert the power ok register bit */
- val = read32((void *)CRU_IHOST_PWRDWN_EN);
- val |= CRU_IHOST_PWRDWN_EN_PWROK_NEON;
- write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
- /* wait for power ok */
- i = 0;
- while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
- CRU_IHOST_PWRDWN_STATUS_PWROK_NEON)) {
- udelay(CRU_RETRY_INTVL_US);
- if (i++ >= CRU_MAX_RETRY_COUNT)
- die("Failed to ack NEON power ok\n");
- }
-
- udelay(CRU_STATUS_DELAY_US);
-
- /* clamp off for the NEON block */
- val = read32((void *)CRU_IHOST_PWRDWN_EN);
- val &= ~CRU_IHOST_PWRDWN_EN_CLAMPON_NEON;
- write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
- udelay(CRU_STATUS_DELAY_US);
-
- /* bring NEON out of reset */
- val = read32((void *)CRU_CONTROL);
- val |= CRU_CONTROL_NEON_RESET_N;
- write32((void *)CRU_CONTROL, val);
-}
-
-/*****************************************************************************
- * PCIe
- *****************************************************************************/
-#define CRMU_PCIE_CFG 0x0301d0a0
-#define PCIE0_LNK_PHY_IDDQ 0x00000004
-#define PCIE1_LNK_PHY_IDDQ 0x00000400
-
-static void pcie_init(void)
-{
- unsigned int val;
-
- /*
- * Force all AFEs of both PCIe0 and PCIe1 to be powered down, including
- * pad biasing
- *
- * This brings down the PCIe interfaces to the lowest possible power
- * mode
- */
- val = read32((void *)CRMU_PCIE_CFG);
- val |= PCIE1_LNK_PHY_IDDQ | PCIE0_LNK_PHY_IDDQ;
- write32((void *)CRMU_PCIE_CFG, val);
-}
-
-/*****************************************************************************
- * M0
- *****************************************************************************/
-#define CRMU_MCU_ACCESS_CONTROL 0x03024c00
-#define CRMU_MCU_ACCESS_MODE_SECURE 0x2
-
-static void M0_init(void)
-{
- /* Set M0 as a secure master */
- write32((void *)CRMU_MCU_ACCESS_CONTROL, CRMU_MCU_ACCESS_MODE_SECURE);
-}
-
-/*****************************************************************************
- * CCU
- *****************************************************************************/
-#define IHOST_PROC_CLK_WR_ACCESS 0x19000000
-#define IHOST_PROC_CLK_POLICY_FREQ 0x19000008
-#define IHOST_PROC_CLK_POLICY_CTL 0x1900000c
-#define IHOST_PROC_CLK_POLICY0_MASK 0x19000010
-#define IHOST_PROC_CLK_POLICY1_MASK 0x19000014
-#define IHOST_PROC_CLK_POLICY2_MASK 0x19000018
-#define IHOST_PROC_CLK_POLICY3_MASK 0x1900001c
-#define IHOST_PROC_CLK_INTEN 0x19000020
-#define IHOST_PROC_CLK_INTSTAT 0x19000024
-#define IHOST_PROC_CLK_LVM_EN 0x19000034
-#define IHOST_PROC_CLK_LVM0_3 0x19000038
-#define IHOST_PROC_CLK_LVM4_7 0x1900003c
-#define IHOST_PROC_CLK_VLT0_3 0x19000040
-#define IHOST_PROC_CLK_VLT4_7 0x19000044
-#define IHOST_PROC_CLK_BUS_QUIESC 0x19000100
-#define IHOST_PROC_CLK_CORE0_CLKGATE 0x19000200
-#define IHOST_PROC_CLK_CORE1_CLKGATE 0x19000204
-#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE 0x19000210
-#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE 0x19000300
-#define IHOST_PROC_CLK_APB0_CLKGATE 0x19000400
-#define IHOST_PROC_CLK_PL310_DIV 0x19000a00
-#define IHOST_PROC_CLK_PL310_TRIGGER 0x19000a04
-#define IHOST_PROC_CLK_ARM_SWITCH_DIV 0x19000a08
-#define IHOST_PROC_CLK_ARM_SWITCH_TRIGGER 0x19000a0c
-#define IHOST_PROC_CLK_APB_DIV 0x19000a10
-#define IHOST_PROC_CLK_APB_DIV_TRIGGER 0x19000a14
-#define IHOST_PROC_CLK_PLLARMA 0x19000c00
-#define IHOST_PROC_CLK_PLLARMB 0x19000c04
-#define IHOST_PROC_CLK_PLLARMC 0x19000c08
-#define IHOST_PROC_CLK_PLLARMCTRL0 0x19000c0c
-#define IHOST_PROC_CLK_PLLARMCTRL1 0x19000c10
-#define IHOST_PROC_CLK_PLLARMCTRL2 0x19000c14
-#define IHOST_PROC_CLK_PLLARMCTRL3 0x19000c18
-#define IHOST_PROC_CLK_PLLARMCTRL4 0x19000c1c
-#define IHOST_PROC_CLK_PLLARMCTRL5 0x19000c20
-#define IHOST_PROC_CLK_PLLARM_OFFSET 0x19000c24
-#define IHOST_PROC_CLK_ARM_DIV 0x19000e00
-#define IHOST_PROC_CLK_ARM_SEG_TRG 0x19000e04
-#define IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE 0x19000e08
-#define IHOST_PROC_CLK_PLL_DEBUG 0x19000e10
-#define IHOST_PROC_CLK_ACTIVITY_MON1 0x19000e20
-#define IHOST_PROC_CLK_ACTIVITY_MON2 0x19000e24
-#define IHOST_PROC_CLK_CLKGATE_DBG 0x19000e40
-#define IHOST_PROC_CLK_APB_CLKGATE_DBG1 0x19000e48
-#define IHOST_PROC_CLK_CLKMON 0x19000e64
-#define IHOST_PROC_CLK_POLICY_DBG 0x19000ec0
-#define IHOST_PROC_CLK_TGTMASK_DBG1 0x19000ec4
-#define IHOST_PROC_RST_WR_ACCESS 0x19000f00
-#define IHOST_PROC_RST_SOFT_RSTN 0x19000f04
-#define IHOST_PROC_RST_A9_CORE_SOFT_RSTN 0x19000f08
-
-#define WR_ACCESS_PRIVATE_ACCESS_MODE 0x80000000
-
-static uint32_t ccu_reg[] = {
- IHOST_PROC_CLK_WR_ACCESS,
- IHOST_PROC_CLK_POLICY_FREQ,
- IHOST_PROC_CLK_POLICY_CTL,
- IHOST_PROC_CLK_POLICY0_MASK,
- IHOST_PROC_CLK_POLICY1_MASK,
- IHOST_PROC_CLK_POLICY2_MASK,
- IHOST_PROC_CLK_POLICY3_MASK,
- IHOST_PROC_CLK_INTEN,
- IHOST_PROC_CLK_INTSTAT,
- IHOST_PROC_CLK_LVM_EN,
- IHOST_PROC_CLK_LVM0_3,
- IHOST_PROC_CLK_LVM4_7,
- IHOST_PROC_CLK_VLT0_3,
- IHOST_PROC_CLK_VLT4_7,
- IHOST_PROC_CLK_BUS_QUIESC,
- IHOST_PROC_CLK_CORE0_CLKGATE,
- IHOST_PROC_CLK_CORE1_CLKGATE,
- IHOST_PROC_CLK_ARM_SWITCH_CLKGATE,
- IHOST_PROC_CLK_ARM_PERIPH_CLKGATE,
- IHOST_PROC_CLK_APB0_CLKGATE,
- IHOST_PROC_CLK_PL310_DIV,
- IHOST_PROC_CLK_PL310_TRIGGER,
- IHOST_PROC_CLK_ARM_SWITCH_DIV,
- IHOST_PROC_CLK_ARM_SWITCH_TRIGGER,
- IHOST_PROC_CLK_APB_DIV,
- IHOST_PROC_CLK_APB_DIV_TRIGGER,
- IHOST_PROC_CLK_PLLARMA,
- IHOST_PROC_CLK_PLLARMB,
- IHOST_PROC_CLK_PLLARMC,
- IHOST_PROC_CLK_PLLARMCTRL0,
- IHOST_PROC_CLK_PLLARMCTRL1,
- IHOST_PROC_CLK_PLLARMCTRL2,
- IHOST_PROC_CLK_PLLARMCTRL3,
- IHOST_PROC_CLK_PLLARMCTRL4,
- IHOST_PROC_CLK_PLLARMCTRL5,
- IHOST_PROC_CLK_PLLARM_OFFSET,
- IHOST_PROC_CLK_ARM_DIV,
- IHOST_PROC_CLK_ARM_SEG_TRG,
- IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE,
- IHOST_PROC_CLK_PLL_DEBUG,
- IHOST_PROC_CLK_ACTIVITY_MON1,
- IHOST_PROC_CLK_ACTIVITY_MON2,
- IHOST_PROC_CLK_CLKGATE_DBG,
- IHOST_PROC_CLK_APB_CLKGATE_DBG1,
- IHOST_PROC_CLK_CLKMON,
- IHOST_PROC_CLK_POLICY_DBG,
- IHOST_PROC_CLK_TGTMASK_DBG1,
- IHOST_PROC_RST_WR_ACCESS,
- IHOST_PROC_RST_SOFT_RSTN,
- IHOST_PROC_RST_A9_CORE_SOFT_RSTN
-};
-
-#define CCU_REG_TABLE_SIZE (sizeof(ccu_reg)/sizeof(ccu_reg[0]))
-
-/* Set priv_access_mode field to unrestricted (0) */
-static void ccu_init(void)
-{
- uint32_t val;
- uint32_t i;
- for (i = 0; i < CCU_REG_TABLE_SIZE; i++) {
- val = read32((void *)(ccu_reg[i]));
- val &= ~WR_ACCESS_PRIVATE_ACCESS_MODE;
- write32((void *)(ccu_reg[i]), val);
- }
-}
-
-/*****************************************************************************
- * LCD
- *****************************************************************************/
-#define ASIU_TOP_CLK_GATING_CTRL 0x180aa024
-#define ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN 0x00000010
-#define ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN 0x00000008
-#define ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN 0x00000001
-#define ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN 0x00000002
-
-static void lcd_init(void)
-{
- unsigned int val;
-
- /* make sure the LCD clock is ungated */
- val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
- val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN;
- write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-}
-
-/*******************************************************************
- * Default priority settings in Cygnus
- *
- * Master Name Default Priority
- * ==================== =================
- * ihost_m0 12
- * mhost0_m0 12
- * mhost1_m0 ` 12
- * pcie0_m0 9
- * pcie0_m1 9
- * cmicd_m0 7
- * amac_m0 7
- * amac_m1 7
- * ext_m0 (LCD) 5
- * ext_m1 (V3D) 5
- * sdio_m0 3
- * sdio_m1 3
- * usb2h_m0 3
- * usb2d_m0 3
- * dmu_m0 3
- * a9jtag_m0 0
- *
- *****************************************************************************/
-
-#define AXIIC_EXT_M0_READ_QOS 0x1a057100
-#define AXIIC_EXT_M0_READ_MASK 0x0000000f
-#define AXIIC_EXT_M0_WRITE_QOS 0x1a057104
-#define AXIIC_EXT_M0_WRITE_MASK 0x0000000f
-
-static void lcd_qos_init(unsigned int qos)
-{
- unsigned int val;
-
- val = read32((void *)AXIIC_EXT_M0_READ_QOS);
- val &= ~AXIIC_EXT_M0_READ_MASK;
- val |= (qos & AXIIC_EXT_M0_READ_MASK);
- write32((void *)AXIIC_EXT_M0_READ_QOS, val);
-
- val = read32((void *)AXIIC_EXT_M0_WRITE_QOS);
- val &= ~AXIIC_EXT_M0_WRITE_MASK;
- val |= (qos & AXIIC_EXT_M0_WRITE_MASK);
- write32((void *)AXIIC_EXT_M0_WRITE_QOS, val);
-}
-
-/*****************************************************************************
- * V3D
- *****************************************************************************/
-static void v3d_init(void)
-{
- unsigned int val;
-
- /* make sure the V3D clock is ungated */
- val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
- val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN |
- ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN;
- write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-}
-
-/*****************************************************************************
- * Audio
- *****************************************************************************/
-#define CRMU_PLL_AON_CTRL 0x0301c020
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL 0x00000800
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG 0x00000400
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO 0x00000200
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN 0x00000100
-
-static void audio_init(void)
-{
- unsigned int val;
-
- /* Ungate (enable) audio clock. */
- val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
- val |= ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN;
- write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-
- /* Power on audio GEN PLL, LDO, and BG. Input isolation = normal. */
- val = read32((void *)CRMU_PLL_AON_CTRL);
- val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG;
- val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO;
- val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL;
- val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN;
- write32((void *)CRMU_PLL_AON_CTRL, val);
-}
-
-/*****************************************************************************
- * SDIO
- *****************************************************************************/
-#define CRMU_SDIO_1P8_FAIL_CONTROL 0x0301c0a0
-#define UHS1_18V_VREG_FAIL 0x00000001
-
-#define SDIO_IDM0_IO_CONTROL_DIRECT 0x18116408
-#define SDIO_IDM1_IO_CONTROL_DIRECT 0x18117408
-#define SDIO_CMD_COMFLICT_DISABLE 0x00400000
-#define SDIO_FEEDBACK_CLK_EN 0x00200000
-#define SDIO_CLK_ENABLE 0x00000001
-
-#define CDRU_SDIO0_IO_CONTROL 0x0301d144
-#define CDRU_SDIO1_IO_CONTROL 0x0301d140
-#define INPUT_DISABLE 0x00000080
-#define SLEW_RATE_ENABLE 0x00000040
-#define PULL_UP_ENABLE 0x00000020
-#define PULL_DOWN_ENABLE 0x00000010
-#define HYSTERESIS_ENABLE 0x00000008
-#define SDIO_DEFAULT_DRIVE_STRENGTH 0x4 /* 8 mA */
-
-#define SDIO_IDM0_IDM_RESET_CONTROL 0x18116800
-#define SDIO_IDM1_IDM_RESET_CONTROL 0x18117800
-#define SDIO_RESET_MASK 0x00000001
-#define SDIO_RESET_TIMEOUT 1000
-
-#define CRMU_SDIO_CONTROL0 0x0301d088
-#define CRMU_SDIO_CONTROL1 0x0301d08c
-#define CRMU_SDIO_CONTROL2 0x0301d090
-#define CRMU_SDIO_CONTROL3 0x0301d094
-#define CRMU_SDIO_CONTROL4 0x0301d098
-#define CRMU_SDIO_CONTROL5 0x0301d09c
-
-/*
- * SDIO_CAPS_L
- *
- * Field Bit(s)
- * ===========================
- * DDR50 31
- * SDR104 30
- * SDR50 29
- * SLOTTYPE 28:27
- * ASYNCHIRQ 26
- * SYSBUS64 25
- * V18 24
- * V3 23
- * V33 22
- * SUPRSM 21
- * SDMA 20
- * HSPEED 19
- * ADMA2 18
- * EXTBUSMED 17
- * MAXBLK 16:15
- * BCLK 14:7
- * TOUT 6
- * TOUTFREQ 5:0
- */
-#define SDIO_CAPS_L 0xA17C0000
-
-/*
- * SDIO_CAPS_H
- *
- * Field Bit(s)
- * ===========================
- * reserved 31:20
- * SPIBLOCKMODE 19
- * SPIMODE_CAP 18
- * CLOCKMULT 17:10
- * RETUNE_MODE 9:8
- * USETUNE_SDR50 7
- * TMRCNT_RETUNE 6:3
- * DRVR_TYPED 2
- * DRVR_TYPEC 1
- * DRVR_TYPEA 0
- */
-#define SDIO_CAPS_H 0x000C0087
-
-/*
- * Preset value
- *
- * Field Bit(s)
- * ===========================
- * Driver Strength 12:11
- * Clock Generator 10
- * SDCLK Frequeency 9:0
- */
-
-/*
- * SDIO_PRESETVAL1
- *
- * Field Bit(s) Description
- * ============================================================
- * DDR50_PRESET 25:13 Preset Value for DDR50
- * DEFAULT_PRESET 12:0 Preset Value for Default Speed
- */
-#define SDIO_PRESETVAL1 0x01004004
-
-/*
- * SDIO_PRESETVAL2
- *
- * Field Bit(s) Description
- * ============================================================
- * HIGH_SPEED_PRESET 25:13 Preset Value for High Speed
- * INIT_PRESET 12:0 Preset Value for Initialization
- */
-#define SDIO_PRESETVAL2 0x01004100
-
-/*
- * SDIO_PRESETVAL3
- *
- * Field Bit(s) Description
- * ============================================================
- * SDR104_PRESET 25:13 Preset Value for SDR104
- * SDR12_PRESET 12:0 Preset Value for SDR12
- */
-#define SDIO_PRESETVAL3 0x00000004
-
-/*
- * SDIO_PRESETVAL4
- *
- * Field Bit(s) Description
- * ============================================================
- * SDR25_PRESET 25:13 Preset Value for SDR25
- * SDR50_PRESET 12:0 Preset Value for SDR50
- */
-#define SDIO_PRESETVAL4 0x01005001
-
-static void sdio_ctrl_init(unsigned int idx)
-{
- unsigned int sdio_idm_io_control_direct_reg;
- unsigned int cdru_sdio_io_control_reg;
- unsigned int sdio_idm_reset_control_reg;
- unsigned int val, timeout;
-
- switch (idx) {
- case 0:
- sdio_idm_io_control_direct_reg = SDIO_IDM0_IO_CONTROL_DIRECT;
- cdru_sdio_io_control_reg = CDRU_SDIO0_IO_CONTROL;
- sdio_idm_reset_control_reg = SDIO_IDM0_IDM_RESET_CONTROL;
- break;
- case 1:
- sdio_idm_io_control_direct_reg = SDIO_IDM1_IO_CONTROL_DIRECT;
- cdru_sdio_io_control_reg = CDRU_SDIO1_IO_CONTROL;
- sdio_idm_reset_control_reg = SDIO_IDM1_IDM_RESET_CONTROL;
- break;
- default:
- return;
- }
-
- /*
- * Disable the cmd conflict error interrupt and enable feedback clock
- */
- val = read32((void *)sdio_idm_io_control_direct_reg);
- val |= SDIO_CMD_COMFLICT_DISABLE | SDIO_FEEDBACK_CLK_EN |
- SDIO_CLK_ENABLE;
- write32((void *)sdio_idm_io_control_direct_reg, val);
-
- /*
- * Set drive strength, enable hysteresis and slew rate control
- */
- val = SDIO_DEFAULT_DRIVE_STRENGTH |
- HYSTERESIS_ENABLE | SLEW_RATE_ENABLE;
- write32((void *)cdru_sdio_io_control_reg, val);
-
- /* Reset SDIO controller */
- val = read32((void *)sdio_idm_reset_control_reg);
- val |= SDIO_RESET_MASK;
- write32((void *)sdio_idm_reset_control_reg, SDIO_RESET_MASK);
- udelay(10);
- val &= ~SDIO_RESET_MASK;
- write32((void *)sdio_idm_reset_control_reg, val);
-
- timeout = 0;
- while (read32((void *)sdio_idm_reset_control_reg) & SDIO_RESET_MASK) {
- udelay(1);
- if (timeout++ > SDIO_RESET_TIMEOUT)
- die("Failed to bring SDIO out of reset\n");
- }
-}
-
-static void sdio_init(void)
-{
- unsigned int val;
-
- /*
- * Configure SDIO host controller capabilities
- * (common setting for all SDIO controllers)
- */
- write32((void *)CRMU_SDIO_CONTROL0, SDIO_CAPS_H);
- write32((void *)CRMU_SDIO_CONTROL1, SDIO_CAPS_L);
- /*
- * Configure SDIO host controller preset values
- * (common setting for all SDIO controllers)
- */
- write32((void *)CRMU_SDIO_CONTROL2, SDIO_PRESETVAL1);
- write32((void *)CRMU_SDIO_CONTROL3, SDIO_PRESETVAL2);
- write32((void *)CRMU_SDIO_CONTROL4, SDIO_PRESETVAL3);
- write32((void *)CRMU_SDIO_CONTROL5, SDIO_PRESETVAL4);
-
- /*
- * The sdhci driver attempts to change the SDIO IO voltage for UHS-I
- * cards by setting the EN1P8V in control2 register then checks the
- * outcome by reading it back.
- * Cygnus does not have an internal regulator for the SDIO IO voltage
- * but can be configured to indicate success (leave EN1P8V set)
- * or failure (clear EN1P8V).
- *
- * Clear CRMU_SDIO_UHS1_18V_VREG_FAIL in CRMU_SDIO_1P8_FAIL_CONTROL
- * register to indicate success.
- * (common setting for all SDIO controllers)
- */
- val = read32((void *)CRMU_SDIO_1P8_FAIL_CONTROL);
- val &= ~UHS1_18V_VREG_FAIL;
- write32((void *)CRMU_SDIO_1P8_FAIL_CONTROL, val);
-
- /*
- * Initialize each SDIO controller
- */
- sdio_ctrl_init(0);
- sdio_ctrl_init(1);
-}
-
-void hw_init(void)
-{
- tz_init();
- printk(BIOS_INFO, "trustzone initialized\n");
- dmac_init();
- printk(BIOS_INFO, "PL330 DMAC initialized\n");
- lcd_init();
- lcd_qos_init(15);
- printk(BIOS_INFO, "LCD initialized\n");
- v3d_init();
- printk(BIOS_INFO, "V3D initialized\n");
- audio_init();
- printk(BIOS_INFO, "audio initialized\n");
- neon_init();
- printk(BIOS_INFO, "neon initialized\n");
- pcie_init();
- printk(BIOS_INFO, "PCIe initialized\n");
- M0_init();
- printk(BIOS_INFO, "M0 initialized\n");
- ccu_init();
- printk(BIOS_INFO, "CCU initialized\n");
- sdio_init();
- printk(BIOS_INFO, "SDIO initialized\n");
-}
diff --git a/src/soc/broadcom/cygnus/i2c.c b/src/soc/broadcom/cygnus/i2c.c
deleted file mode 100644
index ac431e7..0000000
--- a/src/soc/broadcom/cygnus/i2c.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/i2c_simple.h>
-#include <soc/i2c.h>
-
-struct cygnus_i2c_regs {
- u32 i2c_con;
- u32 i2c_timing_con;
- u32 i2c_addr;
- u32 i2c_fifo_master;
- u32 i2c_fifo_slave;
- u32 i2c_bit_bang;
- u32 reserved0[(0x30 - 0x18) / 4];
- u32 i2c_master_comm;
- u32 i2c_slave_comm;
- u32 i2c_int_en;
- u32 i2c_int_status;
- u32 i2c_master_data_wr;
- u32 i2c_master_data_rd;
- u32 i2c_slave_data_wr;
- u32 i2c_slave_data_rd;
- u32 reserved1[(0xb0 - 0x50) / 4];
- u32 i2c_timing_con2;
-};
-
-static struct cygnus_i2c_regs *i2c_bus[] = {
- (struct cygnus_i2c_regs *)0x18008000,
- (struct cygnus_i2c_regs *)0x1800b000,
-};
-
-#define I2C_TIMEOUT_US 100000 /* 100ms */
-#define I2C_FIFO_MAX_SIZE 64
-
-#define ETIMEDOUT 1
-#define EINVAL 2
-#define EBUSY 3
-
-/* Configuration (0x0) */
-#define I2C_SMB_RESET (1 << 31)
-#define I2C_SMB_EN (1 << 30)
-
-/* Timing configuration (0x4) */
-#define I2C_MODE_400 (1 << 31)
-
-/* Master FIFO control (0xc) */
-#define I2C_MASTER_RX_FIFO_FLUSH (1 << 31)
-#define I2C_MASTER_TX_FIFO_FLUSH (1 << 30)
-
-/* Master command (0x30) */
-#define I2C_MASTER_START_BUSY (1 << 31)
-#define I2C_MASTER_STATUS_SFT 25
-#define I2C_MASTER_STATUS_MASK (0x7 << I2C_MASTER_STATUS_SFT)
-#define I2C_MASTER_PROT_SFT 9
-#define I2C_MASTER_PROT_BLK_WR (0x7 << I2C_MASTER_PROT_SFT)
-#define I2C_MASTER_PROT_BLK_RD (0x8 << I2C_MASTER_PROT_SFT)
-
-/* Master data write (0x40) */
-#define I2C_MASTER_WR_STATUS (1 << 31)
-
-/* Master data read (0x44) */
-#define I2C_MASTER_RD_DATA_MASK 0xff
-
-static unsigned int i2c_bus_busy(struct cygnus_i2c_regs *reg_addr)
-{
- return read32(®_addr->i2c_master_comm) & I2C_MASTER_START_BUSY;
-}
-
-static int i2c_wait_bus_busy(struct cygnus_i2c_regs *reg_addr)
-{
- int timeout = I2C_TIMEOUT_US;
- while (timeout--) {
- if (!i2c_bus_busy(reg_addr))
- break;
- udelay(1);
- }
-
- if (timeout <= 0)
- return ETIMEDOUT;
-
- return 0;
-}
-
-static void i2c_flush_fifo(struct cygnus_i2c_regs *reg_addr)
-{
- write32(®_addr->i2c_fifo_master,
- I2C_MASTER_RX_FIFO_FLUSH | I2C_MASTER_TX_FIFO_FLUSH);
-}
-
-static int i2c_write(struct cygnus_i2c_regs *reg_addr,
- struct i2c_msg *segment)
-{
- uint8_t *data = segment->buf;
- unsigned int val, status;
- int i, ret;
-
- write32(®_addr->i2c_master_data_wr, segment->slave << 1);
-
- for (i = 0; i < segment->len; i++) {
- val = data[i];
-
- /* mark the last byte */
- if (i == segment->len - 1)
- val |= I2C_MASTER_WR_STATUS;
-
- write32(®_addr->i2c_master_data_wr, val);
- }
- if (segment->len == 0)
- write32(®_addr->i2c_master_data_wr, I2C_MASTER_WR_STATUS);
-
- /*
- * Now we can activate the transfer.
- */
- write32(®_addr->i2c_master_comm,
- I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_WR);
-
- ret = i2c_wait_bus_busy(reg_addr);
- if (ret) {
- printk(BIOS_ERR, "I2C bus timeout\n");
- goto flush_fifo;
- }
-
- /* check transaction successful */
- status = read32(®_addr->i2c_master_comm);
- ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
- if (ret) {
- printk(BIOS_ERR, "I2C write error %u\n", status);
- goto flush_fifo;
- }
-
- return 0;
-
-flush_fifo:
- i2c_flush_fifo(reg_addr);
- return ret;
-}
-
-static int i2c_read(struct cygnus_i2c_regs *reg_addr, struct i2c_msg *segment)
-{
- uint8_t *data = segment->buf;
- int i, ret;
- unsigned int status;
-
- write32(®_addr->i2c_master_data_wr, segment->slave << 1 | 1);
-
- /*
- * Now we can activate the transfer. Specify the number of bytes to read
- */
- write32(®_addr->i2c_master_comm,
- I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_RD | segment->len);
-
- ret = i2c_wait_bus_busy(reg_addr);
- if (ret) {
- printk(BIOS_ERR, "I2C bus timeout\n");
- goto flush_fifo;
- }
-
- /* check transaction successful */
- status = read32(®_addr->i2c_master_comm);
- ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
- if (ret) {
- printk(BIOS_ERR, "I2C read error %u\n", status);
- goto flush_fifo;
- }
-
- for (i = 0; i < segment->len; i++)
- data[i] = read32(®_addr->i2c_master_data_rd) &
- I2C_MASTER_RD_DATA_MASK;
-
- return 0;
-
-flush_fifo:
- i2c_flush_fifo(reg_addr);
- return ret;
-}
-
-static int i2c_do_xfer(struct cygnus_i2c_regs *reg_addr,
- struct i2c_msg *segment)
-{
- int ret;
-
- if (segment->len > I2C_FIFO_MAX_SIZE - 1) {
- printk(BIOS_ERR,
- "I2C transfer error: segment size (%d) is larger than limit (%d)\n",
- segment->len, I2C_FIFO_MAX_SIZE);
- return EINVAL;
- }
-
- if (i2c_bus_busy(reg_addr)) {
- printk(BIOS_WARNING, "I2C transfer error: bus is busy\n");
- return EBUSY;
- }
-
- if (segment->flags & I2C_M_RD)
- ret = i2c_read(reg_addr, segment);
- else
- ret = i2c_write(reg_addr, segment);
-
- return ret;
-}
-
-int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
- int seg_count)
-{
- int i;
- int res = 0;
- struct cygnus_i2c_regs *regs = i2c_bus[bus];
- struct i2c_msg *seg = segments;
-
- for (i = 0; i < seg_count; i++, seg++) {
- res = i2c_do_xfer(regs, seg);
- if (res)
- break;
- }
- return res;
-}
-
-void i2c_init(unsigned int bus, unsigned int hz)
-{
- struct cygnus_i2c_regs *regs = i2c_bus[bus];
-
- assert(bus >= 0 && bus <= 1);
-
- setbits_le32(®s->i2c_con, I2C_SMB_RESET);
- udelay(100); /* wait 100 usec per spec */
- clrbits_le32(®s->i2c_con, I2C_SMB_RESET);
-
- switch (hz) {
- case 100000:
- clrbits_le32(®s->i2c_timing_con, I2C_MODE_400);
- break;
- case 400000:
- setbits_le32(®s->i2c_timing_con, I2C_MODE_400);
- break;
- default:
- printk(BIOS_ERR, "I2C bus does not support frequency %d Hz\n",
- hz);
- break;
- }
-
- i2c_flush_fifo(regs);
-
- /* disable all interrupts */
- write32(®s->i2c_int_en, 0);
-
- /* clear all pending interrupts */
- write32(®s->i2c_int_status, 0xffffffff);
-
- write32(®s->i2c_con, I2C_SMB_EN);
-}
diff --git a/src/soc/broadcom/cygnus/include/soc/addressmap.h b/src/soc/broadcom/cygnus/include/soc/addressmap.h
deleted file mode 100644
index 9cc3a52..0000000
--- a/src/soc/broadcom/cygnus/include/soc/addressmap.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
-#define __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
-
-#define IPROC_PERIPH_BASE 0x19020000
-#define IPROC_PERIPH_GLB_TIM_REG_BASE (IPROC_PERIPH_BASE + 0x200)
-
-#define IPROC_QSPI_BASE 0x18047000
-
-#define IPROC_IOMUX_OVERRIDE_BASE 0x0301D24C
-
-#endif /* __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h
deleted file mode 100644
index 0ba09e3..0000000
--- a/src/soc/broadcom/cygnus/include/soc/config.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-
-#ifndef __SOC_BROADCOM_CYGNUS_CONFIG_H__
-#define __SOC_BROADCOM_CYGNUS_CONFIG_H__
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/halapis/ddr_regs.h>
-
-/* DDR shmoo Parameters */
-#define SDI_INTERFACE_BITWIDTH 16
-#define SDI_NUM_COLUMNS 1024
-#define SDI_NUM_BANKS 8
-
-#ifdef DDR3_SIZE_512MB
-#define SDI_NUM_ROWS 32768
-#else
-#define SDI_NUM_ROWS 65536
-#endif
-
-/* Idle count (in units of 1024 cycles) before auto entering self-refresh */
-#define DDR_AUTO_SELF_REFRESH_IDLE_COUNT 16
-
-#endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus.h b/src/soc/broadcom/cygnus/include/soc/cygnus.h
deleted file mode 100644
index dac5d60..0000000
--- a/src/soc/broadcom/cygnus/include/soc/cygnus.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_H__
-#define __SOC_BROADCOM_CYGNUS_H__
-
-void usb_init(void);
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h b/src/soc/broadcom/cygnus/include/soc/cygnus_types.h
deleted file mode 100644
index 7466024..0000000
--- a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
-#define __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
-
-#include <stdint.h>
-#include <types.h>
-
-#ifndef TRUE
-#define TRUE (1 == 1)
-#endif
-
-#ifndef FALSE
-#define FALSE (1 == 0)
-#endif
-
-#ifndef NULL
-#define NULL 0
-#endif
-
-/**********************************************************************
- * Basic types
- **********************************************************************/
-
-typedef uint8_t uint8;
-typedef int8_t int8;
-typedef uint16_t uint16;
-typedef int16_t int16;
-typedef int32_t int32;
-typedef uint32_t uint32;
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h
deleted file mode 100644
index bce5222..0000000
--- a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
-#define __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
-
-#include <soc/config.h>
-
-#define SOC_E_NONE (0)
-#define SOC_E_FAIL (-1)
-#define SOC_E_INTERNAL (-2)
-#define SOC_E_TIMEOUT (-3)
-#define SOC_E_PARAM (-4)
-#define SOC_E_MEMORY (-5)
-#define SOC_E_UNAVAIL (-6)
-#define SOC_E_CONFIG (-7)
-#define SOC_DDR3_CLOCK_MHZ(unit) iproc_get_ddr3_clock_mhz(unit)
-
-#define DDR_SHMOO_PARAM_MEM_PTR (0x1b000000) /*size ~0x300 */
-#define DDR_SHMOO_VREFW_MEM_PTR (0x50000000) /* size ~0x30000 */
-#define SOC_DDR3_NUM_MEMORIES (1)
-
-/* Convenience Macros - Arad Memory Controller - Recheck when MemC files change */
-enum drc_reg_set {
- DRC_BIST_CONFIGr = 0,
- DRC_BIST_CONFIG2r,
- DRC_BIST_GENERAL_CONFIGURATIONSr,
- DRC_BIST_CONFIGURATIONSr,
- DRC_BIST_NUMBER_OF_ACTIONSr,
- DRC_BIST_START_ADDRESSr,
- DRC_BIST_END_ADDRESSr,
- DRC_BIST_SINGLE_BIT_MASKr,
- DRC_BIST_PATTERN_WORD_7r,
- DRC_BIST_PATTERN_WORD_6r,
- DRC_BIST_PATTERN_WORD_5r,
- DRC_BIST_PATTERN_WORD_4r,
- DRC_BIST_PATTERN_WORD_3r,
- DRC_BIST_PATTERN_WORD_2r,
- DRC_BIST_PATTERN_WORD_1r,
- DRC_BIST_PATTERN_WORD_0r,
- DRC_BIST_FULL_MASK_WORD_7r,
- DRC_BIST_FULL_MASK_WORD_6r,
- DRC_BIST_FULL_MASK_WORD_5r,
- DRC_BIST_FULL_MASK_WORD_4r,
- DRC_BIST_FULL_MASK_WORD_3r,
- DRC_BIST_FULL_MASK_WORD_2r,
- DRC_BIST_FULL_MASK_WORD_1r,
- DRC_BIST_FULL_MASK_WORD_0r,
- DRC_BIST_STATUSESr,
- DRC_BIST_FULL_MASK_ERROR_COUNTERr,
- DRC_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr,
- DRC_BIST_ERROR_OCCURREDr,
- DRC_BIST_GLOBAL_ERROR_COUNTERr,
- DRC_BIST_LAST_ADDR_ERRr,
- DRC_BIST_LAST_DATA_ERR_WORD_7r,
- DRC_BIST_LAST_DATA_ERR_WORD_6r,
- DRC_BIST_LAST_DATA_ERR_WORD_5r,
- DRC_BIST_LAST_DATA_ERR_WORD_4r,
- DRC_BIST_LAST_DATA_ERR_WORD_3r,
- DRC_BIST_LAST_DATA_ERR_WORD_2r,
- DRC_BIST_LAST_DATA_ERR_WORD_1r,
- DRC_BIST_LAST_DATA_ERR_WORD_0r
-};
-
-
-
-#define DRCA DDR_BistConfig
-#define DRCB DDR_BistConfig
-#define DRCC DDR_BistConfig
-#define DRCD DDR_BistConfig
-#define DRCE DDR_BistConfig
-#define DRCF DDR_BistConfig
-#define DRCG DDR_BistConfig
-#define DRCH DDR_BistConfig
-#define DRCALL DDR_BistConfig
-
-#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_SHIFT 26
-#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_WIDTH 6
-#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_SHIFT 25
-#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_SHIFT 24
-#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_SHIFT 23
-#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_SHIFT 22
-#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_SHIFT 21
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_SHIFT 20
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_SHIFT 19
-#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_SHIFT 18
-#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_SHIFT 17
-#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_SHIFT 16
-#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_SHIFT 8
-#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_WIDTH 8
-#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_SHIFT 0
-#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_WIDTH 8
-
-#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_SHIFT 0
-#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_WIDTH 32
-
-
-#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_SHIFT 0
-#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_WIDTH 26
-#define DRCA_BIST_START_ADDRESSr_RESERVED_SHIFT 26
-#define DRCA_BIST_START_ADDRESSr_RESERVED_WIDTH 6
-
-#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_SHIFT 0
-#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_WIDTH 26
-#define DRCA_BIST_END_ADDRESSr_RESERVED_SHIFT 26
-#define DRCA_BIST_END_ADDRESSr_RESERVED_WIDTH 6
-
-#define DRCA_BIST_STATUSESr_RESERVED_SHIFT 4
-#define DRCA_BIST_STATUSESr_RESERVED_WIDTH 28
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_SHIFT 3
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_WIDTH 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_SHIFT 2
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_WIDTH 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_SHIFT 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_WIDTH 1
-#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_SHIFT 0
-#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_WIDTH 1
-
-#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_SHIFT 0
-#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_WIDTH 32
-
-
-#define soc_reg_field_set(unit, r, m, f, data) \
- (*(m) = ((*(m) & ~(((1 << r##_##f##_WIDTH) - 1) << r##_##f##_SHIFT)) | ((data & ((1 << r##_##f##_WIDTH) - 1)) << r##_##f##_SHIFT)))
-
-
-#define soc_reg_field_get(unit, r, m, f) \
- ((m >> r##_##f##_SHIFT) & ((1 << r##_##f##_WIDTH) - 1))
-
-
-#define DRC_REG_READ(unit, channel, reg, rvp) \
- soc_reg32_get((volatile uint32*)(channel + 4 * reg), rvp)
-
-#define DRC_REG_WRITE(unit, channel, reg, rv) \
- soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv)
-
-#endif /* __SOC_BROADCOM_CYGNUS_DDR_BIST_H__ */
-
-/* End of File */
diff --git a/src/soc/broadcom/cygnus/include/soc/gpio.h b/src/soc/broadcom/cygnus/include/soc/gpio.h
deleted file mode 100644
index 69f06ce..0000000
--- a/src/soc/broadcom/cygnus/include/soc/gpio.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_GPIO_H__
-#define __SOC_BROADCOM_CYGNUS_GPIO_H__
-
-#include <types.h>
-
-#define ENOTSUPP 524 /* Operation is not supported */
-
-/* Supported GPIO types. Not all of these types are supported on all boards. */
-enum iproc_gpio_types {
- IPROC_GPIO_CCA_ID,
- IPROC_GPIO_CMICM_ID,
- IPROC_GPIO_ASIU_ID
-};
-
-typedef u32 gpio_t;
-
-
-void *cygnus_pinmux_init(void);
-int cygnus_gpio_request_enable(void *priv, unsigned pin);
-void cygnus_gpio_disable_free(void *priv, unsigned pin);
-void gpio_init(void);
-void gpio_free(gpio_t gpio);
-
-#endif /* __SOC_BROADCOM_CYGNUS_GPIO_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
deleted file mode 100644
index 32668d1..0000000
--- a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
+++ /dev/null
@@ -1,1074 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-#ifndef __SOC_BROADCOM_CYGNUS_DDR_REGS_H__
-#define __SOC_BROADCOM_CYGNUS_DDR_REGS_H__
-
-#define CRMU_DDR_PHY_AON_CTRL 0x0301c024
-#define CRMU_DDR_PHY_AON_CTRL_BASE 0x024
-#define CRMU_DDR_PHY_AON_CTRL_OFFSET 0x0301c024
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN 5
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY 4
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY 3
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI 2
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL 0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__RESERVED_L 31
-#define CRMU_DDR_PHY_AON_CTRL__RESERVED_R 6
-#define CRMU_DDR_PHY_AON_CTRL_WIDTH 6
-#define CRMU_DDR_PHY_AON_CTRL__WIDTH 6
-#define CRMU_DDR_PHY_AON_CTRL_ALL_L 5
-#define CRMU_DDR_PHY_AON_CTRL_ALL_R 0
-#define CRMU_DDR_PHY_AON_CTRL__ALL_L 5
-#define CRMU_DDR_PHY_AON_CTRL__ALL_R 0
-#define CRMU_DDR_PHY_AON_CTRL_DATAMASK 0x0000003f
-#define CRMU_DDR_PHY_AON_CTRL_RESETVALUE 0x7
-
-#define CRMU_IHOST_POR_WAKEUP_FLAG 0x03024c50
-#define CRMU_IHOST_POR_WAKEUP_FLAG_BASE 0xc50
-#define CRMU_IHOST_POR_WAKEUP_FLAG_OFFSET 0x03024c50
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_RESETVALUE 0x0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_L 31
-#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_R 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG_WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG__WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_L 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_R 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_L 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_R 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG_DATAMASK 0x00000001
-#define CRMU_IHOST_POR_WAKEUP_FLAG_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_00 0x18010000
-#define DDR_DENALI_CTL_00_BASE 0x000
-#define DDR_DENALI_CTL_00__VERSION_L 31
-#define DDR_DENALI_CTL_00__VERSION_R 16
-#define DDR_DENALI_CTL_00__VERSION_WIDTH 16
-#define DDR_DENALI_CTL_00__VERSION_RESETVALUE 0x2041
-#define DDR_DENALI_CTL_00__DRAM_CLASS_L 11
-#define DDR_DENALI_CTL_00__DRAM_CLASS_R 8
-#define DDR_DENALI_CTL_00__DRAM_CLASS_WIDTH 4
-#define DDR_DENALI_CTL_00__DRAM_CLASS_RESETVALUE 0x0
-#define DDR_DENALI_CTL_00__START 0
-#define DDR_DENALI_CTL_00__START_WIDTH 1
-#define DDR_DENALI_CTL_00__START_RESETVALUE 0x0
-#define DDR_DENALI_CTL_00__RESERVED_L 15
-#define DDR_DENALI_CTL_00__RESERVED_R 12
-#define DDR_DENALI_CTL_00_WIDTH 32
-#define DDR_DENALI_CTL_00__WIDTH 32
-#define DDR_DENALI_CTL_00_ALL_L 31
-#define DDR_DENALI_CTL_00_ALL_R 0
-#define DDR_DENALI_CTL_00__ALL_L 31
-#define DDR_DENALI_CTL_00__ALL_R 0
-#define DDR_DENALI_CTL_00_DATAMASK 0xffff0f01
-#define DDR_DENALI_CTL_00_RDWRMASK 0x0000f0fe
-#define DDR_DENALI_CTL_00_RESETVALUE 0x20410000
-
-#define DDR_DENALI_CTL_56 0x180100e0
-#define DDR_DENALI_CTL_56_BASE 0x0e0
-#define DDR_DENALI_CTL_56__LP_CMD_L 31
-#define DDR_DENALI_CTL_56__LP_CMD_R 24
-#define DDR_DENALI_CTL_56__LP_CMD_WIDTH 8
-#define DDR_DENALI_CTL_56__LP_CMD_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRX_F1_L 23
-#define DDR_DENALI_CTL_56__CKSRX_F1_R 16
-#define DDR_DENALI_CTL_56__CKSRX_F1_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRX_F1_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRE_F1_L 15
-#define DDR_DENALI_CTL_56__CKSRE_F1_R 8
-#define DDR_DENALI_CTL_56__CKSRE_F1_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRE_F1_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRX_F0_L 7
-#define DDR_DENALI_CTL_56__CKSRX_F0_R 0
-#define DDR_DENALI_CTL_56__CKSRX_F0_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRX_F0_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56_WIDTH 32
-#define DDR_DENALI_CTL_56__WIDTH 32
-#define DDR_DENALI_CTL_56_ALL_L 31
-#define DDR_DENALI_CTL_56_ALL_R 0
-#define DDR_DENALI_CTL_56__ALL_L 31
-#define DDR_DENALI_CTL_56__ALL_R 0
-#define DDR_DENALI_CTL_56_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_56_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_56_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57 0x180100e4
-#define DDR_DENALI_CTL_57_BASE 0x0e4
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_L 26
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R 24
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_WIDTH 3
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_L 18
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R 16
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_WIDTH 3
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_L 11
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_R 8
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_WIDTH 4
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_STATE_L 5
-#define DDR_DENALI_CTL_57__LP_STATE_R 0
-#define DDR_DENALI_CTL_57__LP_STATE_WIDTH 6
-#define DDR_DENALI_CTL_57__LP_STATE_RESETVALUE 0x20
-#define DDR_DENALI_CTL_57__RESERVED_0_L 31
-#define DDR_DENALI_CTL_57__RESERVED_0_R 27
-#define DDR_DENALI_CTL_57__RESERVED_1_L 23
-#define DDR_DENALI_CTL_57__RESERVED_1_R 19
-#define DDR_DENALI_CTL_57__RESERVED_2_L 15
-#define DDR_DENALI_CTL_57__RESERVED_2_R 12
-#define DDR_DENALI_CTL_57__RESERVED_3_L 7
-#define DDR_DENALI_CTL_57__RESERVED_3_R 6
-#define DDR_DENALI_CTL_57__RESERVED_L 31
-#define DDR_DENALI_CTL_57__RESERVED_R 27
-#define DDR_DENALI_CTL_57_WIDTH 27
-#define DDR_DENALI_CTL_57__WIDTH 27
-#define DDR_DENALI_CTL_57_ALL_L 26
-#define DDR_DENALI_CTL_57_ALL_R 0
-#define DDR_DENALI_CTL_57__ALL_L 26
-#define DDR_DENALI_CTL_57__ALL_R 0
-#define DDR_DENALI_CTL_57_DATAMASK 0x07070f3f
-#define DDR_DENALI_CTL_57_RDWRMASK 0xf8f8f0c0
-#define DDR_DENALI_CTL_57_RESETVALUE 0x20
-#define DDR_DENALI_CTL_58 0x180100e8
-#define DDR_DENALI_CTL_58_BASE 0x0e8
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_L 31
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R 24
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_WIDTH 8
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_RESETVALUE 0x00
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_L 19
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_R 8
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_WIDTH 12
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_RESETVALUE 0x000
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_L 1
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_R 0
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_WIDTH 2
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_58__RESERVED_L 23
-#define DDR_DENALI_CTL_58__RESERVED_R 20
-#define DDR_DENALI_CTL_58_WIDTH 32
-#define DDR_DENALI_CTL_58__WIDTH 32
-#define DDR_DENALI_CTL_58_ALL_L 31
-#define DDR_DENALI_CTL_58_ALL_R 0
-#define DDR_DENALI_CTL_58__ALL_L 31
-#define DDR_DENALI_CTL_58__ALL_R 0
-#define DDR_DENALI_CTL_58_DATAMASK 0xff0fff03
-#define DDR_DENALI_CTL_58_RDWRMASK 0x00f000fc
-#define DDR_DENALI_CTL_58_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_175 0x180102bc
-#define DDR_DENALI_CTL_175_BASE 0x2bc
-#define DDR_DENALI_CTL_175__INT_STATUS_L 31
-#define DDR_DENALI_CTL_175__INT_STATUS_R 0
-#define DDR_DENALI_CTL_175__INT_STATUS_WIDTH 32
-#define DDR_DENALI_CTL_175__INT_STATUS_RESETVALUE 0x00000000
-#define DDR_DENALI_CTL_175_WIDTH 32
-#define DDR_DENALI_CTL_175__WIDTH 32
-#define DDR_DENALI_CTL_175_ALL_L 31
-#define DDR_DENALI_CTL_175_ALL_R 0
-#define DDR_DENALI_CTL_175__ALL_L 31
-#define DDR_DENALI_CTL_175__ALL_R 0
-#define DDR_DENALI_CTL_175_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_175_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_175_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_177 0x180102c4
-#define DDR_DENALI_CTL_177_BASE 0x2c4
-#define DDR_DENALI_CTL_177__INT_ACK_L 31
-#define DDR_DENALI_CTL_177__INT_ACK_R 0
-#define DDR_DENALI_CTL_177__INT_ACK_WIDTH 32
-#define DDR_DENALI_CTL_177__INT_ACK_RESETVALUE 0x00000000
-#define DDR_DENALI_CTL_177_WIDTH 32
-#define DDR_DENALI_CTL_177__WIDTH 32
-#define DDR_DENALI_CTL_177_ALL_L 31
-#define DDR_DENALI_CTL_177_ALL_R 0
-#define DDR_DENALI_CTL_177__ALL_L 31
-#define DDR_DENALI_CTL_177__ALL_R 0
-#define DDR_DENALI_CTL_177_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_177_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_177_RESETVALUE 0x0
-
-#define DDR_BistConfig 0x18010c00
-#define DDR_BistConfig_BASE 0xc00
-#define DDR_BistConfig__bist_finished_period_L 24
-#define DDR_BistConfig__bist_finished_period_R 17
-#define DDR_BistConfig__bist_finished_period_WIDTH 8
-#define DDR_BistConfig__bist_finished_period_RESETVALUE 0x00
-#define DDR_BistConfig__clr_bist_last_data_err 16
-#define DDR_BistConfig__clr_bist_last_data_err_WIDTH 1
-#define DDR_BistConfig__clr_bist_last_data_err_RESETVALUE 0x0
-#define DDR_BistConfig__bus16_mode 15
-#define DDR_BistConfig__bus16_mode_WIDTH 1
-#define DDR_BistConfig__bus16_mode_RESETVALUE 0x0
-#define DDR_BistConfig__enable_8_banks_mode 14
-#define DDR_BistConfig__enable_8_banks_mode_WIDTH 1
-#define DDR_BistConfig__enable_8_banks_mode_RESETVALUE 0x0
-#define DDR_BistConfig__disable_col_bank_swapping 13
-#define DDR_BistConfig__disable_col_bank_swapping_WIDTH 1
-#define DDR_BistConfig__disable_col_bank_swapping_RESETVALUE 0x0
-#define DDR_BistConfig__bist_arpriority_L 12
-#define DDR_BistConfig__bist_arpriority_R 10
-#define DDR_BistConfig__bist_arpriority_WIDTH 3
-#define DDR_BistConfig__bist_arpriority_RESETVALUE 0x0
-#define DDR_BistConfig__bist_arapcmd 9
-#define DDR_BistConfig__bist_arapcmd_WIDTH 1
-#define DDR_BistConfig__bist_arapcmd_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awuser 8
-#define DDR_BistConfig__bist_awuser_WIDTH 1
-#define DDR_BistConfig__bist_awuser_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awpriority_L 7
-#define DDR_BistConfig__bist_awpriority_R 5
-#define DDR_BistConfig__bist_awpriority_WIDTH 3
-#define DDR_BistConfig__bist_awpriority_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awcobuf 4
-#define DDR_BistConfig__bist_awcobuf_WIDTH 1
-#define DDR_BistConfig__bist_awcobuf_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awapcmd 3
-#define DDR_BistConfig__bist_awapcmd_WIDTH 1
-#define DDR_BistConfig__bist_awapcmd_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awcache_0 2
-#define DDR_BistConfig__bist_awcache_0_WIDTH 1
-#define DDR_BistConfig__bist_awcache_0_RESETVALUE 0x0
-#define DDR_BistConfig__axi_port_sel 1
-#define DDR_BistConfig__axi_port_sel_WIDTH 1
-#define DDR_BistConfig__axi_port_sel_RESETVALUE 0x0
-#define DDR_BistConfig__bist_resetb 0
-#define DDR_BistConfig__bist_resetb_WIDTH 1
-#define DDR_BistConfig__bist_resetb_RESETVALUE 0x0
-#define DDR_BistConfig__RESERVED_L 31
-#define DDR_BistConfig__RESERVED_R 25
-#define DDR_BistConfig_WIDTH 25
-#define DDR_BistConfig__WIDTH 25
-#define DDR_BistConfig_ALL_L 24
-#define DDR_BistConfig_ALL_R 0
-#define DDR_BistConfig__ALL_L 24
-#define DDR_BistConfig__ALL_R 0
-#define DDR_BistConfig_DATAMASK 0x01ffffff
-#define DDR_BistConfig_RDWRMASK 0xfe000000
-#define DDR_BistConfig_RESETVALUE 0x0
-
-#define DDR_BistGeneralConfigurations 0x18010c08
-#define DDR_BistGeneralConfigurations_BASE 0xc08
-#define DDR_BistGeneralConfigurations__NumCols_L 6
-#define DDR_BistGeneralConfigurations__NumCols_R 4
-#define DDR_BistGeneralConfigurations__NumCols_WIDTH 3
-#define DDR_BistGeneralConfigurations__NumCols_RESETVALUE 0x2
-#define DDR_BistGeneralConfigurations__RESERVED_L 31
-#define DDR_BistGeneralConfigurations__RESERVED_R 7
-#define DDR_BistGeneralConfigurations_WIDTH 7
-#define DDR_BistGeneralConfigurations__WIDTH 7
-#define DDR_BistGeneralConfigurations_ALL_L 6
-#define DDR_BistGeneralConfigurations_ALL_R 0
-#define DDR_BistGeneralConfigurations__ALL_L 6
-#define DDR_BistGeneralConfigurations__ALL_R 0
-#define DDR_BistGeneralConfigurations_DATAMASK 0x00000070
-#define DDR_BistGeneralConfigurations_RDWRMASK 0xffffff8f
-#define DDR_BistGeneralConfigurations_RESETVALUE 0x20
-
-#define DDR_PHY_CONTROL_REGS_REVISION 0x18011000
-#define DDR_PHY_CONTROL_REGS_REVISION_BASE 0x000
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_R 25
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_WIDTH 7
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_L 24
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_R 23
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_L 22
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_R 20
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_RESETVALUE 0x2
-#define DDR_PHY_CONTROL_REGS_REVISION__WB 19
-#define DDR_PHY_CONTROL_REGS_REVISION__WB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_REVISION__WB_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_L 18
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_R 16
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_RESETVALUE 0x2
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_L 15
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_R 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_RESETVALUE 0xe2
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_L 7
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_RESETVALUE 0x01
-#define DDR_PHY_CONTROL_REGS_REVISION_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_REVISION__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_REVISION_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_REVISION_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_REVISION_RESETVALUE 0xa2e201
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS 0x18011004
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_BASE 0x004
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_WIDTH 4
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_L 19
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_R 17
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST 16
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X 15
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X 14
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X 13
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_L 12
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_R 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_WIDTH 12
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_RESETVALUE 0x000
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_R 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_WIDTH 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__WIDTH 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_DATAMASK 0x00ffffff
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RDWRMASK 0xff000000
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG 0x18011008
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_BASE 0x008
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_L 26
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_R 25
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_L 24
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_R 23
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_RESETVALUE 0x3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL 22
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_L 21
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_L 19
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_R 18
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_RESETVALUE 0x3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD 17
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE 16
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_L 13
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_R 8
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV 4
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_L 3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_L 15
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_R 14
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_L 7
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_R 5
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_DATAMASK 0x0fff3f1f
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RDWRMASK 0xf000c0e0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RESETVALUE 0x39d0000
-
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS 0x18011018
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_BASE 0x018
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_RESETVALUE 0x01
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_L 15
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R 12
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH 4
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_L 11
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_R 10
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_L 9
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH 10
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_DATAMASK 0x0ff0ffff
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RDWRMASK 0xf00f0000
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RESETVALUE 0x101020
-
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x1801102c
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_BASE 0x02c
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE 30
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_L 29
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_R 4
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_WIDTH 26
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESETVALUE 0xa
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x18011030
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_BASE 0x030
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_R 11
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_WIDTH 21
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_L 10
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x18011034
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_BASE 0x034
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_R 22
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_WIDTH 10
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_L 21
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_WIDTH 22
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESETVALUE 0x0
-
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x1801103c
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_BASE 0x03c
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5 26
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR 25
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1 24
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0 23
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT 22
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR 21
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA 20
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2 19
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1 18
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0 17
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1 16
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15 15
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14 14
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13 13
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12 12
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11 11
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10 10
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09 9
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_L 8
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_WIDTH 7
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_L 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_DATAMASK 0x0fffffff
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RDWRMASK 0xf0000000
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESETVALUE 0x0
-
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x18011200
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_BASE 0x200
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_R 20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_WIDTH 12
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_RESETVALUE 0x000
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT 19
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_L 18
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_R 17
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST 16
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3 15
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2 14
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1 13
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0 12
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_L 11
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_R 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_L 5
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESETVALUE 0xf820
-
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL 0x1801123c
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_BASE 0x23c
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_R 10
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_WIDTH 22
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1 9
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0 8
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1 7
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0 6
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N 5
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1 4
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0 3
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE 2
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RESETVALUE 0xe1
-
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL 0x18011248
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_BASE 0x248
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS 18
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ 17
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_L 16
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_R 12
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_L 11
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_R 7
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_L 6
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_R 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_WIDTH 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__WIDTH 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_L 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_L 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_DATAMASK 0x000fffff
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RDWRMASK 0xfff00000
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RESETVALUE 0x20003
-
-#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x18011400
-#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BASE 0x400
-
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x180114c8
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_BASE 0x4c8
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved 15
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_L 30
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_R 20
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESETVALUE 0x5000a
-
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x180116c8
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_BASE 0x6c8
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved 15
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_L 30
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_R 20
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESETVALUE 0x5000a
-
-#define IHOST_SCU_POWER_STATUS 0x19020008
-#define IHOST_SCU_POWER_STATUS_BASE 0x008
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_L 25
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_R 24
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_L 17
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_R 16
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_L 9
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_R 8
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__reserved_L 7
-#define IHOST_SCU_POWER_STATUS__reserved_R 2
-#define IHOST_SCU_POWER_STATUS__reserved_WIDTH 6
-#define IHOST_SCU_POWER_STATUS__reserved_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_L 1
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_R 0
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__RESERVED_0_L 31
-#define IHOST_SCU_POWER_STATUS__RESERVED_0_R 26
-#define IHOST_SCU_POWER_STATUS__RESERVED_1_L 23
-#define IHOST_SCU_POWER_STATUS__RESERVED_1_R 18
-#define IHOST_SCU_POWER_STATUS__RESERVED_2_L 15
-#define IHOST_SCU_POWER_STATUS__RESERVED_2_R 10
-#define IHOST_SCU_POWER_STATUS__RESERVED_L 31
-#define IHOST_SCU_POWER_STATUS__RESERVED_R 26
-#define IHOST_SCU_POWER_STATUS_WIDTH 26
-#define IHOST_SCU_POWER_STATUS__WIDTH 26
-#define IHOST_SCU_POWER_STATUS_ALL_L 25
-#define IHOST_SCU_POWER_STATUS_ALL_R 0
-#define IHOST_SCU_POWER_STATUS__ALL_L 25
-#define IHOST_SCU_POWER_STATUS__ALL_R 0
-#define IHOST_SCU_POWER_STATUS_DATAMASK 0x030303ff
-#define IHOST_SCU_POWER_STATUS_RDWRMASK 0xfcfcfc00
-#define IHOST_SCU_POWER_STATUS_RESETVALUE 0x0
-
-#define IHOST_GTIM_GLOB_CTRL 0x19020208
-#define IHOST_GTIM_GLOB_CTRL_BASE 0x208
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_L 15
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_R 8
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_WIDTH 8
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_RESETVALUE 0x00
-#define IHOST_GTIM_GLOB_CTRL__reserved_L 7
-#define IHOST_GTIM_GLOB_CTRL__reserved_R 4
-#define IHOST_GTIM_GLOB_CTRL__reserved_WIDTH 4
-#define IHOST_GTIM_GLOB_CTRL__reserved_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G 3
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G 2
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G 1
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G 0
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__RESERVED_L 31
-#define IHOST_GTIM_GLOB_CTRL__RESERVED_R 16
-#define IHOST_GTIM_GLOB_CTRL_WIDTH 16
-#define IHOST_GTIM_GLOB_CTRL__WIDTH 16
-#define IHOST_GTIM_GLOB_CTRL_ALL_L 15
-#define IHOST_GTIM_GLOB_CTRL_ALL_R 0
-#define IHOST_GTIM_GLOB_CTRL__ALL_L 15
-#define IHOST_GTIM_GLOB_CTRL__ALL_R 0
-#define IHOST_GTIM_GLOB_CTRL_DATAMASK 0x0000ffff
-#define IHOST_GTIM_GLOB_CTRL_RDWRMASK 0xffff0000
-#define IHOST_GTIM_GLOB_CTRL_RESETVALUE 0x0
-
-#define DDR_S0_IDM_RESET_CONTROL 0xf8101800
-#define DDR_S0_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S0_IDM_RESET_CONTROL__RESET 0
-#define DDR_S0_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL__RESET_RESETVALUE 0x0
-#define DDR_S0_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S0_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S0_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S0_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S0_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S0_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S0_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S0_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S0_IDM_RESET_CONTROL_RESETVALUE 0x0
-
-#define DDR_S1_IDM_IO_CONTROL_DIRECT 0xf8102408
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_BASE 0x408
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf 30
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0 29
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn 28
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n 27
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb 26
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby 13
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps 12
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank 11
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_L 10
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_R 9
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_WIDTH 2
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_L 8
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_R 4
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_WIDTH 5
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_RESETVALUE 0xb
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid 3
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init 2
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_L 25
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_R 14
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_WIDTH 32
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__WIDTH 32
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_L 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_R 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_L 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_R 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_DATAMASK 0xfc003ffd
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_RDWRMASK 0x03ffc002
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_RESETVALUE 0x600010b9
-#define DDR_S1_IDM_IO_STATUS 0xf8102500
-#define DDR_S1_IDM_IO_STATUS_BASE 0x500
-#define DDR_S1_IDM_IO_STATUS__RESERVED_L 31
-#define DDR_S1_IDM_IO_STATUS__RESERVED_R 4
-#define DDR_S1_IDM_IO_STATUS__RESERVED_WIDTH 28
-#define DDR_S1_IDM_IO_STATUS__RESERVED_RESETVALUE 0x0000000
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb 3
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_WIDTH 1
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready 2
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready_WIDTH 1
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_STATUS__ddr_type_L 1
-#define DDR_S1_IDM_IO_STATUS__ddr_type_R 0
-#define DDR_S1_IDM_IO_STATUS__ddr_type_WIDTH 2
-#define DDR_S1_IDM_IO_STATUS__ddr_type_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_STATUS_WIDTH 32
-#define DDR_S1_IDM_IO_STATUS__WIDTH 32
-#define DDR_S1_IDM_IO_STATUS_ALL_L 31
-#define DDR_S1_IDM_IO_STATUS_ALL_R 0
-#define DDR_S1_IDM_IO_STATUS__ALL_L 31
-#define DDR_S1_IDM_IO_STATUS__ALL_R 0
-#define DDR_S1_IDM_IO_STATUS_DATAMASK 0xffffffff
-#define DDR_S1_IDM_IO_STATUS_RDWRMASK 0x00000000
-#define DDR_S1_IDM_IO_STATUS_RESETVALUE 0x8
-#define DDR_S1_IDM_RESET_CONTROL 0xf8102800
-#define DDR_S1_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S1_IDM_RESET_CONTROL__RESET 0
-#define DDR_S1_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
-#define DDR_S1_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S1_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S1_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S1_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S1_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S1_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S1_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S1_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S1_IDM_RESET_CONTROL_RESETVALUE 0x1
-
-#define DDR_S2_IDM_RESET_CONTROL 0xf8103800
-#define DDR_S2_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S2_IDM_RESET_CONTROL__RESET 0
-#define DDR_S2_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
-#define DDR_S2_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S2_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S2_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S2_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S2_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S2_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S2_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S2_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S2_IDM_RESET_CONTROL_RESETVALUE 0x1
-
-#define ROM_S0_IDM_IO_STATUS 0xf8104500
-#define ROM_S0_IDM_IO_STATUS_BASE 0x500
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl 16
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_WIDTH 1
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_L 11
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_R 8
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_WIDTH 4
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_L 3
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_R 0
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_WIDTH 4
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__RESERVED_0_L 31
-#define ROM_S0_IDM_IO_STATUS__RESERVED_0_R 17
-#define ROM_S0_IDM_IO_STATUS__RESERVED_1_L 15
-#define ROM_S0_IDM_IO_STATUS__RESERVED_1_R 12
-#define ROM_S0_IDM_IO_STATUS__RESERVED_2_L 7
-#define ROM_S0_IDM_IO_STATUS__RESERVED_2_R 4
-#define ROM_S0_IDM_IO_STATUS__RESERVED_L 31
-#define ROM_S0_IDM_IO_STATUS__RESERVED_R 17
-#define ROM_S0_IDM_IO_STATUS_WIDTH 17
-#define ROM_S0_IDM_IO_STATUS__WIDTH 17
-#define ROM_S0_IDM_IO_STATUS_ALL_L 16
-#define ROM_S0_IDM_IO_STATUS_ALL_R 0
-#define ROM_S0_IDM_IO_STATUS__ALL_L 16
-#define ROM_S0_IDM_IO_STATUS__ALL_R 0
-#define ROM_S0_IDM_IO_STATUS_DATAMASK 0x00010f0f
-#define ROM_S0_IDM_IO_STATUS_RDWRMASK 0xfffef0f0
-#define ROM_S0_IDM_IO_STATUS_RESETVALUE 0x0
-#endif /* __SOC_BROADCOM_CYGNUS_DDR_REGS_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/hw_init.h b/src/soc/broadcom/cygnus/include/soc/hw_init.h
deleted file mode 100644
index 83dd7f3..0000000
--- a/src/soc/broadcom/cygnus/include/soc/hw_init.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_HW_INIT_H__
-#define __SOC_BROADCOM_CYGNUS_HW_INIT_H__
-
-void hw_init(void);
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/i2c.h b/src/soc/broadcom/cygnus/include/soc/i2c.h
deleted file mode 100644
index 96b5346..0000000
--- a/src/soc/broadcom/cygnus/include/soc/i2c.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_I2C_H__
-#define __SOC_BROADCOM_CYGNUS_I2C_H__
-
-void i2c_init(unsigned int bus, unsigned int hz);
-
-#endif /* __SOC_BROADCOM_CYGNUS_I2C_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
deleted file mode 100644
index 42b59da..0000000
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-SECTIONS
-{
- SRAM_START(0x02000000)
- REGION(reserved_for_system_status, 0x02000000, 4K, 4)
- TTB(0x02004000, 16K) /* must be aligned to 16K */
- TTB_SUBTABLES(0x02008000, 1K)
- REGION(reserved_for_maskrom, 0x02009400, 4K, 4)
- BOOTBLOCK(0x0200A440, 18K)
- PRERAM_CBMEM_CONSOLE(0x0200F000, 2K)
- VBOOT2_WORK(0x0200f800, 16K)
- OVERLAP_VERSTAGE_ROMSTAGE(0x02013800, 122K)
- PRERAM_CBFS_CACHE(0x02032000, 1K)
- TIMESTAMP(0x02032400, 1K)
- STACK(0x02033000, 12K)
- REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4)
- SRAM_END(0x02040000)
-
- DRAM_START(0x60000000)
- RAMSTAGE(0x60000000, 128K)
- POSTRAM_CBFS_CACHE(0x60100000, 1M)
- DMA_COHERENT(0x60200000, 2M)
-}
diff --git a/src/soc/broadcom/cygnus/include/soc/ns16550.h b/src/soc/broadcom/cygnus/include/soc/ns16550.h
deleted file mode 100644
index b95bf88..0000000
--- a/src/soc/broadcom/cygnus/include/soc/ns16550.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 Flying Pig Systems
- * Copyright (C) 2005 Wind River Systems
- * Copyright (C) 2009 DENX Software Engineering GmbH
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-
-struct ns16550 {
- union {
- uint32_t thr; /* Transmit holding register. */
- uint32_t rbr; /* Receive buffer register. */
- uint32_t dll; /* Divisor latch lsb. */
- };
- union {
- uint32_t ier; /* Interrupt enable register. */
- uint32_t dlm; /* Divisor latch msb. */
- };
- union {
- uint32_t iir; /* Interrupt identification register. */
- uint32_t fcr; /* FIFO control register. */
- };
- uint32_t lcr; /* 3 */
- uint32_t mcr; /* 4 */
- uint32_t lsr; /* 5 */
- uint32_t msr; /* 6 */
- uint32_t spr; /* 7 */
- uint32_t mdr1; /* 8 */
- uint32_t reg9; /* 9 */
- uint32_t regA; /* A */
- uint32_t regB; /* B */
- uint32_t regC; /* C */
- uint32_t regD; /* D */
- uint32_t regE; /* E */
- uint32_t uasr; /* F */
- uint32_t scr; /* 10*/
- uint32_t ssr; /* 11*/
- uint32_t reg12; /* 12*/
- uint32_t osc_12m_sel; /* 13*/
-};
-
-/*
- * These are the definitions for the FIFO Control Register
- */
-#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
-#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
-#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
-#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
-#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
-#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
-
-#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
-#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_DTR 0x01 /* DTR */
-#define UART_MCR_RTS 0x02 /* RTS */
-#define UART_MCR_OUT1 0x04 /* Out 1 */
-#define UART_MCR_OUT2 0x08 /* Out 2 */
-#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
-
-#define UART_MCR_DMA_EN 0x04
-#define UART_MCR_TX_DFR 0x08
-
-/*
- * These are the definitions for the Line Control Register
- *
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
- * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
- */
-#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
-#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
-#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
-#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
-#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
-#define UART_LCR_STB 0x04 /* # stop Bits, off=1, on=1.5 or 2) */
-#define UART_LCR_PEN 0x08 /* Parity eneble */
-#define UART_LCR_EPS 0x10 /* Even Parity Select */
-#define UART_LCR_STKP 0x20 /* Stick Parity */
-#define UART_LCR_SBRK 0x40 /* Set Break */
-#define UART_LCR_BKSE 0x80 /* Bank select enable */
-#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_DR 0x01 /* Data ready */
-#define UART_LSR_OE 0x02 /* Overrun */
-#define UART_LSR_PE 0x04 /* Parity error */
-#define UART_LSR_FE 0x08 /* Framing error */
-#define UART_LSR_BI 0x10 /* Break */
-#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
-#define UART_LSR_TEMT 0x40 /* Xmitter empty */
-#define UART_LSR_ERR 0x80 /* Error */
-
-#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
-#define UART_MSR_RI 0x40 /* Ring Indicator */
-#define UART_MSR_DSR 0x20 /* Data Set Ready */
-#define UART_MSR_CTS 0x10 /* Clear to Send */
-#define UART_MSR_DDCD 0x08 /* Delta DCD */
-#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
-#define UART_MSR_DDSR 0x02 /* Delta DSR */
-#define UART_MSR_DCTS 0x01 /* Delta CTS */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
-#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
-
-#define UART_IIR_MSI 0x00 /* Modem status interrupt */
-#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
-#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
-#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
-#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
-#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
-#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
-
-/* useful defaults for LCR: 8 data, 1 stop, no parity */
-#define UART_LCR_8N1 0x03
diff --git a/src/soc/broadcom/cygnus/include/soc/reg_utils.h b/src/soc/broadcom/cygnus/include/soc/reg_utils.h
deleted file mode 100644
index e276613..0000000
--- a/src/soc/broadcom/cygnus/include/soc/reg_utils.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_REG_UTILS__
-#define __SOC_BROADCOM_CYGNUS_REG_UTILS__
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define __REG32(x) (*((volatile uint32_t *)(x)))
-#define __REG16(x) (*((volatile uint16_t *)(x)))
-#define __REG8(x) (*((volatile uint8_t *) (x)))
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************/
-/*
- * 32-bit register access functions
- */
-/****************************************************************************/
-
-extern uint32_t reg_debug;
-#define REG_DEBUG(val) (reg_debug = val)
-
-static inline void
-reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & ~(value)));
-#endif
- *reg &= ~(value);
-}
-
-static inline void
-reg32_set_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg | value));
-#endif
- *reg |= value;
-}
-
-static inline void
-reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg ^ value));
-#endif
- *reg ^= value;
-}
-
-static inline void
-reg32_write_masked(volatile uint32_t *reg, uint32_t mask, uint32_t value)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & (~mask)) | (value & mask));
-#endif
- *reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x, 0x%x)\n", __FUNCTION__, (uint32_t)reg, value);
-#endif
- *reg = value;
-}
-
-static inline uint32_t
-reg32_read(volatile uint32_t *reg)
-{
-#ifdef DEBUG_REG
- if (reg_debug)
- printf("%s reg (0x%x): 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg);
-#endif
- return *reg;
-}
-
-/****************************************************************************/
-/*
- * 16-bit register access functions
- */
-/****************************************************************************/
-
-static inline void
-reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
-{
- *reg &= ~(value);
-}
-
-static inline void
-reg16_set_bits(volatile uint16_t *reg, uint16_t value)
-{
- *reg |= value;
-}
-
-static inline void
-reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
-{
- *reg ^= value;
-}
-
-static inline void
-reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
-{
- *reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void
-reg16_write(volatile uint16_t *reg, uint16_t value)
-{
- *reg = value;
-}
-
-static inline uint16_t
-reg16_read(volatile uint16_t *reg)
-{
- return *reg;
-}
-
-/****************************************************************************/
-/*
- * 8-bit register access functions
- */
-/****************************************************************************/
-
-static inline void
-reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
-{
- *reg &= ~(value);
-}
-
-static inline void
-reg8_set_bits(volatile uint8_t *reg, uint8_t value)
-{
- *reg |= value;
-}
-
-static inline void
-reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
-{
- *reg ^= value;
-}
-
-static inline void
-reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
-{
- *reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void
-reg8_write(volatile uint8_t *reg, uint8_t value)
-{
- *reg = value;
-}
-
-static inline uint8_t
-reg8_read(volatile uint8_t *reg)
-{
- return *reg;
-}
-#endif /* __SOC_BROADCOM_CYGNUS_REG_UTILS__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/sdram.h b/src/soc/broadcom/cygnus/include/soc/sdram.h
deleted file mode 100644
index 18a4b64..0000000
--- a/src/soc/broadcom/cygnus/include/soc/sdram.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_SDRAM_H__
-#define __SOC_BROADCOM_CYGNUS_SDRAM_H__
-
-#include <stdint.h>
-
-void ddr_init2(void);
-void sdram_init(void);
-uint32_t sdram_size_mb(void);
-
-#endif /* __SOC_BROADCOM_CYGNUS_SDRAM_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
deleted file mode 100644
index 7e233fa..0000000
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
+++ /dev/null
@@ -1,11271 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__
-#define __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_ALIGN(c, r, f) c##_##r##_##f##_ALIGN
-#define BRCM_BITS(c, r, f) c##_##r##_##f##_BITS
-#define BRCM_MASK(c, r, f) c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c, r, f) c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m, c, r, f) \
- ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f))
-
-#define SET_FIELD(m, c, r, f, d) \
- ((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \
- BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \
- )
-
-#define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d)
-#define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d)
-
-#endif /* GET & SET */
-
-/***************************************************************************
- *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION 0x00000000 /* Address & Control revision register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS 0x00000004 /* PHY PLL status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG 0x00000008 /* PHY PLL configuration register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1 0x0000000c /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2 0x00000010 /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3 0x00000014 /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS 0x00000018 /* PHY PLL integer divider register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER 0x0000001c /* PHY PLL fractional divider register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL 0x00000020 /* PHY PLL spread spectrum control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT 0x00000024 /* PHY PLL spread spectrum limit register */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL 0x00000028 /* Aux Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x0000002c /* Idle mode pad control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x00000030 /* Idle mode pad enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x00000034 /* Idle mode pad enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x00000038 /* PVT Compensation control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x0000003c /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG 0x00000040 /* DRAM configuration register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1 0x00000044 /* DRAM timing register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2 0x00000048 /* DRAM timing register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3 0x0000004c /* DRAM timing register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4 0x00000050 /* DRAM timing register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE 0x00000060 /* PHY VDL calibration control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1 0x00000064 /* PHY VDL calibration status register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2 0x00000068 /* PHY VDL calibration status register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL 0x0000006c /* PHY VDL delay monitoring control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF 0x00000070 /* PHY VDL delay monitoring reference register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS 0x00000074 /* PHY VDL delay monitoring status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE 0x00000078 /* PHY VDL delay monitoring override register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL 0x0000007c /* PHY VDL delay monitoring output control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS 0x00000080 /* PHY VDL delay monitoring output status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR 0x00000084 /* PHY VDL delay monitoring output status clear register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00 0x00000090 /* DDR interface signal AD[00] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01 0x00000094 /* DDR interface signal AD[01] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02 0x00000098 /* DDR interface signal AD[02] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03 0x0000009c /* DDR interface signal AD[03] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04 0x000000a0 /* DDR interface signal AD[04] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05 0x000000a4 /* DDR interface signal AD[05] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06 0x000000a8 /* DDR interface signal AD[06] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07 0x000000ac /* DDR interface signal AD[07] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08 0x000000b0 /* DDR interface signal AD[08] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09 0x000000b4 /* DDR interface signal AD[09] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10 0x000000b8 /* DDR interface signal AD[10] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11 0x000000bc /* DDR interface signal AD[11] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12 0x000000c0 /* DDR interface signal AD[12] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13 0x000000c4 /* DDR interface signal AD[13] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14 0x000000c8 /* DDR interface signal AD[14] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15 0x000000cc /* DDR interface signal AD[15] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0 0x000000d0 /* DDR interface signal BA[0] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1 0x000000d4 /* DDR interface signal BA[1] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2 0x000000d8 /* DDR interface signal BA[2] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0 0x000000dc /* DDR interface signal AUX[0] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1 0x000000e0 /* DDR interface signal AUX[1] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2 0x000000e4 /* DDR interface signal AUX[2] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0 0x000000e8 /* DDR interface signal CS0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1 0x000000ec /* DDR interface signal CS1 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR 0x000000f0 /* DDR interface signal PAR VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N 0x000000f4 /* DDR interface signal RAS_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N 0x000000f8 /* DDR interface signal CAS_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE 0x000000fc /* DDR interface signal CKE0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N 0x00000100 /* DDR interface signal RST_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT 0x00000104 /* DDR interface signal ODT0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N 0x00000108 /* DDR interface signal WE_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P 0x0000010c /* DDR interface signal DDR_CK-P VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N 0x00000110 /* DDR interface signal DDR_CK-N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL 0x00000114 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL 0x00000118 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH 0x00000130 /* Refresh engine controller */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL 0x00000134 /* Update VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1 0x00000138 /* Update VDL snoop control register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2 0x0000013c /* Update VDL snoop control register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1 0x00000140 /* DRAM Command Register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1 0x00000144 /* DRAM AUX_N Command Register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2 0x00000148 /* DRAM Command Register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2 0x0000014c /* DRAM AUX_N Command Register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3 0x00000150 /* DRAM Command Register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3 0x00000154 /* DRAM AUX_N Command Register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4 0x00000158 /* DRAM Command Register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4 0x0000015c /* DRAM AUX_N Command Register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER 0x00000160 /* DRAM Command Timer Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0 0x00000164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1 0x00000168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2 0x0000016c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3 0x00000170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4 0x00000174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5 0x00000178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6 0x0000017c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7 0x00000180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8 0x00000184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15 0x00000188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63 0x0000018c /* LPDDR Mode Register 63 */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR 0x00000190 /* DDR4 Alert status clear register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS 0x00000194 /* DDR4 Alert status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY 0x00000198 /* DDR4 CA parity control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL 0x0000019c /* GDDR5 CA playback control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0 0x000001a0 /* LPDDR3 and GDDR5 CA playback status register0 */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL 0x000001ac /* Write leveling control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS 0x000001b0 /* Write leveling status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL 0x000001b4 /* Read enable test cycle control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS 0x000001b8 /* Read enable test cycle status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED 0x000001c0 /* Traffic generator seed register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1 0x000001c4 /* Traffic generator address register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2 0x000001c8 /* Traffic generator address register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL 0x000001cc /* Traffic generator control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL 0x000001d0 /* Traffic generator data control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK 0x000001d4 /* Traffic generator DQ mask register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK 0x000001d8 /* Traffic generator ECC DQ mask register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS 0x000001dc /* Traffic generator status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS 0x000001e0 /* Traffic generator DQ status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS 0x000001e4 /* Traffic generator ECC DQ status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL 0x000001e8 /* Traffic generator error count control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS 0x000001ec /* Traffic generator error count status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL 0x000001f0 /* Virtual VTT Control and Status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS 0x000001f4 /* Virtual VTT Control and Status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS 0x000001f8 /* Virtual VTT Connections register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE 0x000001fc /* Virtual VTT Override register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x00000200 /* VREF DAC Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL 0x00000204 /* PhyBist Control Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED 0x00000208 /* PhyBist Seed Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK 0x0000020c /* PhyBist Command/Address Bus Mask */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS 0x00000210 /* PhyBist General Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS 0x00000214 /* PhyBist Per-Bit Control Pad Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS 0x00000218 /* PhyBist Byte Lane #0 Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS 0x0000021c /* PhyBist Byte Lane #1 Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL 0x00000230 /* Standby Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE 0x00000234 /* Freeze-on-error enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL 0x00000238 /* Debug Mux Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL 0x0000023c /* DFI Interface Ownership Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL 0x00000240 /* Write ODT Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL 0x00000244 /* ABI and PAR Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL 0x00000248 /* ZQ Calibration Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL 0x0000024c /* Ring-Osc control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS 0x00000250 /* Ring-Osc count register */
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG 0x0000011c /* Address and Control Spare register */
-
-/***************************************************************************
- *DDR34_CORE_PHY_BYTE_LANE_0 - DDR34 CORE DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x00000400 /* Write channel DQS-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N 0x00000404 /* Write channel DQS-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0 0x00000408 /* Write channel DQ0 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1 0x0000040c /* Write channel DQ1 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2 0x00000410 /* Write channel DQ2 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3 0x00000414 /* Write channel DQ3 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4 0x00000418 /* Write channel DQ4 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5 0x0000041c /* Write channel DQ5 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6 0x00000420 /* Write channel DQ6 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7 0x00000424 /* Write channel DQ7 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM 0x00000428 /* Write channel DM VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC 0x0000042c /* Write channel EDC VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP 0x00000430 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN 0x00000434 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P 0x00000438 /* Read channel DQ0-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N 0x0000043c /* Read channel DQ0-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P 0x00000440 /* Read channel DQ1-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N 0x00000444 /* Read channel DQ1-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P 0x00000448 /* Read channel DQ2-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N 0x0000044c /* Read channel DQ2-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P 0x00000450 /* Read channel DQ3-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N 0x00000454 /* Read channel DQ3-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P 0x00000458 /* Read channel DQ4-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N 0x0000045c /* Read channel DQ4-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P 0x00000460 /* Read channel DQ5-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N 0x00000464 /* Read channel DQ5-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P 0x00000468 /* Read channel DQ6-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N 0x0000046c /* Read channel DQ6-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P 0x00000470 /* Read channel DQ7-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N 0x00000474 /* Read channel DQ7-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP 0x00000478 /* Read channel DM-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN 0x0000047c /* Read channel DM-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP 0x00000480 /* Read channel EDC-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN 0x00000484 /* Read channel EDC-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0 0x00000488 /* Read channel CS_N[0] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1 0x0000048c /* Read channel CS_N[1] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL 0x00000490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL 0x00000494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL 0x000004b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo address pointer register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x000004c4 /* Read fifo status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x000004c8 /* Idle mode SSTL pad control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x000004cc /* SSTL pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL 0x000004d0 /* SSTL read enable pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL 0x000004d4 /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x000004d8 /* Write cycle preamble control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL 0x000004e0 /* Read channel ODT control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL 0x000004f0 /* GDDR5M EDC digital phase detector control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS 0x000004f4 /* GDDR5M EDC digital phase detector status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL 0x000004f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS 0x000004fc /* GDDR5M EDC digital phase detector output signal status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR 0x00000500 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL 0x00000504 /* GDDR5M EDC signal path CRC control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS 0x00000508 /* GDDR5M EDC signal path CRC status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT 0x0000050c /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR 0x00000510 /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG 0x00000514 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *DDR34_CORE_PHY_BYTE_LANE_1 - DDR34 CORE DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P 0x00000600 /* Write channel DQS-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N 0x00000604 /* Write channel DQS-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0 0x00000608 /* Write channel DQ0 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1 0x0000060c /* Write channel DQ1 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2 0x00000610 /* Write channel DQ2 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3 0x00000614 /* Write channel DQ3 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4 0x00000618 /* Write channel DQ4 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5 0x0000061c /* Write channel DQ5 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6 0x00000620 /* Write channel DQ6 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7 0x00000624 /* Write channel DQ7 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM 0x00000628 /* Write channel DM VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC 0x0000062c /* Write channel EDC VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP 0x00000630 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN 0x00000634 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P 0x00000638 /* Read channel DQ0-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N 0x0000063c /* Read channel DQ0-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P 0x00000640 /* Read channel DQ1-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N 0x00000644 /* Read channel DQ1-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P 0x00000648 /* Read channel DQ2-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N 0x0000064c /* Read channel DQ2-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P 0x00000650 /* Read channel DQ3-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N 0x00000654 /* Read channel DQ3-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P 0x00000658 /* Read channel DQ4-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N 0x0000065c /* Read channel DQ4-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P 0x00000660 /* Read channel DQ5-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N 0x00000664 /* Read channel DQ5-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P 0x00000668 /* Read channel DQ6-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N 0x0000066c /* Read channel DQ6-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P 0x00000670 /* Read channel DQ7-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N 0x00000674 /* Read channel DQ7-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP 0x00000678 /* Read channel DM-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN 0x0000067c /* Read channel DM-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP 0x00000680 /* Read channel EDC-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN 0x00000684 /* Read channel EDC-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0 0x00000688 /* Read channel CS_N[0] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1 0x0000068c /* Read channel CS_N[1] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL 0x00000690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL 0x00000694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL 0x000006b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo address pointer register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x000006c4 /* Read fifo status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x000006c8 /* Idle mode SSTL pad control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x000006cc /* SSTL pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL 0x000006d0 /* SSTL read enable pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL 0x000006d4 /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x000006d8 /* Write cycle preamble control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL 0x000006e0 /* Read channel ODT control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL 0x000006f0 /* GDDR5M EDC digital phase detector control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS 0x000006f4 /* GDDR5M EDC digital phase detector status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL 0x000006f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS 0x000006fc /* GDDR5M EDC digital phase detector output signal status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR 0x00000700 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL 0x00000704 /* GDDR5M EDC signal path CRC control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS 0x00000708 /* GDDR5M EDC signal path CRC status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT 0x0000070c /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR 0x00000710 /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG 0x00000714 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_MASK 0xfe000000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_BITS 7
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_SHIFT 25
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: PERFORMANCE [24:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_MASK 0x01800000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_SHIFT 23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: TECHNOLOGY [22:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_MASK 0x00700000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: WB [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_SHIFT 19
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: BITS [18:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_MASK 0x00070000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_DEFAULT 0x000000e2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_DEFAULT 0x00000001
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_SHIFT 24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCK_GEN [23:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_MASK 0x00f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: reserved1 [19:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_MASK 0x000e0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_SHIFT 15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK 0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK 0x00001ffe
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_MASK 0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved_for_eco1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_SHIFT 27
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_MASK 0x01800000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_MASK 0x000c0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: HOLD [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_MASK 0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: ENABLE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved2 [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_MASK 0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_MASK 0x00003f00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved3 [07:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_MASK 0x000000e0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved4 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_MASK 0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KP [09:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_MASK 0x000003c0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_DEFAULT 0x00000005
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KI [05:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_MASK 0x00000038
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_DEFAULT 0x00000002
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KA [02:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_MASK 0x00000007
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_RANGE [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_SHIFT 30
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED2 [29:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_MASK 0x20000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_SHIFT 29
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_MASK 0x10000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_SHIFT 27
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_MASK 0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_MASK 0x00c00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_MASK 0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED1 [19:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_MASK 0x000c0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_MASK 0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_MASK 0x0001c000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_SHIFT 13
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_MASK 0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: MDIV [27:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_MASK 0x0ff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [15:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK 0x0000f000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_DEFAULT 0x00000020
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_MASK 0x000ffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_MASK 0xfc000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_SHIFT 26
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_MASK 0x03fffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_SHIFT 0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_MASK 0xffe00000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_SHIFT 21
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_ODT [20:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_MASK 0x001f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_CS [12:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_MASK 0x00001f00
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved2 [07:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_MASK 0x000000e0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_AD [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [29:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_MASK 0x3ffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_BITS 26
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_MASK 0xfffff800
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_BITS 21
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_SHIFT 11
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - PVT Compensation control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_MASK 0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_SHIFT 27
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_MASK 0x01000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_MASK 0x00040000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_MASK 0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_SHIFT 15
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_MASK 0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_SHIFT 13
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_MASK 0x00000400
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved1 [08:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_MASK 0x000001fc
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_BITS 7
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: RX_MODE [01:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved0 [30:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_MASK 0x70000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_SHIFT 27
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_MASK 0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS16 [25:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_MASK 0x02000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS8 [24:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_MASK 0x01000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved1 [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_MASK 0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_SHIFT 15
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_MASK 0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_MASK 0x00003000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_MASK 0x00000300
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_MASK 0x000000f0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRAS [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRRD [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_MASK 0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRP [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRCD [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TRTP [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TWR [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_MASK 0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCWL [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCAS [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_SHIFT 24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TCAL [23:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_MASK 0x00f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRTW [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_DEFAULT 0x00000004
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TWTR [15:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_MASK 0x0000f000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRFC [11:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_MASK 0x00000fff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING4 :: temp [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_MASK 0xffffffc0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_BITS 26
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved0 [31:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_MASK 0xe0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_SHIFT 29
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved1 [27:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_MASK 0x0e000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_SHIFT 25
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved2 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000fe00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_BITS 7
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_MASK 0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *REFRESH - Refresh engine controller
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: ENABLE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: PERIOD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_MASK 0xffffffc0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_BITS 26
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: MODE [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_MASK 0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved1 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_MASK 0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_MASK 0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_MASK 0x07ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_MASK 0x00007ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_MASK 0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_MASK 0x07ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_MASK 0x00007ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_MASK 0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_SHIFT 29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_MASK 0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_MASK 0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_SHIFT 29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_MASK 0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_MASK 0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_SHIFT 29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_MASK 0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_MASK 0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_SHIFT 29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_MASK 0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_MASK 0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_BITS 15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_STATUS :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_STATUS :: STATUS [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PARITY - DDR4 CA parity control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: reserved0 [31:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_MASK 0xfffffffc
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_BITS 30
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: ERROR [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved1 [07:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_MASK 0x000000f8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_BITS 18
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_BITS 19
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved1 [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_MASK 0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_MASK 0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved1 [11:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_MASK 0x00000fc0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_CONTROL - Traffic generator control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: reserved0 [31:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_MASK 0xffffe000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_BITS 19
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_STATUS - Traffic generator status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_MASK 0xfffffe00
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_BITS 23
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_MASK 0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_BITS 13
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_MASK 0x0007fff8
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_SHIFT 15
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_MASK 0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT 13
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK 0x00000fc0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_DEFAULT 0x00000020
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK 0x0000003f
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_DEFAULT 0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved2 [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_MASK 0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_SHIFT 23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved3 [19:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_MASK 0x000e0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved4 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: SSO [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_MASK 0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: MODE [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_SEED :: SEED [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *PHYBIST_CA_MASK - PhyBist Command/Address Bus Mask
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CA_MASK :: MASK [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_SHIFT 3
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_SHIFT 8
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_SHIFT 8
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_SHIFT 0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_MASK 0xff800000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_SHIFT 23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_READY [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: ARMED [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: WARMSTART [18:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_MASK 0x00040000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_BIAS [10:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_MASK 0x00000600
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: SKIP_MRS [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: RST_N [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: CKE [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL0 [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL1 [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL0_BL0 [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL0_BL0_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_MUX_CONTROL - Debug Mux Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved0 [31:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved0_MASK 0xfffff800
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved0_BITS 21
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved0_SHIFT 11
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: BYTE_SEL [10:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_MASK 0x00000700
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_BYTE_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: reserved1 [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved1_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: PHASE_SEL [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_MASK 0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_PHASE_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_MUX_CONTROL :: SOURCE_SEL [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL_SOURCE_SEL_DEFAULT 0x00000000
-
-/***************************************************************************
- *DFI_CNTRL - DFI Interface Ownership Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: SELF_REFRESH_CS1 [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS1_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS1_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: SELF_REFRESH_CS0 [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS0_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS0_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_SELF_REFRESH_CS0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS1 [07:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_MASK 0x00000080
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS1_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CS0 [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CS0_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_RST_N [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_RST_N_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CKE1 [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE1_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE1_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: DFI_CKE0 [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE0_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE0_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_DFI_CKE0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_ENABLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: ACK_STATUS [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ACK_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DFI_CNTRL :: ASSERT_REQ [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL_ASSERT_REQ_DEFAULT 0x00000001
-
-/***************************************************************************
- *WRITE_ODT_CNTRL - Write ODT Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: reserved0 [31:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_reserved0_MASK 0xffffe000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_reserved0_BITS 19
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_reserved0_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_FORCE_VALUE [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_FORCE [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_FORCE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_ENABLE [10:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_MASK 0x00000400
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_LENGTH [09:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_MASK 0x000003c0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_LENGTH_DEFAULT 0x00000004
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_ODT_CNTRL :: ODT_DELAY [05:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_MASK 0x0000003f
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL_ODT_DELAY_DEFAULT 0x00000010
-
-/***************************************************************************
- *ABI_PAR_CNTRL - ABI and PAR Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_INCLUDE_AUX [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: PAR_ENABLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_PAR_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_INCLUDE_AUX [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_INCLUDE_AUX_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ABI_PAR_CNTRL :: ABI_ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL_ABI_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *ZQ_CAL - ZQ Calibration Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_STATUS [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_STATUS [18:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_MASK 0x00040000
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_IDDQ [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_MASK 0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_IDDQ_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_P [16:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_MASK 0x0001f000
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_P_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_DRIVE_N [11:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_MASK 0x00000f80
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_DRIVE_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: reserved_for_padding1 [06:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved_for_padding1_MASK 0x0000007c
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved_for_padding1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved_for_padding1_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_reserved_for_padding1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_PCOMP_ENB [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_PCOMP_ENB_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ZQ_CAL :: ZQ_NCOMP_ENB [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL_ZQ_NCOMP_ENB_DEFAULT 0x00000001
-
-/***************************************************************************
- *RO_PROC_MON_CTL - Ring-Osc control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: reserved0 [31:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_reserved0_MASK 0xf8000000
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_reserved0_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_reserved0_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: BUSY [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_MASK 0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: TRIGGER [25:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_MASK 0x02000000
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_TRIGGER_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: RESET [24:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_MASK 0x01000000
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_RESET_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: SEL [23:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_MASK 0x00fff000
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_CTL :: EN [11:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_MASK 0x00000fff
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL_EN_DEFAULT 0x00000000
-
-/***************************************************************************
- *RO_PROC_MON_STATUS - Ring-Osc count register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_STATUS :: CLK_COUNT [31:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_MASK 0xffffff00
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_BITS 24
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_CLK_COUNT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: RO_PROC_MON_STATUS :: RO_COUNT [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_MASK 0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS_RO_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *AC_SPARE_REG - Address and Control Spare register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: AC_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG_reserved_for_eco0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG_reserved_for_eco0_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved1_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved1_BITS 13
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_CONTROL :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_BITS 27
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_CONTROL :: MODE [04:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_MODE_MASK 0x00000010
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_MODE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_CONTROL :: reserved1 [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo address pointer register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_BITS 29
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_DATA :: DATA [31:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_BITS 32
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_reserved0_BITS 28
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_BITS 30
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved_for_padding1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved_for_padding1_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_reserved0_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved0_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved1_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved2_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved3_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved3_SHIFT 10
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: reserved4 [08:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved4_MASK 0x000001fc
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved4_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved4_BITS 7
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_reserved4_SHIFT 2
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: STATIC_PAD_CTL :: RX_MODE [01:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_BITS 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved_for_padding0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved_for_padding0_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: reserved1 [30:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved1_BITS 21
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_reserved0_BITS 26
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved0_BITS 7
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved0_BITS 20
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved1_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved2_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved3_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_reserved0_BITS 28
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved0_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved1_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_0 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG_reserved_for_eco0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG_reserved_for_eco0_BITS 32
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_DM - Write channel DM VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_DM :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_WR_EDC :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved2_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: reserved1 [15:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved1_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_reserved1_SHIFT 8
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved1_BITS 13
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_CONTROL - Read channel datapath control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_BITS 27
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_CONTROL :: MODE [04:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_MODE_MASK 0x00000010
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_MODE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_CONTROL :: RD_DATA_DLY [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007
-
-/***************************************************************************
- *READ_FIFO_ADDR - Read fifo address pointer register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: reserved0 [31:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_BITS 29
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_reserved0_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_ADDR :: ADDR [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_DATA - Read fifo data register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_DATA :: DATA [31:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_MASK 0xffffffff
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_BITS 32
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA_DATA_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_DM_DBI - Read fifo dm/dbi register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_reserved0_BITS 28
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0
-
-/***************************************************************************
- *READ_FIFO_STATUS - Read fifo status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_BITS 30
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_SHIFT 2
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_FIFO_CLEAR - Read fifo status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved_for_padding1 [15:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved_for_padding1_MASK 0x00008000
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved_for_padding1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved_for_padding1_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved_for_padding1_SHIFT 15
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [29:25] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [24:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_reserved0_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved0 [31:21] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved0_MASK 0xffe00000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved0_BITS 11
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved0_SHIFT 21
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_SHIFT 20
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved1 [19:18] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved1_MASK 0x000c0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved1_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved1_SHIFT 18
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved2_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DM_MODE [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved3 [11:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved3_MASK 0x00000c00
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved3_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved3_SHIFT 10
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: reserved4 [08:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved4_MASK 0x000001fc
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved4_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved4_BITS 7
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_reserved4_SHIFT 2
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: STATIC_PAD_CTL :: RX_MODE [01:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_MASK 0x00000003
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WR_PREAMBLE_MODE - Write cycle preamble control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_BITS 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS [11:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_SHIFT 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved1_SHIFT 5
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002
-
-/***************************************************************************
- *ODT_CONTROL - Read channel ODT control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved_for_padding0 [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved_for_padding0_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved_for_padding0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved_for_padding0_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved_for_padding0_SHIFT 31
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: reserved1 [30:10] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved1_MASK 0x7ffffc00
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved1_BITS 21
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_ENABLE [09:09] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_MASK 0x00000200
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_SHIFT 9
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_DELAY [08:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_MASK 0x000001c0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_SHIFT 6
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_DELAY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003
-
-/***************************************************************************
- *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_reserved0_BITS 26
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_reserved0_SHIFT 6
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: UPDATE [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: MONITOR [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_CONTROL :: INIT [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: reserved0 [31:25] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved0_MASK 0xfe000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved0_BITS 7
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved0_SHIFT 25
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved0_BITS 20
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_BITS 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved1 [15:11] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved1_BITS 5
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved1_SHIFT 11
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: CRCWL [10:08] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_BITS 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_SHIFT 8
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved2 [07:06] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved2_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved2_SHIFT 6
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: CRCRL [05:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_BITS 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_SHIFT 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: reserved3 [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved3_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved3_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_reserved3_SHIFT 3
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_reserved0_BITS 28
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_SHIFT 3
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: WR_PASS [02:02] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_SHIFT 2
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_SHIFT 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS :: RD_PASS [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved0_MASK 0xf0000000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved0_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_SHIFT 16
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: reserved1 [15:12] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved1_MASK 0x0000f000
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved1_BITS 4
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_reserved1_SHIFT 12
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_BITS 12
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *BL_SPARE_REG - Byte-Lane Spare register
- ***************************************************************************/
-/* DDR34_CORE_PHY_BYTE_LANE_1 :: BL_SPARE_REG :: reserved_for_eco0 [31:00] */
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_MASK 0xffffffff
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_ALIGN 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_BITS 32
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_SHIFT 0
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG_reserved_for_eco0_DEFAULT 0x00000000
-
-#endif /* __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__ */
-
-/* End of File */
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h
deleted file mode 100644
index 416b398..0000000
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_reg_access.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
-#define __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__
-
-#include <soc/cygnus_types.h>
-#define GLOBAL_REG_RBUS_START 0x0000000000000000LL
-
-uint32 REGRD(uint32 address);
-uint32 REGWR(uint32 address, uint32 data);
-
-#define DDR_PHY_REG_READ(_unit, _pc, flags, _reg_addr, _val) \
- (*(uint32 *)_val = REGRD((_pc) + (_reg_addr)))
-/* soc_ddr40_phy_reg_ci_read((_unit), (_pc), (_reg_addr), (_val)) */
-#define DDR_PHY_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \
- REGWR((_pc) + (_reg_addr), (_val))
-/* soc_ddr40_phy_reg_ci_write((_unit), (_pc), (_reg_addr), (_val)) */
-#define DDR_PHY_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \
- REGWR((_pc) + (_reg_addr), (REGRD((_pc) + (_reg_addr)) & ~(_mask)) | ((_val) & (_mask)))
-/* soc_ddr40_phy_reg_ci_modify((_unit), (_pc), (_reg_addr), (_val), (_mask)) */
-#define DDR_PHY_GET_FIELD(m, c, r, f) \
- GET_FIELD(m, c, r, f)
-#define DDR_PHY_SET_FIELD(m, c, r, f, d) \
- SET_FIELD(m, c, r, f, d)
-#endif /* __SOC_BROADCOM_CYGNUS_PHY_REG_ACCESS_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h
deleted file mode 100644
index 00b4f6c..0000000
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/shmoo_and28.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
-#define __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__
-
-#include <delay.h>
-#include <soc/cygnus_types.h>
-
-#undef printf
-#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
-#include <console/console.h>
-#define printf(args...) printk(BIOS_INFO, args)
-#else
-#define printf(args...)
-#endif
-
-#ifndef SOC_E_NONE
-#define SOC_E_NONE 0x0
-#endif
-#ifndef SOC_E_FAIL
-#define SOC_E_FAIL 0x1
-#endif
-#ifndef SOC_E_TIMEOUT
-#define SOC_E_TIMEOUT 0x2
-#endif
-#ifndef SOC_E_MEMORY
-#define SOC_E_MEMORY 0x4
-#endif
-#define SET_ADDR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
-#define SET_VREF_DAC_CONTROL(v) ((v) & 0xFFFFF)
-#define SET_WR_VDL_FORCE(v) (0x10000 | ((v) & 0x011FF))
-#define SET_WR_CHAN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x000F7))
-#define SET_RD_VDL_FORCE(v) (0x10000 | ((v) & 0x010FF))
-#define SET_RD_EN_DLY_CYC_FORCE(v) (0x10000 | ((v) & 0x001FF))
-#define SET_RD_CONTROL(v) ((v) & 0x0001F)
-
-#define SHMOO_AND28_PHY_TYPE_RSVP 0
-#define SHMOO_AND28_PHY_TYPE_E0 0xE0
-#define SHMOO_AND28_PHY_TYPE_E2 0xE2
-#define SHMOO_AND28_PHY_TYPE_F0 0xF0
-
-#define SHMOO_AND28_CTL_TYPE_RSVP 0
-#define SHMOO_AND28_CTL_TYPE_RSVP_STR "t0"
-#define SHMOO_AND28_CTL_TYPE_1 1
-#define SHMOO_AND28_CTL_TYPE_1_STR "t1"
-
-#define SHMOO_AND28_DRAM_TYPE_RSVP 0
-#define SHMOO_AND28_DRAM_TYPE_DDR3 3
-#define SHMOO_AND28_DRAM_TYPE_DDR3L 31
-#define SHMOO_AND28_DRAM_TYPE_DDR4 4
-#define SHMOO_AND28_DRAM_TYPE_GDDR5 5
-
-#define SHMOO_AND28_PHY_REG_BASE_RSVP 0
-#define SHMOO_AND28_PHY_REG_BASE_CYGNUS 0x18011000
-#define SHMOO_AND28_PHY_REG_BASE_GREYHOUND 0x18011000
-
-#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_RSVP 0
-#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE_GREYHOUND 0x18010C00
-
-#define SHMOO_AND28_CHIP_ID_RSVP 0
-#define SHMOO_AND28_CHIP_ID_CYGNUS 0xC
-#define SHMOO_AND28_CHIP_ID_GREYHOUND 0x6
-
-#define SHMOO_AND28_CHIP_ID SHMOO_AND28_CHIP_ID_CYGNUS
-#define SHMOO_AND28_PHY_TYPE SHMOO_AND28_PHY_TYPE_E2
-#define SHMOO_AND28_PHY_REG_BASE SHMOO_AND28_PHY_REG_BASE_CYGNUS
-#define SHMOO_AND28_YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE_CYGNUS
-#define SHMOO_AND28_CTL_TYPE SHMOO_AND28_CTL_TYPE_1
-#define SHMOO_AND28_DRAM_TYPE SHMOO_AND28_DRAM_TYPE_DDR3L
-#define SHMOO_AND28_PHY_BITWIDTH 16
-#define SHMOO_AND28_PHY_CONSTANT_CONFIG 0
-#define PHY_AND28_E2 SHMOO_AND28_PHY_TYPE
-
-#define SHMOO_AND28_PHY_BITWIDTH_IS_32 (SHMOO_AND28_PHY_BITWIDTH >> 5)
-#define YDC_DDR_BIST_PHY_BITWIDTH_IS_32 SHMOO_AND28_PHY_BITWIDTH_IS_32
-#define YDC_DDR_BIST_REG_BASE SHMOO_AND28_YDC_DDR_BIST_REG_BASE
-
-#define SHMOO_AND28_BIT 1
-#define SHMOO_AND28_BYTE (SHMOO_AND28_BIT << 3)
-#define SHMOO_AND28_HALFWORD (SHMOO_AND28_BYTE << 1)
-#define SHMOO_AND28_WORD (SHMOO_AND28_HALFWORD << 1)
-#define SHMOO_AND28_DOUBLEWORD (SHMOO_AND28_WORD << 1)
-#define SHMOO_AND28_QUADWORD (SHMOO_AND28_DOUBLEWORD << 1)
-
-#define SHMOO_AND28_SHORT_SLEEP 1
-#define SHMOO_AND28_LONG_SLEEP 10
-#define SHMOO_AND28_DEEP_SLEEP 100
-#define SHMOO_AND28_HIBERNATION 1000
-#define SHMOO_AND28_STASIS 1000000
-
-#define SHMOO_AND28_SHMOO_RSVP -1
-#define SHMOO_AND28_RD_EN 23
-#define SHMOO_AND28_RD_EXTENDED 50
-#define SHMOO_AND28_WR_EXTENDED 60
-#define SHMOO_AND28_ADDR_EXTENDED 71
-#define SHMOO_AND28_CTRL_EXTENDED 72
-#define SHMOO_AND28_DDR3_SEQUENCE_COUNT 5
-#define SHMOO_AND28_DDR3L_SEQUENCE_COUNT 5
-/* BEGIN: EXTRA */
-/* END: EXTRA */
-
-#define SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED 1
-
-#define SHMOO_AND28_REPEAT 9
-#define SHMOO_AND28_REPEAT_HALF (SHMOO_COMBO28_REPEAT >> 1)
-
-#define SHMOO_AND28_SEQUENTIAL 0
-#define SHMOO_AND28_SINGLE 1
-
-#define SHMOO_AND28_ACTION_RSVP -1
-#define SHMOO_AND28_ACTION_RESTORE 0
-#define SHMOO_AND28_ACTION_RUN 1
-#define SHMOO_AND28_ACTION_SAVE 2
-#define SHMOO_AND28_ACTION_RUN_AND_SAVE 3
-
-#define SHMOO_AND28_MAX_INTERFACES 8
-#define SHMOO_AND28_INTERFACE_RSVP -1
-#define SHMOO_AND28_BYTES_PER_INTERFACE 4
-
-#define SHMOO_AND28_BIST_NOF_PATTERNS 8
-#define SHMOO_AND28_BIST_MPR_NOF_PATTERNS 4
-
-#define SHMOO_AND28_MAX_VISIBLE_UI_COUNT 4
-#define SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT 4
-#define SHMOO_AND28_LAST_EFFECTIVE_UI (SHMOO_AND28_MAX_EFFECTIVE_UI_COUNT - 1)
-#define SHMOO_AND28_MAX_VDL_LENGTH 256
-#define SHMOO_AND28_MAX_VREF_RANGE 64
-#define SHMOO_AND28_MAX_ZQ_CAL_RANGE 32
-
-#define SHMOO_AND28_RESULT2D_X SHMOO_AND28_MAX_VDL_LENGTH
-#define SHMOO_AND28_RESULT2D_Y SHMOO_AND28_MAX_VREF_RANGE
-
-#define SHMOO_AND28_STRING_LENGTH (SHMOO_AND28_RESULT2D_X + 1)
-#define SHMOO_AND28_ERROR_ARRAY_LENGTH 4
-
-#define SHMOO_AND28_CALIB_CENTER_PASS 111
-#define SHMOO_AND28_CALIB_RISING_EDGE 011
-#define SHMOO_AND28_CALIB_FALLING_EDGE 100
-#define SHMOO_AND28_CALIB_PASS_START 001
-#define SHMOO_AND28_CALIB_FAIL_START 110
-#define SHMOO_AND28_CALIB_VDL_ZERO 000
-
-#define SHMOO_AND28_VDL_TFIX 18
-
-#define SHMOO_AND28_RD_DATA_DLY_INIT 7
-
-#define SHMOO_AND28_RD_EN_CYC_INIT 1
-
-#define SHMOO_AND28_RD_EN_VDL_INIT 0
-
-#define SHMOO_AND28_RD_DQ_VDL_INIT 0
-#define SHMOO_AND28_RD_DQ_FAIL_CAP 5
-
-#define SHMOO_AND28_RD_DQS_VDL_OFFSET SHMOO_AND28_RD_DQ_VDL_INIT
-
-#define SHMOO_AND28_WR_CYC_INIT 0
-
-#define SHMOO_AND28_PHY_NOF_AD 16
-#define SHMOO_AND28_PHY_NOF_BA 3
-#define SHMOO_AND28_PHY_NOF_AUX 3
-#define SHMOO_AND28_PHY_NOF_CS 2
-
-typedef struct and28_shmoo_dram_info_s {
- uint32 ctl_type;
- uint32 dram_type;
- uint32 dram_bitmap;
- uint32 interface_bitwidth;
- int num_columns;
- int num_rows;
- int num_banks;
- int data_rate_mbps;
- int ref_clk_mhz;
- uint32 refi;
- uint32 command_parity_latency;
- int sim_system_mode;
-} and28_shmoo_dram_info_t;
-
-typedef struct and28_shmoo_config_param_s {
- uint16 control_regs_ad[SHMOO_AND28_PHY_NOF_AD];
- uint16 control_regs_ba[SHMOO_AND28_PHY_NOF_BA];
- uint16 control_regs_aux[SHMOO_AND28_PHY_NOF_AUX];
- uint16 control_regs_cs[SHMOO_AND28_PHY_NOF_CS];
- uint16 control_regs_par;
- uint16 control_regs_ras_n;
- uint16 control_regs_cas_n;
- uint16 control_regs_cke;
- uint16 control_regs_rst_n;
- uint16 control_regs_odt;
- uint16 control_regs_we_n;
- uint32 control_regs_vref_dac_control;
-
- uint16 wr_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 wr_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 wr_vdl_dq[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
- uint16 wr_vdl_dm[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 wr_vdl_edc[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint8 wr_chan_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
-
- uint16 rd_vdl_dqsp[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 rd_vdl_dqsn[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 rd_vdl_dqp[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
- uint16 rd_vdl_dqn[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_BYTE];
- uint16 rd_vdl_dmp[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 rd_vdl_dmn[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint16 rd_en_vdl_cs[SHMOO_AND28_BYTES_PER_INTERFACE][SHMOO_AND28_PHY_NOF_CS];
- uint16 rd_en_dly_cyc[SHMOO_AND28_BYTES_PER_INTERFACE];
- uint8 rd_control[SHMOO_AND28_BYTES_PER_INTERFACE];
-} and28_shmoo_config_param_t;
-
-typedef struct and28_vendor_info_s {
- uint32 dram_density;
- uint32 fifo_depth;
- uint32 revision_id;
- uint32 manufacture_id;
-} and28_vendor_info_t;
-
-typedef struct and28_shmoo_container_s {
- uint32 sizeX;
- uint32 sizeY;
- uint32 yCapMin;
- uint32 yCapMax;
- uint32 yJump;
- uint32 calibMode;
- uint32 calibPos;
- uint32 calibStart;
- uint32 result2D[(SHMOO_AND28_RESULT2D_X)*(SHMOO_AND28_RESULT2D_Y)];
- uint32 resultData[SHMOO_AND28_WORD];
- uint32 shmooType;
- uint32 dramType;
- uint32 ctlType;
- uint32 trefi;
- uint32 step1000;
- uint32 size1000UI;
- uint32 endUI[SHMOO_AND28_MAX_VISIBLE_UI_COUNT];
- uint32 engageUIshift;
- uint32 wckInv;
-} and28_shmoo_container_t;
-
-typedef struct and28_step_size_s {
- uint32 step1000;
- uint32 size1000UI;
-} and28_step_size_t;
-
-typedef struct and28_ui_position_s {
- uint32 ui;
- uint32 position;
-} and28_ui_position_t;
-
-typedef uint32 and28_shmoo_error_array_t[SHMOO_AND28_ERROR_ARRAY_LENGTH];
-
-int soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi);
-int soc_and28_shmoo_phy_init(int unit, int phy_ndx);
-int soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat,
- int plot, int action, and28_shmoo_config_param_t *config_param);
-
-#endif /* __SOC_BROADCOM_CYGNUS_SHMOO_AND28_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h
deleted file mode 100644
index 97fba17..0000000
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/ydc_ddr_bist.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__
-#define __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__
-
-#include <delay.h>
-#include <soc/cygnus_types.h>
-
-#ifndef YDC_DDR_BIST_REG_BASE
-#define YDC_DDR_BIST_REG_BASE 0x18010C00
-#endif
-
-#ifndef YDC_DDR_BIST_PHY_BITWITDH_IS_32
-#define YDC_DDR_BIST_PHY_BITWITDH_IS_32 1
-#endif
-
-#define YDC_DDR_BIST_POLL_INTERVAL_US 10
-#define YDC_DDR_BIST_POLL_COUNT_LIMIT 100000
-
-#define SOC_E_NONE 0x0
-#define SOC_E_FAIL 0x1
-#define SOC_E_TIMEOUT 0x2
-#define SOC_E_MEMORY 0x4
-
-typedef struct ydc_ddr_bist_info_s {
- uint32 write_weight;
- uint32 read_weight;
- uint32 bist_timer_us; /* if bist_timer_us != 0, ignore bist_num_actions and wait bist_timer_us before stoping bist */
- uint32 bist_num_actions;
- uint32 bist_start_address;
- uint32 bist_end_address;
- uint32 prbs_mode;
- uint32 mpr_mode;
-} ydc_ddr_bist_info_t;
-
-typedef struct ydc_ddr_bist_err_cnt_s {
- uint32 bist_err_occur;
- uint32 bist_full_err_cnt;
- uint32 bist_single_err_cnt;
- uint32 bist_global_err_cnt;
-} ydc_ddr_bist_err_cnt_t;
-
-extern int soc_ydc_ddr_bist_config_set(int unit, int phy_ndx,
- ydc_ddr_bist_info_t *bist_info);
-extern int soc_ydc_ddr_bist_run(int unit, int phy_ndx,
- ydc_ddr_bist_err_cnt_t *error_count);
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_ALIGN(c, r, f) c##_##r##_##f##_ALIGN
-#define BRCM_BITS(c, r, f) c##_##r##_##f##_BITS
-#define BRCM_MASK(c, r, f) c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c, r, f) c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m, c, r, f) \
- ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f))
-
-#define SET_FIELD(m, c, r, f, d) \
- ((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \
- BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \
- )
-
-#define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d)
-#define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d)
-
-#endif /* GET & SET */
-
-#define YDC_DDR_BIST_REG_READ(_unit, _pc, flags, _reg_addr, _val) \
- (*(uint32 *)_val = REGRD((_pc) + (_reg_addr)))
-#define YDC_DDR_BIST_REG_WRITE(_unit, _pc, _flags, _reg_addr, _val) \
- REGWR((_pc) + (_reg_addr), (_val))
-#define YDC_DDR_BIST_REG_MODIFY(_unit, _pc, _flags, _reg_addr, _val, _mask) \
- REGWR((_pc) + (_reg_addr), (REGRD((_pc) + (_reg_addr)) & ~(_mask)) | ((_val) & (_mask)))
-#define YDC_DDR_BIST_GET_FIELD(m, c, r, f) \
- GET_FIELD(m, c, r, f)
-#define YDC_DDR_BIST_SET_FIELD(m, c, r, f, d) \
- SET_FIELD(m, c, r, f, d)
-
-/****************************************************************************
- * Core Enums.
- ***************************************************************************/
-#define YDC_DDR_BIST_CONFIG 0x00000000
-#define YDC_DDR_BIST_CONFIG_2 0x00000004
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS 0x00000008
-#define YDC_DDR_BIST_CONFIGURATIONS 0x0000000C
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS 0x00000010
-#define YDC_DDR_BIST_START_ADDRESS 0x00000014
-#define YDC_DDR_BIST_END_ADDRESS 0x00000018
-#define YDC_DDR_BIST_SINGLE_BIT_MASK 0x0000001C
-#define YDC_DDR_BIST_PATTERN_WORD_7 0x00000020
-#define YDC_DDR_BIST_PATTERN_WORD_6 0x00000024
-#define YDC_DDR_BIST_PATTERN_WORD_5 0x00000028
-#define YDC_DDR_BIST_PATTERN_WORD_4 0x0000002C
-#define YDC_DDR_BIST_PATTERN_WORD_3 0x00000030
-#define YDC_DDR_BIST_PATTERN_WORD_2 0x00000034
-#define YDC_DDR_BIST_PATTERN_WORD_1 0x00000038
-#define YDC_DDR_BIST_PATTERN_WORD_0 0x0000003C
-#define YDC_DDR_BIST_FULL_MASK_WORD_7 0x00000040
-#define YDC_DDR_BIST_FULL_MASK_WORD_6 0x00000044
-#define YDC_DDR_BIST_FULL_MASK_WORD_5 0x00000048
-#define YDC_DDR_BIST_FULL_MASK_WORD_4 0x0000004C
-#define YDC_DDR_BIST_FULL_MASK_WORD_3 0x00000050
-#define YDC_DDR_BIST_FULL_MASK_WORD_2 0x00000054
-#define YDC_DDR_BIST_FULL_MASK_WORD_1 0x00000058
-#define YDC_DDR_BIST_FULL_MASK_WORD_0 0x0000005C
-#define YDC_DDR_BIST_STATUSES 0x00000060
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER 0x00000064
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER 0x00000068
-#define YDC_DDR_BIST_ERROR_OCCURRED 0x0000006C
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER 0x00000070
-#define YDC_DDR_BIST_LAST_ADDR_ERR 0x00000074
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7 0x00000078
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6 0x0000007C
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5 0x00000080
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4 0x00000084
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3 0x00000088
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2 0x0000008C
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1 0x00000090
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0 0x00000094
-
-/****************************************************************************
- * YDC_DDR_BIST_YDC_DDR_BIST
- ***************************************************************************/
-
-/* BIST Configuration Register */
-#define READ_YDC_DDR_BIST_CONFIGr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000000, (_val))
-#define WRITE_YDC_DDR_BIST_CONFIGr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000000, (_val))
-#define MODIFY_YDC_DDR_BIST_CONFIGr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000000, (_val), (_mask))
-
-/* BIST Configuration Register 2 */
-#define READ_YDC_DDR_BIST_CONFIG_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000004, (_val))
-#define WRITE_YDC_DDR_BIST_CONFIG_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000004, (_val))
-#define MODIFY_YDC_DDR_BIST_CONFIG_2r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000004, (_val), (_mask))
-
-/* BIST General Configurations Register */
-#define READ_YDC_DDR_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000008, (_val))
-#define WRITE_YDC_DDR_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000008, (_val))
-#define MODIFY_YDC_DDR_BIST_GENERAL_CONFIGURATIONSr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000008, (_val), (_mask))
-
-/* BIST Configurations Register */
-#define READ_YDC_DDR_BIST_CONFIGURATIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000000c, (_val))
-#define WRITE_YDC_DDR_BIST_CONFIGURATIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000000c, (_val))
-#define MODIFY_YDC_DDR_BIST_CONFIGURATIONSr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000000c, (_val), (_mask))
-
-/* BIST Number of Actions Register */
-#define READ_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000010, (_val))
-#define WRITE_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000010, (_val))
-#define MODIFY_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000010, (_val), (_mask))
-
-/* BIST Start Address Register */
-#define READ_YDC_DDR_BIST_START_ADDRESSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000014, (_val))
-#define WRITE_YDC_DDR_BIST_START_ADDRESSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000014, (_val))
-#define MODIFY_YDC_DDR_BIST_START_ADDRESSr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000014, (_val), (_mask))
-
-/* BIST End Address Register */
-#define READ_YDC_DDR_BIST_END_ADDRESSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000018, (_val))
-#define WRITE_YDC_DDR_BIST_END_ADDRESSr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000018, (_val))
-#define MODIFY_YDC_DDR_BIST_END_ADDRESSr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000018, (_val), (_mask))
-
-/* BIST Single Bit Mask Register */
-#define READ_YDC_DDR_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000001c, (_val))
-#define WRITE_YDC_DDR_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000001c, (_val))
-#define MODIFY_YDC_DDR_BIST_SINGLE_BIT_MASKr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000001c, (_val), (_mask))
-
-/* BIST Pattern Word 7 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000020, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000020, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_7r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000020, (_val), (_mask))
-
-/* BIST Pattern Word 6 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000024, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000024, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_6r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000024, (_val), (_mask))
-
-/* BIST Pattern Word 5 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000028, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000028, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_5r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000028, (_val), (_mask))
-
-/* BIST Pattern Word 4 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000002c, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000002c, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_4r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000002c, (_val), (_mask))
-
-/* BIST Pattern Word 3 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000030, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000030, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_3r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000030, (_val), (_mask))
-
-/* BIST Pattern Word 2 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000034, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000034, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_2r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000034, (_val), (_mask))
-
-/* BIST Pattern Word 1 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000038, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000038, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_1r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000038, (_val), (_mask))
-
-/* BIST Pattern Word 0 Register */
-#define READ_YDC_DDR_BIST_PATTERN_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000003c, (_val))
-#define WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000003c, (_val))
-#define MODIFY_YDC_DDR_BIST_PATTERN_WORD_0r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000003c, (_val), (_mask))
-
-/* BIST Full Mask Word 7 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000040, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000040, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_7r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000040, (_val), (_mask))
-
-/* BIST Full Mask Word 6 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000044, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000044, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_6r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000044, (_val), (_mask))
-
-/* BIST Full Mask Word 5 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000048, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000048, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_5r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000048, (_val), (_mask))
-
-/* BIST Full Mask Word 4 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000004c, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000004c, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_4r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000004c, (_val), (_mask))
-
-/* BIST Full Mask Word 3 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000050, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000050, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_3r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000050, (_val), (_mask))
-
-/* BIST Full Mask Word 2 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000054, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000054, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_2r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000054, (_val), (_mask))
-
-/* BIST Full Mask Word 1 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000058, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000058, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_1r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000058, (_val), (_mask))
-
-/* BIST Full Mask Word 0 Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000005c, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000005c, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_WORD_0r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000005c, (_val), (_mask))
-
-/* BIST Status Register */
-#define READ_YDC_DDR_BIST_STATUSESr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000060, (_val))
-#define WRITE_YDC_DDR_BIST_STATUSESr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000060, (_val))
-#define MODIFY_YDC_DDR_BIST_STATUSESr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000060, (_val), (_mask))
-
-/* BIST Full Mask Error Counter Register */
-#define READ_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000064, (_val))
-#define WRITE_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000064, (_val))
-#define MODIFY_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000064, (_val), (_mask))
-
-/* BIST Single Bit Mask Error Counter Register */
-#define READ_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000068, (_val))
-#define WRITE_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000068, (_val))
-#define MODIFY_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000068, (_val), (_mask))
-
-/* BIST Error Occurred Register */
-#define READ_YDC_DDR_BIST_ERROR_OCCURREDr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000006c, (_val))
-#define WRITE_YDC_DDR_BIST_ERROR_OCCURREDr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000006c, (_val))
-#define MODIFY_YDC_DDR_BIST_ERROR_OCCURREDr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000006c, (_val), (_mask))
-
-/* BIST Global Error Counter Register */
-#define READ_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000070, (_val))
-#define WRITE_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000070, (_val))
-#define MODIFY_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000070, (_val), (_mask))
-
-/* BIST Last Error Address Register */
-#define READ_YDC_DDR_BIST_LAST_ADDR_ERRr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000074, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_ADDR_ERRr(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000074, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_ADDR_ERRr(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000074, (_val), (_mask))
-
-/* BIST Last Data Error Word 7 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000078, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_7r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000078, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_7r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000078, (_val), (_mask))
-
-/* BIST Last Data Error Word 6 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000007c, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_6r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000007c, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_6r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000007c, (_val), (_mask))
-
-/* BIST Last Data Error Word 5 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000080, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_5r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000080, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_5r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000080, (_val), (_mask))
-
-/* BIST Last Data Error Word 4 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000084, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_4r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000084, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_4r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000084, (_val), (_mask))
-
-/* BIST Last Data Error Word 3 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000088, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_3r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000088, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_3r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000088, (_val), (_mask))
-
-/* BIST Last Data Error Word 2 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x0000008c, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_2r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x0000008c, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_2r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x0000008c, (_val), (_mask))
-
-/* BIST Last Data Error Word 1 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000090, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_1r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000090, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_1r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000090, (_val), (_mask))
-
-/* BIST Last Data Error Word 0 Register */
-#define READ_YDC_DDR_BIST_LAST_DATA_ERR_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_READ((_unit), (_pc), 0x00, 0x00000094, (_val))
-#define WRITE_YDC_DDR_BIST_LAST_DATA_ERR_WORD_0r(_unit, _pc, _val) \
- YDC_DDR_BIST_REG_WRITE((_unit), (_pc), 0x00, 0x00000094, (_val))
-#define MODIFY_YDC_DDR_BIST_LAST_DATA_ERR_WORD_0r(_unit, _pc, _val, _mask) \
- YDC_DDR_BIST_REG_MODIFY((_unit), (_pc), 0x00, 0x00000094, (_val), (_mask))
-
-
-/****************************************************************************
- * YDC_DDR_BIST_YDC_DDR_BIST
- ***************************************************************************/
-/****************************************************************************
- * YDC_DDR_BIST :: CONFIG
- ***************************************************************************/
-/* YDC_DDR_BIST :: CONFIG :: reserved0 [31:25] */
-#define YDC_DDR_BIST_CONFIG_RESERVED0_MASK 0xfe000000
-#define YDC_DDR_BIST_CONFIG_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_RESERVED0_BITS 7
-#define YDC_DDR_BIST_CONFIG_RESERVED0_SHIFT 25
-#define YDC_DDR_BIST_CONFIG_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_FINISHED_PERIOD [24:17] */
-#define YDC_DDR_BIST_CONFIG_BIST_FINISHED_PERIOD_MASK 0x01fe0000
-#define YDC_DDR_BIST_CONFIG_BIST_FINISHED_PERIOD_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_FINISHED_PERIOD_BITS 8
-#define YDC_DDR_BIST_CONFIG_BIST_FINISHED_PERIOD_SHIFT 17
-#define YDC_DDR_BIST_CONFIG_BIST_FINISHED_PERIOD_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: CLR_BIST_LAST_DATA_ERR [16:16] */
-#define YDC_DDR_BIST_CONFIG_CLR_BIST_LAST_DATA_ERR_MASK 0x00010000
-#define YDC_DDR_BIST_CONFIG_CLR_BIST_LAST_DATA_ERR_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_CLR_BIST_LAST_DATA_ERR_BITS 1
-#define YDC_DDR_BIST_CONFIG_CLR_BIST_LAST_DATA_ERR_SHIFT 16
-#define YDC_DDR_BIST_CONFIG_CLR_BIST_LAST_DATA_ERR_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BUS16_MODE [15:15] */
-#define YDC_DDR_BIST_CONFIG_BUS16_MODE_MASK 0x00008000
-#define YDC_DDR_BIST_CONFIG_BUS16_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BUS16_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIG_BUS16_MODE_SHIFT 15
-#define YDC_DDR_BIST_CONFIG_BUS16_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: ENABLE_8_BANKS_MODE [14:14] */
-#define YDC_DDR_BIST_CONFIG_ENABLE_8_BANKS_MODE_MASK 0x00004000
-#define YDC_DDR_BIST_CONFIG_ENABLE_8_BANKS_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_ENABLE_8_BANKS_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIG_ENABLE_8_BANKS_MODE_SHIFT 14
-#define YDC_DDR_BIST_CONFIG_ENABLE_8_BANKS_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: DISABLE_COL_BANK_SWAPPING [13:13] */
-#define YDC_DDR_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_MASK 0x00002000
-#define YDC_DDR_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_BITS 1
-#define YDC_DDR_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_SHIFT 13
-#define YDC_DDR_BIST_CONFIG_DISABLE_COL_BANK_SWAPPING_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_ARPRIORITY [12:10] */
-#define YDC_DDR_BIST_CONFIG_BIST_ARPRIORITY_MASK 0x00001c00
-#define YDC_DDR_BIST_CONFIG_BIST_ARPRIORITY_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_ARPRIORITY_BITS 3
-#define YDC_DDR_BIST_CONFIG_BIST_ARPRIORITY_SHIFT 10
-#define YDC_DDR_BIST_CONFIG_BIST_ARPRIORITY_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_ARAPCMD [09:09] */
-#define YDC_DDR_BIST_CONFIG_BIST_ARAPCMD_MASK 0x00000200
-#define YDC_DDR_BIST_CONFIG_BIST_ARAPCMD_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_ARAPCMD_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_ARAPCMD_SHIFT 9
-#define YDC_DDR_BIST_CONFIG_BIST_ARAPCMD_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_AWUSER [08:08] */
-#define YDC_DDR_BIST_CONFIG_BIST_AWUSER_MASK 0x00000100
-#define YDC_DDR_BIST_CONFIG_BIST_AWUSER_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_AWUSER_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_AWUSER_SHIFT 8
-#define YDC_DDR_BIST_CONFIG_BIST_AWUSER_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_AWPRIORITY [07:05] */
-#define YDC_DDR_BIST_CONFIG_BIST_AWPRIORITY_MASK 0x000000e0
-#define YDC_DDR_BIST_CONFIG_BIST_AWPRIORITY_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_AWPRIORITY_BITS 3
-#define YDC_DDR_BIST_CONFIG_BIST_AWPRIORITY_SHIFT 5
-#define YDC_DDR_BIST_CONFIG_BIST_AWPRIORITY_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_AWCOBUF [04:04] */
-#define YDC_DDR_BIST_CONFIG_BIST_AWCOBUF_MASK 0x00000010
-#define YDC_DDR_BIST_CONFIG_BIST_AWCOBUF_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_AWCOBUF_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_AWCOBUF_SHIFT 4
-#define YDC_DDR_BIST_CONFIG_BIST_AWCOBUF_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_AWAPCMD [03:03] */
-#define YDC_DDR_BIST_CONFIG_BIST_AWAPCMD_MASK 0x00000008
-#define YDC_DDR_BIST_CONFIG_BIST_AWAPCMD_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_AWAPCMD_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_AWAPCMD_SHIFT 3
-#define YDC_DDR_BIST_CONFIG_BIST_AWAPCMD_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_AWCACHE_0 [02:02] */
-#define YDC_DDR_BIST_CONFIG_BIST_AWCACHE_0_MASK 0x00000004
-#define YDC_DDR_BIST_CONFIG_BIST_AWCACHE_0_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_AWCACHE_0_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_AWCACHE_0_SHIFT 2
-#define YDC_DDR_BIST_CONFIG_BIST_AWCACHE_0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: AXI_PORT_SEL [01:01] */
-#define YDC_DDR_BIST_CONFIG_AXI_PORT_SEL_MASK 0x00000002
-#define YDC_DDR_BIST_CONFIG_AXI_PORT_SEL_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_AXI_PORT_SEL_BITS 1
-#define YDC_DDR_BIST_CONFIG_AXI_PORT_SEL_SHIFT 1
-#define YDC_DDR_BIST_CONFIG_AXI_PORT_SEL_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG :: BIST_RESETB [00:00] */
-#define YDC_DDR_BIST_CONFIG_BIST_RESETB_MASK 0x00000001
-#define YDC_DDR_BIST_CONFIG_BIST_RESETB_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_BIST_RESETB_BITS 1
-#define YDC_DDR_BIST_CONFIG_BIST_RESETB_SHIFT 0
-#define YDC_DDR_BIST_CONFIG_BIST_RESETB_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: CONFIG_2
- ***************************************************************************/
-/* YDC_DDR_BIST :: CONFIG_2 :: reserved0 [31:19] */
-#define YDC_DDR_BIST_CONFIG_2_RESERVED0_MASK 0xfff80000
-#define YDC_DDR_BIST_CONFIG_2_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_RESERVED0_BITS 13
-#define YDC_DDR_BIST_CONFIG_2_RESERVED0_SHIFT 19
-#define YDC_DDR_BIST_CONFIG_2_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG_2 :: FIFO_RADDR_ALMOST_FULL_LEVEL [18:16] */
-#define YDC_DDR_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_MASK 0x00070000
-#define YDC_DDR_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_BITS 3
-#define YDC_DDR_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_SHIFT 16
-#define YDC_DDR_BIST_CONFIG_2_FIFO_RADDR_ALMOST_FULL_LEVEL_DEFAULT 0x00000004
-
-/* YDC_DDR_BIST :: CONFIG_2 :: reserved1 [15:11] */
-#define YDC_DDR_BIST_CONFIG_2_RESERVED1_MASK 0x0000f800
-#define YDC_DDR_BIST_CONFIG_2_RESERVED1_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_RESERVED1_BITS 5
-#define YDC_DDR_BIST_CONFIG_2_RESERVED1_SHIFT 11
-#define YDC_DDR_BIST_CONFIG_2_RESERVED1_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG_2 :: FIFO_CMD_ALMOST_FULL_LEVEL [10:08] */
-#define YDC_DDR_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_MASK 0x00000700
-#define YDC_DDR_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_BITS 3
-#define YDC_DDR_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_SHIFT 8
-#define YDC_DDR_BIST_CONFIG_2_FIFO_CMD_ALMOST_FULL_LEVEL_DEFAULT 0x00000002
-
-/* YDC_DDR_BIST :: CONFIG_2 :: reserved2 [07:03] */
-#define YDC_DDR_BIST_CONFIG_2_RESERVED2_MASK 0x000000f8
-#define YDC_DDR_BIST_CONFIG_2_RESERVED2_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_RESERVED2_BITS 5
-#define YDC_DDR_BIST_CONFIG_2_RESERVED2_SHIFT 3
-#define YDC_DDR_BIST_CONFIG_2_RESERVED2_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIG_2 :: FIFO_WDATA_ALMOST_FULL_LEVEL [02:00] */
-#define YDC_DDR_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_MASK 0x00000007
-#define YDC_DDR_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_ALIGN 0
-#define YDC_DDR_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_BITS 3
-#define YDC_DDR_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_SHIFT 0
-#define YDC_DDR_BIST_CONFIG_2_FIFO_WDATA_ALMOST_FULL_LEVEL_DEFAULT 0x00000002
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: GENERAL_CONFIGURATIONS
- ***************************************************************************/
-/* YDC_DDR_BIST :: GENERAL_CONFIGURATIONS :: reserved0 [31:07] */
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED0_MASK 0xffffff80
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED0_BITS 25
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED0_SHIFT 7
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: GENERAL_CONFIGURATIONS :: NUM_COLS [06:04] */
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_MASK 0x00000070
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_ALIGN 0
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_BITS 3
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_SHIFT 4
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_NUM_COLS_DEFAULT 0x00000002
-
-/* YDC_DDR_BIST :: GENERAL_CONFIGURATIONS :: reserved1 [03:00] */
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED1_MASK 0x0000000f
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED1_ALIGN 0
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED1_BITS 4
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED1_SHIFT 0
-#define YDC_DDR_BIST_GENERAL_CONFIGURATIONS_RESERVED1_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: CONFIGURATIONS
- ***************************************************************************/
-/* YDC_DDR_BIST :: CONFIGURATIONS :: reserved0 [31:26] */
-#define YDC_DDR_BIST_CONFIGURATIONS_RESERVED0_MASK 0xfc000000
-#define YDC_DDR_BIST_CONFIGURATIONS_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_RESERVED0_BITS 6
-#define YDC_DDR_BIST_CONFIGURATIONS_RESERVED0_SHIFT 26
-#define YDC_DDR_BIST_CONFIGURATIONS_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: BIST_EN [25:25] */
-#define YDC_DDR_BIST_CONFIGURATIONS_BIST_EN_MASK 0x02000000
-#define YDC_DDR_BIST_CONFIGURATIONS_BIST_EN_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_BIST_EN_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_BIST_EN_SHIFT 25
-#define YDC_DDR_BIST_CONFIGURATIONS_BIST_EN_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: DATA_ADDR_MODE [24:24] */
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_ADDR_MODE_MASK 0x01000000
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_ADDR_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_ADDR_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_ADDR_MODE_SHIFT 24
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_ADDR_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: DATA_SHIFT_MODE [23:23] */
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_SHIFT_MODE_MASK 0x00800000
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_SHIFT_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_SHIFT_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_SHIFT_MODE_SHIFT 23
-#define YDC_DDR_BIST_CONFIGURATIONS_DATA_SHIFT_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: ADDRESS_SHIFT_MODE [22:22] */
-#define YDC_DDR_BIST_CONFIGURATIONS_ADDRESS_SHIFT_MODE_MASK 0x00400000
-#define YDC_DDR_BIST_CONFIGURATIONS_ADDRESS_SHIFT_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_ADDRESS_SHIFT_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_ADDRESS_SHIFT_MODE_SHIFT 22
-#define YDC_DDR_BIST_CONFIGURATIONS_ADDRESS_SHIFT_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: CONS_ADDR_8_BANKS [21:21] */
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_8_BANKS_MASK 0x00200000
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_8_BANKS_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_8_BANKS_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_8_BANKS_SHIFT 21
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_8_BANKS_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: CONS_ADDR_4_BANKS [20:20] */
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_4_BANKS_MASK 0x00100000
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_4_BANKS_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_4_BANKS_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_4_BANKS_SHIFT 20
-#define YDC_DDR_BIST_CONFIGURATIONS_CONS_ADDR_4_BANKS_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: IND_WR_RD_ADDR_MODE [19:19] */
-#define YDC_DDR_BIST_CONFIGURATIONS_IND_WR_RD_ADDR_MODE_MASK 0x00080000
-#define YDC_DDR_BIST_CONFIGURATIONS_IND_WR_RD_ADDR_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_IND_WR_RD_ADDR_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_IND_WR_RD_ADDR_MODE_SHIFT 19
-#define YDC_DDR_BIST_CONFIGURATIONS_IND_WR_RD_ADDR_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: PRBS_MODE [18:18] */
-#define YDC_DDR_BIST_CONFIGURATIONS_PRBS_MODE_MASK 0x00040000
-#define YDC_DDR_BIST_CONFIGURATIONS_PRBS_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_PRBS_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_PRBS_MODE_SHIFT 18
-#define YDC_DDR_BIST_CONFIGURATIONS_PRBS_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: TWO_ADDR_MODE [17:17] */
-#define YDC_DDR_BIST_CONFIGURATIONS_TWO_ADDR_MODE_MASK 0x00020000
-#define YDC_DDR_BIST_CONFIGURATIONS_TWO_ADDR_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_TWO_ADDR_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_TWO_ADDR_MODE_SHIFT 17
-#define YDC_DDR_BIST_CONFIGURATIONS_TWO_ADDR_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: PATTERN_BIT_MODE [16:16] */
-#define YDC_DDR_BIST_CONFIGURATIONS_PATTERN_BIT_MODE_MASK 0x00010000
-#define YDC_DDR_BIST_CONFIGURATIONS_PATTERN_BIT_MODE_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_PATTERN_BIT_MODE_BITS 1
-#define YDC_DDR_BIST_CONFIGURATIONS_PATTERN_BIT_MODE_SHIFT 16
-#define YDC_DDR_BIST_CONFIGURATIONS_PATTERN_BIT_MODE_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: READ_WEIGHT [15:08] */
-#define YDC_DDR_BIST_CONFIGURATIONS_READ_WEIGHT_MASK 0x0000ff00
-#define YDC_DDR_BIST_CONFIGURATIONS_READ_WEIGHT_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_READ_WEIGHT_BITS 8
-#define YDC_DDR_BIST_CONFIGURATIONS_READ_WEIGHT_SHIFT 8
-#define YDC_DDR_BIST_CONFIGURATIONS_READ_WEIGHT_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: CONFIGURATIONS :: WRITE_WEIGHT [07:00] */
-#define YDC_DDR_BIST_CONFIGURATIONS_WRITE_WEIGHT_MASK 0x000000ff
-#define YDC_DDR_BIST_CONFIGURATIONS_WRITE_WEIGHT_ALIGN 0
-#define YDC_DDR_BIST_CONFIGURATIONS_WRITE_WEIGHT_BITS 8
-#define YDC_DDR_BIST_CONFIGURATIONS_WRITE_WEIGHT_SHIFT 0
-#define YDC_DDR_BIST_CONFIGURATIONS_WRITE_WEIGHT_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: NUMBER_OF_ACTIONS
- ***************************************************************************/
-/* YDC_DDR_BIST :: NUMBER_OF_ACTIONS :: BIST_NUM_ACTIONS [31:00] */
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_MASK 0xffffffff
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_ALIGN 0
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_BITS 32
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_SHIFT 0
-#define YDC_DDR_BIST_NUMBER_OF_ACTIONS_BIST_NUM_ACTIONS_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: START_ADDRESS
- ***************************************************************************/
-/* YDC_DDR_BIST :: START_ADDRESS :: reserved0 [31:26] */
-#define YDC_DDR_BIST_START_ADDRESS_RESERVED0_MASK 0xfc000000
-#define YDC_DDR_BIST_START_ADDRESS_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_START_ADDRESS_RESERVED0_BITS 6
-#define YDC_DDR_BIST_START_ADDRESS_RESERVED0_SHIFT 26
-#define YDC_DDR_BIST_START_ADDRESS_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: START_ADDRESS :: BIST_START_ADDRESS [25:00] */
-#define YDC_DDR_BIST_START_ADDRESS_BIST_START_ADDRESS_MASK 0x03ffffff
-#define YDC_DDR_BIST_START_ADDRESS_BIST_START_ADDRESS_ALIGN 0
-#define YDC_DDR_BIST_START_ADDRESS_BIST_START_ADDRESS_BITS 26
-#define YDC_DDR_BIST_START_ADDRESS_BIST_START_ADDRESS_SHIFT 0
-#define YDC_DDR_BIST_START_ADDRESS_BIST_START_ADDRESS_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: END_ADDRESS
- ***************************************************************************/
-/* YDC_DDR_BIST :: END_ADDRESS :: reserved0 [31:26] */
-#define YDC_DDR_BIST_END_ADDRESS_RESERVED0_MASK 0xfc000000
-#define YDC_DDR_BIST_END_ADDRESS_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_END_ADDRESS_RESERVED0_BITS 6
-#define YDC_DDR_BIST_END_ADDRESS_RESERVED0_SHIFT 26
-#define YDC_DDR_BIST_END_ADDRESS_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: END_ADDRESS :: BIST_END_ADDRESS [25:00] */
-#define YDC_DDR_BIST_END_ADDRESS_BIST_END_ADDRESS_MASK 0x03ffffff
-#define YDC_DDR_BIST_END_ADDRESS_BIST_END_ADDRESS_ALIGN 0
-#define YDC_DDR_BIST_END_ADDRESS_BIST_END_ADDRESS_BITS 26
-#define YDC_DDR_BIST_END_ADDRESS_BIST_END_ADDRESS_SHIFT 0
-#define YDC_DDR_BIST_END_ADDRESS_BIST_END_ADDRESS_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: SINGLE_BIT_MASK
- ***************************************************************************/
-/* YDC_DDR_BIST :: SINGLE_BIT_MASK :: BIST_SINGLE_MASK [31:00] */
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_MASK 0xffffffff
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_ALIGN 0
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_BITS 32
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_SHIFT 0
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_BIST_SINGLE_MASK_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_7
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_7 :: BIST_PATTERN_7 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_7_BIST_PATTERN_7_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_7_BIST_PATTERN_7_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_7_BIST_PATTERN_7_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_7_BIST_PATTERN_7_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_7_BIST_PATTERN_7_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_6
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_6 :: BIST_PATTERN_6 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_6_BIST_PATTERN_6_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_6_BIST_PATTERN_6_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_6_BIST_PATTERN_6_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_6_BIST_PATTERN_6_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_6_BIST_PATTERN_6_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_5
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_5 :: BIST_PATTERN_5 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_5_BIST_PATTERN_5_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_5_BIST_PATTERN_5_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_5_BIST_PATTERN_5_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_5_BIST_PATTERN_5_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_5_BIST_PATTERN_5_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_4
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_4 :: BIST_PATTERN_4 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_4_BIST_PATTERN_4_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_4_BIST_PATTERN_4_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_4_BIST_PATTERN_4_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_4_BIST_PATTERN_4_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_4_BIST_PATTERN_4_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_3
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_3 :: BIST_PATTERN_3 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_3_BIST_PATTERN_3_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_3_BIST_PATTERN_3_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_3_BIST_PATTERN_3_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_3_BIST_PATTERN_3_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_3_BIST_PATTERN_3_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_2
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_2 :: BIST_PATTERN_2 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_2_BIST_PATTERN_2_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_2_BIST_PATTERN_2_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_2_BIST_PATTERN_2_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_2_BIST_PATTERN_2_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_2_BIST_PATTERN_2_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_1
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_1 :: BIST_PATTERN_1 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_1_BIST_PATTERN_1_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_1_BIST_PATTERN_1_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_1_BIST_PATTERN_1_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_1_BIST_PATTERN_1_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_1_BIST_PATTERN_1_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: PATTERN_WORD_0
- ***************************************************************************/
-/* YDC_DDR_BIST :: PATTERN_WORD_0 :: BIST_PATTERN_0 [31:00] */
-#define YDC_DDR_BIST_PATTERN_WORD_0_BIST_PATTERN_0_MASK 0xffffffff
-#define YDC_DDR_BIST_PATTERN_WORD_0_BIST_PATTERN_0_ALIGN 0
-#define YDC_DDR_BIST_PATTERN_WORD_0_BIST_PATTERN_0_BITS 32
-#define YDC_DDR_BIST_PATTERN_WORD_0_BIST_PATTERN_0_SHIFT 0
-#define YDC_DDR_BIST_PATTERN_WORD_0_BIST_PATTERN_0_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_7
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_7 :: BIST_FULL_MASK_7 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_7_BIST_FULL_MASK_7_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_6
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_6 :: BIST_FULL_MASK_6 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_6_BIST_FULL_MASK_6_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_5
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_5 :: BIST_FULL_MASK_5 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_5_BIST_FULL_MASK_5_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_4
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_4 :: BIST_FULL_MASK_4 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_4_BIST_FULL_MASK_4_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_3
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_3 :: BIST_FULL_MASK_3 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_3_BIST_FULL_MASK_3_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_2
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_2 :: BIST_FULL_MASK_2 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_2_BIST_FULL_MASK_2_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_1
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_1 :: BIST_FULL_MASK_1 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_1_BIST_FULL_MASK_1_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_WORD_0
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_WORD_0 :: BIST_FULL_MASK_0 [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_WORD_0_BIST_FULL_MASK_0_DEFAULT 0xffffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: STATUSES
- ***************************************************************************/
-/* YDC_DDR_BIST :: STATUSES :: reserved0 [31:04] */
-#define YDC_DDR_BIST_STATUSES_RESERVED0_MASK 0xfffffff0
-#define YDC_DDR_BIST_STATUSES_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_STATUSES_RESERVED0_BITS 28
-#define YDC_DDR_BIST_STATUSES_RESERVED0_SHIFT 4
-#define YDC_DDR_BIST_STATUSES_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: STATUSES :: OVERFLOW_FIFO_RADDR [03:03] */
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_RADDR_MASK 0x00000008
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_RADDR_ALIGN 0
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_RADDR_BITS 1
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_RADDR_SHIFT 3
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_RADDR_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: STATUSES :: OVERFLOW_FIFO_CMD [02:02] */
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_CMD_MASK 0x00000004
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_CMD_ALIGN 0
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_CMD_BITS 1
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_CMD_SHIFT 2
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_CMD_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: STATUSES :: OVERFLOW_FIFO_WDATA [01:01] */
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_WDATA_MASK 0x00000002
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_WDATA_ALIGN 0
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_WDATA_BITS 1
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_WDATA_SHIFT 1
-#define YDC_DDR_BIST_STATUSES_OVERFLOW_FIFO_WDATA_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: STATUSES :: BIST_FINISHED [00:00] */
-#define YDC_DDR_BIST_STATUSES_BIST_FINISHED_MASK 0x00000001
-#define YDC_DDR_BIST_STATUSES_BIST_FINISHED_ALIGN 0
-#define YDC_DDR_BIST_STATUSES_BIST_FINISHED_BITS 1
-#define YDC_DDR_BIST_STATUSES_BIST_FINISHED_SHIFT 0
-#define YDC_DDR_BIST_STATUSES_BIST_FINISHED_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: FULL_MASK_ERROR_COUNTER
- ***************************************************************************/
-/* YDC_DDR_BIST :: FULL_MASK_ERROR_COUNTER :: FULL_ERR_CNT [31:00] */
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_MASK 0xffffffff
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_ALIGN 0
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_BITS 32
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_SHIFT 0
-#define YDC_DDR_BIST_FULL_MASK_ERROR_COUNTER_FULL_ERR_CNT_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: SINGLE_BIT_MASK_ERROR_COUNTER
- ***************************************************************************/
-/* YDC_DDR_BIST :: SINGLE_BIT_MASK_ERROR_COUNTER :: SINGLE_ERR_CNT [31:00] */
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_MASK 0xffffffff
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_ALIGN 0
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_BITS 32
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_SHIFT 0
-#define YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTER_SINGLE_ERR_CNT_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: ERROR_OCCURRED
- ***************************************************************************/
-/* YDC_DDR_BIST :: ERROR_OCCURRED :: ERR_OCCURRED [31:00] */
-#define YDC_DDR_BIST_ERROR_OCCURRED_ERR_OCCURRED_MASK 0xffffffff
-#define YDC_DDR_BIST_ERROR_OCCURRED_ERR_OCCURRED_ALIGN 0
-#define YDC_DDR_BIST_ERROR_OCCURRED_ERR_OCCURRED_BITS 32
-#define YDC_DDR_BIST_ERROR_OCCURRED_ERR_OCCURRED_SHIFT 0
-#define YDC_DDR_BIST_ERROR_OCCURRED_ERR_OCCURRED_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: GLOBAL_ERROR_COUNTER
- ***************************************************************************/
-/* YDC_DDR_BIST :: GLOBAL_ERROR_COUNTER :: GLOBAL_ERR_CNT [31:00] */
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_MASK 0xffffffff
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_ALIGN 0
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_BITS 32
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_SHIFT 0
-#define YDC_DDR_BIST_GLOBAL_ERROR_COUNTER_GLOBAL_ERR_CNT_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_ADDR_ERR
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_ADDR_ERR :: reserved0 [31:26] */
-#define YDC_DDR_BIST_LAST_ADDR_ERR_RESERVED0_MASK 0xfc000000
-#define YDC_DDR_BIST_LAST_ADDR_ERR_RESERVED0_ALIGN 0
-#define YDC_DDR_BIST_LAST_ADDR_ERR_RESERVED0_BITS 6
-#define YDC_DDR_BIST_LAST_ADDR_ERR_RESERVED0_SHIFT 26
-#define YDC_DDR_BIST_LAST_ADDR_ERR_RESERVED0_DEFAULT 0x00000000
-
-/* YDC_DDR_BIST :: LAST_ADDR_ERR :: BIST_LAST_ADDR_ERR [25:00] */
-#define YDC_DDR_BIST_LAST_ADDR_ERR_BIST_LAST_ADDR_ERR_MASK 0x03ffffff
-#define YDC_DDR_BIST_LAST_ADDR_ERR_BIST_LAST_ADDR_ERR_ALIGN 0
-#define YDC_DDR_BIST_LAST_ADDR_ERR_BIST_LAST_ADDR_ERR_BITS 26
-#define YDC_DDR_BIST_LAST_ADDR_ERR_BIST_LAST_ADDR_ERR_SHIFT 0
-#define YDC_DDR_BIST_LAST_ADDR_ERR_BIST_LAST_ADDR_ERR_DEFAULT 0x03ffffff
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_7
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_7 :: BIST_LAST_DATA_ERR_7 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7_BIST_LAST_DATA_ERR_7_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7_BIST_LAST_DATA_ERR_7_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7_BIST_LAST_DATA_ERR_7_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7_BIST_LAST_DATA_ERR_7_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_7_BIST_LAST_DATA_ERR_7_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_6
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_6 :: BIST_LAST_DATA_ERR_6 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6_BIST_LAST_DATA_ERR_6_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6_BIST_LAST_DATA_ERR_6_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6_BIST_LAST_DATA_ERR_6_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6_BIST_LAST_DATA_ERR_6_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_6_BIST_LAST_DATA_ERR_6_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_5
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_5 :: BIST_LAST_DATA_ERR_5 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5_BIST_LAST_DATA_ERR_5_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5_BIST_LAST_DATA_ERR_5_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5_BIST_LAST_DATA_ERR_5_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5_BIST_LAST_DATA_ERR_5_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_5_BIST_LAST_DATA_ERR_5_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_4
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_4 :: BIST_LAST_DATA_ERR_4 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4_BIST_LAST_DATA_ERR_4_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4_BIST_LAST_DATA_ERR_4_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4_BIST_LAST_DATA_ERR_4_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4_BIST_LAST_DATA_ERR_4_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_4_BIST_LAST_DATA_ERR_4_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_3
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_3 :: BIST_LAST_DATA_ERR_3 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3_BIST_LAST_DATA_ERR_3_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3_BIST_LAST_DATA_ERR_3_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3_BIST_LAST_DATA_ERR_3_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3_BIST_LAST_DATA_ERR_3_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_3_BIST_LAST_DATA_ERR_3_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_2
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_2 :: BIST_LAST_DATA_ERR_2 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2_BIST_LAST_DATA_ERR_2_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2_BIST_LAST_DATA_ERR_2_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2_BIST_LAST_DATA_ERR_2_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2_BIST_LAST_DATA_ERR_2_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_2_BIST_LAST_DATA_ERR_2_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_1
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_1 :: BIST_LAST_DATA_ERR_1 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1_BIST_LAST_DATA_ERR_1_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1_BIST_LAST_DATA_ERR_1_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1_BIST_LAST_DATA_ERR_1_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1_BIST_LAST_DATA_ERR_1_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_1_BIST_LAST_DATA_ERR_1_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * YDC_DDR_BIST :: LAST_DATA_ERR_WORD_0
- ***************************************************************************/
-/* YDC_DDR_BIST :: LAST_DATA_ERR_WORD_0 :: BIST_LAST_DATA_ERR_0 [31:00] */
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0_BIST_LAST_DATA_ERR_0_MASK 0xffffffff
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0_BIST_LAST_DATA_ERR_0_ALIGN 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0_BIST_LAST_DATA_ERR_0_BITS 32
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0_BIST_LAST_DATA_ERR_0_SHIFT 0
-#define YDC_DDR_BIST_LAST_DATA_ERR_WORD_0_BIST_LAST_DATA_ERR_0_DEFAULT 0x00000000
-
-
-/****************************************************************************
- * Datatype Definitions.
- ***************************************************************************/
-#endif /* __SOC_BROADCOM_CYGNUS_YDC_DDR_BIST_H__ */
-
-/* End of File */
diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h
deleted file mode 100644
index 1d5d234..0000000
--- a/src/soc/broadcom/cygnus/include/soc/tz.h
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_TZ_H__
-#define __SOC_BROADCOM_CYGNUS_TZ_H__
-
-#include <stdint.h>
-
-#define TZ_STATE_SECURE 0
-#define TZ_STATE_NON_SECURE 1
-
-/*
- * Masters (for parameter masters in "tz_set_masters_security")
- */
-#define CYGNUS_M_Pcie0_m0 0x00000003
-#define CYGNUS_M_Pcie1_m0 0x0000000c
-#define CYGNUS_M_cmicd_m0 0x00000030
-#define CYGNUS_M_ext_m0 0x000000c0
-
-#define CYGNUS_M_ext_m1 (0x00000003 << 8)
-#define CYGNUS_M_sdio_m0 (0x0000000c << 8)
-#define CYGNUS_M_sdio_m1 (0x00000030 << 8)
-#define CYGNUS_M_amac_m0 (0x000000c0 << 8)
-
-#define CYGNUS_M_amac_m1 (0x00000003 << 16)
-#define CYGNUS_M_usb2h_m0 (0x0000000c << 16)
-#define CYGNUS_M_usb2d_m0 (0x00000030 << 16)
-#define CYGNUS_M_a9jtag_m0 (0x000000c0 << 16)
-
-/*
- * Non virtual slaves (for parameter slave_vector in "tz_set_non_virtual_slaves_security")
- * Note: the order has to match the order in non_virtual_slave_regs[] array from tz.c
- */
-#define CYGNUS_S_Ihost_acp (0x1 << 0)
-#define CYGNUS_S_PCIe0_s0 (0x1 << 1)
-#define CYGNUS_S_PCIe1_s0 (0x1 << 2)
-#define CYGNUS_S_ihost_s0 (0x1 << 3)
-#define CYGNUS_S_A9jtag_s0 (0x1 << 4)
-#define CYGNUS_S_CMICd_s0 (0x1 << 5)
-#define CYGNUS_S_mhost0_s0 (0x1 << 6)
-#define CYGNUS_S_mhost1_s0 (0x1 << 7)
-#define CYGNUS_S_Crypto_s0 (0x1 << 8)
-#define CYGNUS_S_DMU_s0 (0x1 << 9)
-
-/*
- * Peripherals (for parameter slave_vector in "tz_set_periph_security")
- */
-#define CYGNUS_periph_APBx_DMU 0x00008000
-#define CYGNUS_periph_APBx_cru 0x00004000
-#define CYGNUS_periph_APBx_ccg_smbus1 0x00000800
-#define CYGNUS_periph_APBx_ccg_gpio 0x00000400
-#define CYGNUS_periph_APBx_ccg_watchdog 0x00000200
-#define CYGNUS_periph_APBx_ccg_smbus0 0x00000100
-#define CYGNUS_periph_APBx_ccg_srab 0x00000080
-#define CYGNUS_periph_APBx_ccg_timer3 0x00000040
-#define CYGNUS_periph_APBx_ccg_timer2 0x00000020
-#define CYGNUS_periph_APBx_ccg_timer1 0x00000010
-#define CYGNUS_periph_APBx_ccg_timer0 0x00000008
-#define CYGNUS_periph_APBx_ccg_mdio 0x00000004
-#define CYGNUS_periph_APBx_ccg_pwm 0x00000002
-#define CYGNUS_periph_APBx_icfg 0x00000001
-
-#define CYGNUS_periph_APBy_ccg_spi5 (0x00002000 << 16)
-#define CYGNUS_periph_APBy_ccg_spi4 (0x00001000 << 16)
-#define CYGNUS_periph_APBy_ccg_spi3 (0x00000800 << 16)
-#define CYGNUS_periph_APBy_ccg_spi2 (0x00000400 << 16)
-#define CYGNUS_periph_APBy_ccg_spi1 (0x00000200 << 16)
-#define CYGNUS_periph_APBy_ccg_spi0 (0x00000100 << 16)
-#define CYGNUS_periph_APBy_ccg_uart4 (0x00000010 << 16)
-#define CYGNUS_periph_APBy_ccg_uart3 (0x00000008 << 16)
-#define CYGNUS_periph_APBy_ccg_uart2 (0x00000004 << 16)
-#define CYGNUS_periph_APBy_ccg_uart1 (0x00000002 << 16)
-#define CYGNUS_periph_APBy_ccg_uart0 (0x00000001 << 16)
-
-/*
- * Sececure Peripherals (for parameter slave_vector in "tz_set_sec_periphs_security")
- */
-#define CYGNUS_sec_periph_APBz_sotp 0x00000020
-#define CYGNUS_sec_periph_APBz_tzpc 0x00000010
-#define CYGNUS_sec_periph_APBz_ccg_wdog 0x00000008
-#define CYGNUS_sec_periph_APBz_ccs_rng 0x00000004
-#define CYGNUS_sec_periph_APBz_ccs_pka 0x00000002
-#define CYGNUS_sec_periph_APBz_ccs_gpio 0x00000001
-
-/*
- * Cfg Slaves (for parameter slave_vector in "tz_set_cfg_slaves_security")
- */
-#define CYGNUS_cfg_slv_APBr_mhost0 0x00004000
-#define CYGNUS_cfg_slv_APBr_dma_s1 0x00000200
-#define CYGNUS_cfg_slv_APBr_dma_s0 0x00000100
-#define CYGNUS_cfg_slv_APBr_acpal 0x00000040
-#define CYGNUS_cfg_slv_APBr_smau 0x00000020
-#define CYGNUS_cfg_slv_APBr_pcie1 0x00000008
-#define CYGNUS_cfg_slv_APBr_pcie0 0x00000004
-#define CYGNUS_cfg_slv_APBr_ddr 0x00000001
-
-#define CYGNUS_cfg_slv_APBs_sram (0x00004000 << 16)
-#define CYGNUS_cfg_slv_APBs_usb2d (0x00001000 << 16)
-#define CYGNUS_cfg_slv_APBs_amac1 (0x00000400 << 16)
-#define CYGNUS_cfg_slv_APBs_usb2h_apb2 (0x00000200 << 16)
-#define CYGNUS_cfg_slv_APBs_usb2h_apb1 (0x00000100 << 16)
-#define CYGNUS_cfg_slv_APBs_qspi (0x00000080 << 16)
-#define CYGNUS_cfg_slv_APBs_nand (0x00000040 << 16)
-#define CYGNUS_cfg_slv_APBs_nor (0x00000020 << 16)
-#define CYGNUS_cfg_slv_APBs_sdio1 (0x00000008 << 16)
-#define CYGNUS_cfg_slv_APBs_amac0 (0x00000004 << 16)
-#define CYGNUS_cfg_slv_APBs_sdio0 (0x00000002 << 16)
-
-/*
- * Wrapper1 (for parameter wrapper1 in "tz_set_wrapper_security")
- */
-#define CYGNUS_APB_W1_wrp_master_ihost_m0 0x00000001
-#define CYGNUS_APB_W1_wrp_master_pcie0_m0 0x00000002
-#define CYGNUS_APB_W1_wrp_master_pcie1_m0 0x00000004
-#define CYGNUS_APB_W1_wrp_master_cmicd_m0 0x00000008
-#define CYGNUS_APB_W1_wrp_master_mhost0_m0 0x00000010
-#define CYGNUS_APB_W1_wrp_master_mhost1_m0 0x00000020
-#define CYGNUS_APB_W1_wrp_slave_ihost_acp 0x00000040
-#define CYGNUS_APB_W1_wrp_slave_ihost_s0 0x00000080
-#define CYGNUS_APB_W1_wrp_slave_pcie0_s0 0x00000100
-#define CYGNUS_APB_W1_wrp_slave_pcie1_s0 0x00000200
-#define CYGNUS_APB_W1_wrp_slave_cmicd_s0 0x00000400
-#define CYGNUS_APB_W1_wrp_slave_smau_s0 0x00000800
-#define CYGNUS_APB_W1_wrp_slave_mhost0_s0 0x00001000
-#define CYGNUS_APB_W1_wrp_slave_mhost1_s0 0x00002000
-#define CYGNUS_APB_W1_wrp_slave_apbr 0x00004000
-#define CYGNUS_APB_W1_wrp_master_dma_m0 0x00008000
-
-/*
- * Wrapper2 (for parameter wrapper2 in "tz_set_wrapper_security")
- */
-#define CYGNUS_APB_W2_wrp_ds_ds_2 0x00000008
-#define CYGNUS_APB_W2_sdrom 0x00000004
-#define CYGNUS_APB_W2_wrp_ds_ds_1 0x00000002
-#define CYGNUS_APB_W2_wrp_ds_ds_0 0x00000001
-
-/*
- * Wrapper3 (for parameter wrapper3 in "tz_set_wrapper_security")
- */
-#define CYGNUS_APB_W3_wrp_master_amac_m1 0x00002000
-#define CYGNUS_APB_W3_wrp_ds_ds_3 0x00001000
-#define CYGNUS_APB_W3_wrp_slave_apbs 0x00000800
-#define CYGNUS_APB_W3_wrp_slave_sram_s0 0x00000400
-#define CYGNUS_APB_W3_wrp_master_sdio_m1 0x00000200
-#define CYGNUS_APB_W3_wrp_slave_a9jtag_s0 0x00000100
-#define CYGNUS_APB_W3_wrp_slave_crypto_s0 0x00000080
-#define CYGNUS_APB_W3_wrp_master_usb2h_m0 0x00000040
-#define CYGNUS_APB_W3_wrp_master_a9jtag_m0 0x00000020
-#define CYGNUS_APB_W3_wrp_master_ext_m1 0x00000010
-#define CYGNUS_APB_W3_wrp_master_sdio_m0 0x00000008
-#define CYGNUS_APB_W3_wrp_master_ext_m0 0x00000004
-#define CYGNUS_APB_W3_wrp_master_usb2d_m0 0x00000002
-#define CYGNUS_APB_W3_wrp_master_amac_m0 0x00000001
-
-/*
- * Wrapper4 (for parameter wrapper4 in "tz_set_wrapper_security")
- */
-#define CYGNUS_APB_W4_wrp_slave_ext_s1 0x00000040
-#define CYGNUS_APB_W4_wrp_slave_dmu_s0 0x00000020
-#define CYGNUS_APB_W4_wrp_slave_ext_s0 0x00000010
-#define CYGNUS_APB_W4_wrp_master_dmu_m0 0x00000008
-#define CYGNUS_APB_W4_wrp_slave_apbz 0x00000004
-#define CYGNUS_APB_W4_wrp_slave_apby 0x00000002
-#define CYGNUS_APB_W4_wrp_slave_apbx 0x00000001
-
-/*
- * Ext Slaves (for parameter slave_vector in "tz_set_ext_slaves_security")
- */
-#define CYGNUS_AXIIC_ext_s0_slave_0 0x00000001 /* LCD */
-#define CYGNUS_AXIIC_ext_s0_slave_1 0x00000002 /* Camera */
-#define CYGNUS_AXIIC_ext_s0_slave_2 0x00000004
-#define CYGNUS_AXIIC_ext_s0_slave_3 0x00000008 /* Smartcard */
-#define CYGNUS_AXIIC_ext_s0_slave_4 0x00000010 /* S-GPIO */
-#define CYGNUS_AXIIC_ext_s0_slave_5 0x00000020 /* GPIO */
-#define CYGNUS_AXIIC_ext_s0_slave_6 0x00000040 /* ADC_APB */
-#define CYGNUS_AXIIC_ext_s0_slave_7 0x00000080
-#define CYGNUS_AXIIC_ext_s0_slave_8 0x00000100 /* GFX_S0 */
-#define CYGNUS_AXIIC_ext_s0_slave_9 0x00000200 /* MIPI */
-#define CYGNUS_AXIIC_ext_s0_slave_10 0x00000400 /* ASIU_TOP */
-#define CYGNUS_AXIIC_ext_s0_slave_11 0x00000800 /* D1W */
-#define CYGNUS_AXIIC_ext_s0_slave_12 0x00001000 /* Keypad */
-#define CYGNUS_AXIIC_ext_s0_slave_13 0x00002000 /* Keypad */
-#define CYGNUS_AXIIC_ext_s0_slave_14 0x00004000 /* Audio */
-#define CYGNUS_AXIIC_ext_s0_slave_15 0x00008000
-
-#define CYGNUS_AXIIC_ext_s1_slave_0 (0x00000001 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_1 (0x00000002 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_2 (0x00000004 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_3 (0x00000008 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_4 (0x00000010 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_5 (0x00000020 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_6 (0x00000040 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_7 (0x00000080 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_8 (0x00000100 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_9 (0x00000200 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_10 (0x00000400 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_11 (0x00000800 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_12 (0x00001000 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_13 (0x00002000 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_14 (0x00004000 << 16)
-#define CYGNUS_AXIIC_ext_s1_slave_15 (0x00008000 << 16)
-
-void tz_set_masters_security(uint32_t masters, uint32_t ns_bit);
-void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2,
- uint32_t wrapper3, uint32_t wrapper4,
- uint32_t ns_bit);
-void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
-void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit);
-void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit);
-void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
-void tz_set_sram_sec_region(uint32_t r0size);
-void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit);
-
-#endif
diff --git a/src/soc/broadcom/cygnus/iomux.c b/src/soc/broadcom/cygnus/iomux.c
deleted file mode 100644
index f684def..0000000
--- a/src/soc/broadcom/cygnus/iomux.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <soc/addressmap.h>
-
-#define CYGNUS_NUM_IOMUX_REGS 8
-#define CYGNUS_NUM_MUX_PER_REG 8
-#define CYGNUS_NUM_IOMUX (CYGNUS_NUM_IOMUX_REGS * \
- CYGNUS_NUM_MUX_PER_REG)
-
-/*
- * Cygnus IOMUX pinctrl core
- *
- * @base1: second I/O register base
- */
-struct cygnus_pinctrl {
- void *base1;
-};
-
-static struct cygnus_pinctrl pinctrl_data = {
- .base1 = (void *)IPROC_IOMUX_OVERRIDE_BASE
-};
-
-/*
- * Certain pins can be individually muxed to GPIO function
- *
- * @is_supported: flag to indicate GPIO mux is supported for this pin
- * @offset: register offset for GPIO mux override of a pin
- * @shift: bit shift for GPIO mux override of a pin
- */
-struct cygnus_gpio_mux {
- int is_supported;
- unsigned int offset;
- unsigned int shift;
-};
-
-/*
- * Description of a pin in Cygnus
- *
- * @pin: pin number
- * @name: pin name
- * @gpio_mux: GPIO override related information
- */
-struct cygnus_pin {
- unsigned pin;
- const char *name;
- struct cygnus_gpio_mux gpio_mux;
-};
-
-#define CYGNUS_PIN_DESC(p, n, i, o, s) \
-{ \
- .pin = p, \
- .name = n, \
- .gpio_mux = { \
- .is_supported = i, \
- .offset = o, \
- .shift = s, \
- }, \
-}
-
-/*
- * List of pins in Cygnus
- */
-static struct cygnus_pin cygnus_pins[] = {
- CYGNUS_PIN_DESC(0, "ext_device_reset_n", 0, 0, 0),
- CYGNUS_PIN_DESC(1, "chip_mode0", 0, 0, 0),
- CYGNUS_PIN_DESC(2, "chip_mode1", 0, 0, 0),
- CYGNUS_PIN_DESC(3, "chip_mode2", 0, 0, 0),
- CYGNUS_PIN_DESC(4, "chip_mode3", 0, 0, 0),
- CYGNUS_PIN_DESC(5, "chip_mode4", 0, 0, 0),
- CYGNUS_PIN_DESC(6, "bsc0_scl", 0, 0, 0),
- CYGNUS_PIN_DESC(7, "bsc0_sda", 0, 0, 0),
- CYGNUS_PIN_DESC(8, "bsc1_scl", 0, 0, 0),
- CYGNUS_PIN_DESC(9, "bsc1_sda", 0, 0, 0),
- CYGNUS_PIN_DESC(10, "d1w_dq", 1, 0x28, 0),
- CYGNUS_PIN_DESC(11, "d1wowstz_l", 1, 0x4, 28),
- CYGNUS_PIN_DESC(12, "gpio0", 0, 0, 0),
- CYGNUS_PIN_DESC(13, "gpio1", 0, 0, 0),
- CYGNUS_PIN_DESC(14, "gpio2", 0, 0, 0),
- CYGNUS_PIN_DESC(15, "gpio3", 0, 0, 0),
- CYGNUS_PIN_DESC(16, "gpio4", 0, 0, 0),
- CYGNUS_PIN_DESC(17, "gpio5", 0, 0, 0),
- CYGNUS_PIN_DESC(18, "gpio6", 0, 0, 0),
- CYGNUS_PIN_DESC(19, "gpio7", 0, 0, 0),
- CYGNUS_PIN_DESC(20, "gpio8", 0, 0, 0),
- CYGNUS_PIN_DESC(21, "gpio9", 0, 0, 0),
- CYGNUS_PIN_DESC(22, "gpio10", 0, 0, 0),
- CYGNUS_PIN_DESC(23, "gpio11", 0, 0, 0),
- CYGNUS_PIN_DESC(24, "gpio12", 0, 0, 0),
- CYGNUS_PIN_DESC(25, "gpio13", 0, 0, 0),
- CYGNUS_PIN_DESC(26, "gpio14", 0, 0, 0),
- CYGNUS_PIN_DESC(27, "gpio15", 0, 0, 0),
- CYGNUS_PIN_DESC(28, "gpio16", 0, 0, 0),
- CYGNUS_PIN_DESC(29, "gpio17", 0, 0, 0),
- CYGNUS_PIN_DESC(30, "gpio18", 0, 0, 0),
- CYGNUS_PIN_DESC(31, "gpio19", 0, 0, 0),
- CYGNUS_PIN_DESC(32, "gpio20", 0, 0, 0),
- CYGNUS_PIN_DESC(33, "gpio21", 0, 0, 0),
- CYGNUS_PIN_DESC(34, "gpio22", 0, 0, 0),
- CYGNUS_PIN_DESC(35, "gpio23", 0, 0, 0),
- CYGNUS_PIN_DESC(36, "mdc", 0, 0, 0),
- CYGNUS_PIN_DESC(37, "mdio", 0, 0, 0),
- CYGNUS_PIN_DESC(38, "pwm0", 1, 0x10, 30),
- CYGNUS_PIN_DESC(39, "pwm1", 1, 0x10, 28),
- CYGNUS_PIN_DESC(40, "pwm2", 1, 0x10, 26),
- CYGNUS_PIN_DESC(41, "pwm3", 1, 0x10, 24),
- CYGNUS_PIN_DESC(42, "sc0_clk", 1, 0x10, 22),
- CYGNUS_PIN_DESC(43, "sc0_cmdvcc_l", 1, 0x10, 20),
- CYGNUS_PIN_DESC(44, "sc0_detect", 1, 0x10, 18),
- CYGNUS_PIN_DESC(45, "sc0_fcb", 1, 0x10, 16),
- CYGNUS_PIN_DESC(46, "sc0_io", 1, 0x10, 14),
- CYGNUS_PIN_DESC(47, "sc0_rst_l", 1, 0x10, 12),
- CYGNUS_PIN_DESC(48, "sc1_clk", 1, 0x10, 10),
- CYGNUS_PIN_DESC(49, "sc1_cmdvcc_l", 1, 0x10, 8),
- CYGNUS_PIN_DESC(50, "sc1_detect", 1, 0x10, 6),
- CYGNUS_PIN_DESC(51, "sc1_fcb", 1, 0x10, 4),
- CYGNUS_PIN_DESC(52, "sc1_io", 1, 0x10, 2),
- CYGNUS_PIN_DESC(53, "sc1_rst_l", 1, 0x10, 0),
- CYGNUS_PIN_DESC(54, "spi0_clk", 1, 0x18, 10),
- CYGNUS_PIN_DESC(55, "spi0_mosi", 1, 0x18, 6),
- CYGNUS_PIN_DESC(56, "spi0_miso", 1, 0x18, 8),
- CYGNUS_PIN_DESC(57, "spi0_ss", 1, 0x18, 4),
- CYGNUS_PIN_DESC(58, "spi1_clk", 1, 0x18, 2),
- CYGNUS_PIN_DESC(59, "spi1_mosi", 1, 0x1c, 30),
- CYGNUS_PIN_DESC(60, "spi1_miso", 1, 0x18, 0),
- CYGNUS_PIN_DESC(61, "spi1_ss", 1, 0x1c, 28),
- CYGNUS_PIN_DESC(62, "spi2_clk", 1, 0x1c, 26),
- CYGNUS_PIN_DESC(63, "spi2_mosi", 1, 0x1c, 22),
- CYGNUS_PIN_DESC(64, "spi2_miso", 1, 0x1c, 24),
- CYGNUS_PIN_DESC(65, "spi2_ss", 1, 0x1c, 20),
- CYGNUS_PIN_DESC(66, "spi3_clk", 1, 0x1c, 18),
- CYGNUS_PIN_DESC(67, "spi3_mosi", 1, 0x1c, 14),
- CYGNUS_PIN_DESC(68, "spi3_miso", 1, 0x1c, 16),
- CYGNUS_PIN_DESC(69, "spi3_ss", 1, 0x1c, 12),
- CYGNUS_PIN_DESC(70, "uart0_cts", 1, 0x1c, 10),
- CYGNUS_PIN_DESC(71, "uart0_rts", 1, 0x1c, 8),
- CYGNUS_PIN_DESC(72, "uart0_rx", 1, 0x1c, 6),
- CYGNUS_PIN_DESC(73, "uart0_tx", 1, 0x1c, 4),
- CYGNUS_PIN_DESC(74, "uart1_cts", 1, 0x1c, 2),
- CYGNUS_PIN_DESC(75, "uart1_dcd", 1, 0x1c, 0),
- CYGNUS_PIN_DESC(76, "uart1_dsr", 1, 0x20, 14),
- CYGNUS_PIN_DESC(77, "uart1_dtr", 1, 0x20, 12),
- CYGNUS_PIN_DESC(78, "uart1_ri", 1, 0x20, 10),
- CYGNUS_PIN_DESC(79, "uart1_rts", 1, 0x20, 8),
- CYGNUS_PIN_DESC(80, "uart1_rx", 1, 0x20, 6),
- CYGNUS_PIN_DESC(81, "uart1_tx", 1, 0x20, 4),
- CYGNUS_PIN_DESC(82, "uart3_rx", 1, 0x20, 2),
- CYGNUS_PIN_DESC(83, "uart3_tx", 1, 0x20, 0),
- CYGNUS_PIN_DESC(84, "sdio1_clk_sdcard", 1, 0x14, 6),
- CYGNUS_PIN_DESC(85, "sdio1_cmd", 1, 0x14, 4),
- CYGNUS_PIN_DESC(86, "sdio1_data0", 1, 0x14, 2),
- CYGNUS_PIN_DESC(87, "sdio1_data1", 1, 0x14, 0),
- CYGNUS_PIN_DESC(88, "sdio1_data2", 1, 0x18, 30),
- CYGNUS_PIN_DESC(89, "sdio1_data3", 1, 0x18, 28),
- CYGNUS_PIN_DESC(90, "sdio1_wp_n", 1, 0x18, 24),
- CYGNUS_PIN_DESC(91, "sdio1_card_rst", 1, 0x14, 10),
- CYGNUS_PIN_DESC(92, "sdio1_led_on", 1, 0x18, 26),
- CYGNUS_PIN_DESC(93, "sdio1_cd", 1, 0x14, 8),
- CYGNUS_PIN_DESC(94, "sdio0_clk_sdcard", 1, 0x14, 26),
- CYGNUS_PIN_DESC(95, "sdio0_cmd", 1, 0x14, 24),
- CYGNUS_PIN_DESC(96, "sdio0_data0", 1, 0x14, 22),
- CYGNUS_PIN_DESC(97, "sdio0_data1", 1, 0x14, 20),
- CYGNUS_PIN_DESC(98, "sdio0_data2", 1, 0x14, 18),
- CYGNUS_PIN_DESC(99, "sdio0_data3", 1, 0x14, 16),
- CYGNUS_PIN_DESC(100, "sdio0_wp_n", 1, 0x14, 12),
- CYGNUS_PIN_DESC(101, "sdio0_card_rst", 1, 0x14, 30),
- CYGNUS_PIN_DESC(102, "sdio0_led_on", 1, 0x14, 14),
- CYGNUS_PIN_DESC(103, "sdio0_cd", 1, 0x14, 28),
- CYGNUS_PIN_DESC(104, "sflash_clk", 1, 0x18, 22),
- CYGNUS_PIN_DESC(105, "sflash_cs_l", 1, 0x18, 20),
- CYGNUS_PIN_DESC(106, "sflash_mosi", 1, 0x18, 14),
- CYGNUS_PIN_DESC(107, "sflash_miso", 1, 0x18, 16),
- CYGNUS_PIN_DESC(108, "sflash_wp_n", 1, 0x18, 12),
- CYGNUS_PIN_DESC(109, "sflash_hold_n", 1, 0x18, 18),
- CYGNUS_PIN_DESC(110, "nand_ale", 1, 0xc, 30),
- CYGNUS_PIN_DESC(111, "nand_ce0_l", 1, 0xc, 28),
- CYGNUS_PIN_DESC(112, "nand_ce1_l", 1, 0xc, 26),
- CYGNUS_PIN_DESC(113, "nand_cle", 1, 0xc, 24),
- CYGNUS_PIN_DESC(114, "nand_dq0", 1, 0xc, 22),
- CYGNUS_PIN_DESC(115, "nand_dq1", 1, 0xc, 20),
- CYGNUS_PIN_DESC(116, "nand_dq2", 1, 0xc, 18),
- CYGNUS_PIN_DESC(117, "nand_dq3", 1, 0xc, 16),
- CYGNUS_PIN_DESC(118, "nand_dq4", 1, 0xc, 14),
- CYGNUS_PIN_DESC(119, "nand_dq5", 1, 0xc, 12),
- CYGNUS_PIN_DESC(120, "nand_dq6", 1, 0xc, 10),
- CYGNUS_PIN_DESC(121, "nand_dq7", 1, 0xc, 8),
- CYGNUS_PIN_DESC(122, "nand_rb_l", 1, 0xc, 6),
- CYGNUS_PIN_DESC(123, "nand_re_l", 1, 0xc, 4),
- CYGNUS_PIN_DESC(124, "nand_we_l", 1, 0xc, 2),
- CYGNUS_PIN_DESC(125, "nand_wp_l", 1, 0xc, 0),
- CYGNUS_PIN_DESC(126, "lcd_clac", 1, 0x4, 26),
- CYGNUS_PIN_DESC(127, "lcd_clcp", 1, 0x4, 24),
- CYGNUS_PIN_DESC(128, "lcd_cld0", 1, 0x4, 22),
- CYGNUS_PIN_DESC(129, "lcd_cld1", 1, 0x4, 0),
- CYGNUS_PIN_DESC(130, "lcd_cld10", 1, 0x4, 20),
- CYGNUS_PIN_DESC(131, "lcd_cld11", 1, 0x4, 18),
- CYGNUS_PIN_DESC(132, "lcd_cld12", 1, 0x4, 16),
- CYGNUS_PIN_DESC(133, "lcd_cld13", 1, 0x4, 14),
- CYGNUS_PIN_DESC(134, "lcd_cld14", 1, 0x4, 12),
- CYGNUS_PIN_DESC(135, "lcd_cld15", 1, 0x4, 10),
- CYGNUS_PIN_DESC(136, "lcd_cld16", 1, 0x4, 8),
- CYGNUS_PIN_DESC(137, "lcd_cld17", 1, 0x4, 6),
- CYGNUS_PIN_DESC(138, "lcd_cld18", 1, 0x4, 4),
- CYGNUS_PIN_DESC(139, "lcd_cld19", 1, 0x4, 2),
- CYGNUS_PIN_DESC(140, "lcd_cld2", 1, 0x8, 22),
- CYGNUS_PIN_DESC(141, "lcd_cld20", 1, 0x8, 30),
- CYGNUS_PIN_DESC(142, "lcd_cld21", 1, 0x8, 28),
- CYGNUS_PIN_DESC(143, "lcd_cld22", 1, 0x8, 26),
- CYGNUS_PIN_DESC(144, "lcd_cld23", 1, 0x8, 24),
- CYGNUS_PIN_DESC(145, "lcd_cld3", 1, 0x8, 20),
- CYGNUS_PIN_DESC(146, "lcd_cld4", 1, 0x8, 18),
- CYGNUS_PIN_DESC(147, "lcd_cld5", 1, 0x8, 16),
- CYGNUS_PIN_DESC(148, "lcd_cld6", 1, 0x8, 14),
- CYGNUS_PIN_DESC(149, "lcd_cld7", 1, 0x8, 12),
- CYGNUS_PIN_DESC(150, "lcd_cld8", 1, 0x8, 10),
- CYGNUS_PIN_DESC(151, "lcd_cld9", 1, 0x8, 8),
- CYGNUS_PIN_DESC(152, "lcd_clfp", 1, 0x8, 6),
- CYGNUS_PIN_DESC(153, "lcd_clle", 1, 0x8, 4),
- CYGNUS_PIN_DESC(154, "lcd_cllp", 1, 0x8, 2),
- CYGNUS_PIN_DESC(155, "lcd_clpower", 1, 0x8, 0),
- CYGNUS_PIN_DESC(156, "camera_vsync", 1, 0x4, 30),
- CYGNUS_PIN_DESC(157, "camera_trigger", 1, 0x0, 0),
- CYGNUS_PIN_DESC(158, "camera_strobe", 1, 0x0, 2),
- CYGNUS_PIN_DESC(159, "camera_standby", 1, 0x0, 4),
- CYGNUS_PIN_DESC(160, "camera_reset_n", 1, 0x0, 6),
- CYGNUS_PIN_DESC(161, "camera_pixdata9", 1, 0x0, 8),
- CYGNUS_PIN_DESC(162, "camera_pixdata8", 1, 0x0, 10),
- CYGNUS_PIN_DESC(163, "camera_pixdata7", 1, 0x0, 12),
- CYGNUS_PIN_DESC(164, "camera_pixdata6", 1, 0x0, 14),
- CYGNUS_PIN_DESC(165, "camera_pixdata5", 1, 0x0, 16),
- CYGNUS_PIN_DESC(166, "camera_pixdata4", 1, 0x0, 18),
- CYGNUS_PIN_DESC(167, "camera_pixdata3", 1, 0x0, 20),
- CYGNUS_PIN_DESC(168, "camera_pixdata2", 1, 0x0, 22),
- CYGNUS_PIN_DESC(169, "camera_pixdata1", 1, 0x0, 24),
- CYGNUS_PIN_DESC(170, "camera_pixdata0", 1, 0x0, 26),
- CYGNUS_PIN_DESC(171, "camera_pixclk", 1, 0x0, 28),
- CYGNUS_PIN_DESC(172, "camera_hsync", 1, 0x0, 30),
- CYGNUS_PIN_DESC(173, "camera_pll_ref_clk", 0, 0, 0),
- CYGNUS_PIN_DESC(174, "usb_id_indication", 0, 0, 0),
- CYGNUS_PIN_DESC(175, "usb_vbus_indication", 0, 0, 0),
- CYGNUS_PIN_DESC(176, "gpio0_3p3", 0, 0, 0),
- CYGNUS_PIN_DESC(177, "gpio1_3p3", 0, 0, 0),
- CYGNUS_PIN_DESC(178, "gpio2_3p3", 0, 0, 0),
- CYGNUS_PIN_DESC(179, "gpio3_3p3", 0, 0, 0),
-};
-
-int cygnus_gpio_request_enable(void *priv, unsigned pin)
-{
- struct cygnus_pinctrl *pinctrl = (struct cygnus_pinctrl *)priv;
- struct cygnus_gpio_mux *mux = &cygnus_pins[pin].gpio_mux;
- u32 val;
-
- /* not all pins support GPIO pinmux override */
- if (!mux->is_supported)
- return -ENOTSUPP;
-
- val = read32(pinctrl->base1 + mux->offset);
- val |= 0x3 << mux->shift;
- write32(pinctrl->base1 + mux->offset, val);
-
- printk(BIOS_INFO, "gpio request enable pin=%u offset=0x%x shift=%u\n",
- pin, mux->offset, mux->shift);
-
- return 0;
-}
-
-void cygnus_gpio_disable_free(void *priv, unsigned pin)
-{
- struct cygnus_pinctrl *pinctrl = (struct cygnus_pinctrl *)priv;
- struct cygnus_gpio_mux *mux = &cygnus_pins[pin].gpio_mux;
- u32 val;
-
- if (!mux->is_supported)
- return;
-
- val = read32(pinctrl->base1 + mux->offset);
- val &= ~(0x3 << mux->shift);
- write32(pinctrl->base1 + mux->offset, val);
-
- printk(BIOS_INFO, "gpio disable free pin=%u offset=0x%x shift=%u\n",
- pin, mux->offset, mux->shift);
-}
-
-void *cygnus_pinmux_init()
-{
- return &pinctrl_data;
-}
diff --git a/src/soc/broadcom/cygnus/ns16550.c b/src/soc/broadcom/cygnus/ns16550.c
deleted file mode 100644
index 0223278..0000000
--- a/src/soc/broadcom/cygnus/ns16550.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- * Copyright (C) Broadcom Corporation
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <boot/coreboot_tables.h>
-#include <console/uart.h>
-#include <delay.h>
-#include <soc/ns16550.h>
-
-#define SYS_NS16550_CLK 100000000
-#define SYS_NS16550_BAUDRATE 115200
-#define MODE_X_DIV 16
-#define SINGLE_CHAR_TIMEOUT (50 * 1000)
-
-static struct ns16550 * const regs =
- (void *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
-
-static int calc_divisor(void)
-{
- /* Compute divisor value. Normally, we should simply return:
- * ns16550_clk / MODE_X_DIV / baudrate
- * but we need to round that value by adding 0.5.
- * Rounding is especially important at high baud rates.
- */
- int div = MODE_X_DIV * SYS_NS16550_BAUDRATE;
- return (SYS_NS16550_CLK + div / 2) / div;
-}
-
-static void ns16550_init(void)
-{
- int baud_divisor = calc_divisor();
-
- while (!(read32(®s->lsr) & UART_LSR_TEMT))
- ;
-
- write32(®s->ier, 0);
- write32(®s->lcr, UART_LCR_BKSE | UART_LCR_8N1);
- write32(®s->dll, 0);
- write32(®s->dlm, 0);
- write32(®s->lcr, UART_LCR_8N1);
- write32(®s->mcr, UART_MCR_DTR | UART_MCR_RTS);
- /* clear & enable FIFOs */
- write32(®s->fcr, UART_FCR_FIFO_EN | UART_FCR_RXSR | UART_FCR_TXSR);
- write32(®s->lcr, UART_LCR_BKSE | UART_LCR_8N1);
- write32(®s->dll, baud_divisor & 0xff);
- write32(®s->dlm, (baud_divisor >> 8) & 0xff);
- write32(®s->lcr, UART_LCR_8N1);
-}
-
-static void ns16550_tx_byte(unsigned char data)
-{
- while ((read32(®s->lsr) & UART_LSR_THRE) == 0)
- ;
- write32(®s->thr, data);
-}
-
-static void ns16550_tx_flush(void)
-{
- while (!(read32(®s->lsr) & UART_LSR_TEMT))
- ;
-}
-
-static int ns16550_tst_byte(void)
-{
- return (read32(®s->lsr) & UART_LSR_DR) != 0;
-}
-
-static unsigned char ns16550_rx_byte(void)
-{
- unsigned long int i = SINGLE_CHAR_TIMEOUT;
- while (i && !ns16550_tst_byte()) {
- udelay(1);
- i--;
- }
- if (i)
- return read32(®s->rbr);
- else
- return 0x0;
-}
-
-void uart_init(int idx)
-{
- ns16550_init();
-}
-
-void uart_tx_byte(int idx, unsigned char data)
-{
- ns16550_tx_byte(data);
-}
-
-void uart_tx_flush(int idx)
-{
- ns16550_tx_flush();
-}
-
-unsigned char uart_rx_byte(int idx)
-{
- return ns16550_rx_byte();
-}
-
-#ifndef __PRE_RAM__
-void uart_fill_lb(void *data)
-{
- struct lb_serial serial;
- serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
- serial.baseaddr = (uintptr_t)regs;
- serial.baud = get_uart_baudrate();
- serial.regwidth = 4;
- lb_add_serial(&serial, data);
-
- lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
-}
-#endif
diff --git a/src/soc/broadcom/cygnus/phy_reg_access.c b/src/soc/broadcom/cygnus/phy_reg_access.c
deleted file mode 100644
index ea82dde..0000000
--- a/src/soc/broadcom/cygnus/phy_reg_access.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#include "soc/shmoo_and28/phy_reg_access.h"
-
-uint32 REGRD (uint32 address) {
-
- volatile unsigned long data;
-
- data = (* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address)));
- //printf("REGRD %08X=%08X\n", address, data);
- return data;
-}
-
-uint32 REGWR (uint32 address, uint32 data) {
-
- ((* (volatile uint32 *) (((uint32)GLOBAL_REG_RBUS_START) | (address))) = data);
- //printf("REGWR %08X=%08X\n", address, data);
- // return SOC_E_NONE;
- return 0;
-}
diff --git a/src/soc/broadcom/cygnus/romstage.c b/src/soc/broadcom/cygnus/romstage.c
deleted file mode 100644
index 6af7704..0000000
--- a/src/soc/broadcom/cygnus/romstage.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <arch/exception.h>
-#include <arch/stages.h>
-#include <armv7.h>
-#include <cbmem.h>
-#include <console/console.h>
-#include <delay.h>
-#include <program_loading.h>
-#include <soc/gpio.h>
-#include <soc/sdram.h>
-#include <stdlib.h>
-#include <symbols.h>
-#include <timestamp.h>
-#include <types.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void main(void)
-{
- timestamp_add_now(TS_START_ROMSTAGE);
-
- console_init();
-
- timestamp_add_now(TS_BEFORE_INITRAM);
- sdram_init();
- timestamp_add_now(TS_AFTER_INITRAM);
-
- /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */
- mmu_config_range((uintptr_t)_dram/MiB,
- sdram_size_mb(), DCACHE_WRITEBACK);
- mmu_config_range((uintptr_t)_dma_coherent/MiB,
- _dma_coherent_size/MiB, DCACHE_OFF);
- gpio_init();
-
- cbmem_initialize_empty();
-
- run_ramstage();
-}
diff --git a/src/soc/broadcom/cygnus/sdram.c b/src/soc/broadcom/cygnus/sdram.c
deleted file mode 100644
index e1e4524..0000000
--- a/src/soc/broadcom/cygnus/sdram.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#include <console/console.h>
-#include <symbols.h>
-#include <soc/sdram.h>
-
-#define DRAM_TEST_LEN 0x8000000
-
-static void test_ddr(void)
-{
- if (IS_ENABLED(CONFIG_CYGNUS_SDRAM_TEST_DDR)) {
- uint32_t *test_buffer = (uint32_t *) _dram;
- uint32_t len = DRAM_TEST_LEN;
- uint32_t i;
- uint32_t fail_count = 0;
-
- printk(BIOS_INFO, "test ddr start from 0x%p to 0x%p\n", test_buffer,
- test_buffer + len);
-
- for (i = 0; i < len; i++)
- *(test_buffer + i) = i;
-
- for (i = 0; i < len; i++) {
- int val = *(test_buffer + i);
-
- if ((i % 0x10000) == 0)
- printk(BIOS_INFO, "#");
-
- if (i != val) {
- printk(BIOS_ERR, "\ntest_ddr: @ 0x%p: %d != %d\n",
- test_buffer + i, i, val);
- fail_count++;
- }
- }
- printk(BIOS_INFO, "\ntest ddr end: fail=%d\n", fail_count);
- }
-}
-
-void sdram_init(void)
-{
- printk(BIOS_INFO, "sdram initialization is in progress...\n");
- ddr_init2();
- printk(BIOS_INFO, "sdram initialization is completed.\n");
-
- test_ddr();
-}
-
-uint32_t sdram_size_mb(void)
-{
- return CONFIG_DRAM_SIZE_MB;
-}
diff --git a/src/soc/broadcom/cygnus/shmoo_and28.c b/src/soc/broadcom/cygnus/shmoo_and28.c
deleted file mode 100644
index 7038a31..0000000
--- a/src/soc/broadcom/cygnus/shmoo_and28.c
+++ /dev/null
@@ -1,4884 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-
-#include <string.h>
-#include <soc/config.h>
-#include <soc/reg_utils.h>
-
-#define SOC_IF_ERROR_RETURN(x) (x)
-#define sal_memset(x,y,z) memset(x,y,z)
-#define sal_usleep(x) udelay(x)
-
-/* BEGIN: TEMPORARY */
-#ifndef BCM_AND28_SUPPORT
-#define BCM_AND28_SUPPORT
-#endif
-/* END: TEMPORARY */
-
-#if IS_ENABLED(CONFIG_CYGNUS_PRINT_SHMOO_DEBUG)
-#define PLOT_SUPPORT
-#endif
-
-#ifdef BCM_AND28_SUPPORT
-#include <soc/shmoo_and28/shmoo_and28.h>
-#include <soc/shmoo_and28/phy_reg_access.h>
-#include <soc/shmoo_and28/ydc_ddr_bist.h>
-
-#ifdef PHY_AND28_E2
-#include <soc/shmoo_and28/phy_and28_e2.h>
-#else
-#error "Phy_AND version is not defined."
-#endif
-#endif
-
-and28_shmoo_dram_info_t *shmoo_dram_info_ptr;
-static and28_shmoo_dram_info_t shmoo_dram_info;
-static and28_shmoo_container_t shmoo_container = {0};
-
-#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3)
-const uint32 shmoo_order_and28_ddr3[SHMOO_AND28_DDR3_SEQUENCE_COUNT] =
-{
- SHMOO_AND28_RD_EN,
- SHMOO_AND28_RD_EXTENDED,
- SHMOO_AND28_WR_EXTENDED,
- SHMOO_AND28_ADDR_EXTENDED,
- SHMOO_AND28_CTRL_EXTENDED
-};
-#endif
-
-#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3L)
-const uint32 shmoo_order_and28_ddr3l[SHMOO_AND28_DDR3L_SEQUENCE_COUNT] =
-{
- SHMOO_AND28_RD_EN,
- SHMOO_AND28_RD_EXTENDED,
- SHMOO_AND28_WR_EXTENDED,
- SHMOO_AND28_ADDR_EXTENDED,
- SHMOO_AND28_CTRL_EXTENDED
-};
-#endif
-
-/* Local function prototype */
-uint32 _shmoo_and28_check_dram(int phy_ndx);
-int _and28_calculate_step_size(int unit, int phy_ndx, and28_step_size_t *ssPtr);
-int _and28_zq_calibration(int unit, int phy_ndx);
-int _soc_and28_shmoo_phy_cfg_pll(int unit, int phy_ndx);
-
-uint32
-_shmoo_and28_check_dram(int phy_ndx)
-{
- return ((shmoo_dram_info_ptr->dram_bitmap >> phy_ndx) & 0x1);
-}
-
-static int
-_initialize_bist(int unit, int phy_ndx, int bit, and28_shmoo_container_t *scPtr)
-{
- ydc_ddr_bist_info_t bist_info;
-
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- bist_info.write_weight = 255;
- bist_info.read_weight = 255;
- bist_info.bist_timer_us = 0;
- bist_info.bist_num_actions = 510;
- bist_info.bist_start_address = 0x00000000;
- bist_info.bist_end_address = 0x00FFFFFF;
- bist_info.mpr_mode = 0;
- bist_info.prbs_mode = 1;
- break;
- case SHMOO_AND28_RD_EXTENDED:
- bist_info.write_weight = 255;
- bist_info.read_weight = 255;
- bist_info.bist_timer_us = 0;
- bist_info.bist_num_actions = 510;
- bist_info.bist_start_address = 0x00000000;
- bist_info.bist_end_address = 0x00FFFFFF;
- bist_info.mpr_mode = 0;
- bist_info.prbs_mode = 1;
- break;
- case SHMOO_AND28_WR_EXTENDED:
- bist_info.write_weight = 255;
- bist_info.read_weight = 255;
- bist_info.bist_timer_us = 0;
- bist_info.bist_num_actions = 510;
- bist_info.bist_start_address = 0x00000000;
- bist_info.bist_end_address = 0x00FFFFFF;
- bist_info.mpr_mode = 0;
- bist_info.prbs_mode = 1;
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- bist_info.write_weight = 255;
- bist_info.read_weight = 255;
- bist_info.bist_timer_us = 0;
- bist_info.bist_num_actions = 510;
- bist_info.bist_start_address = 0x00000000;
- bist_info.bist_end_address = 0x00FFFFFF;
- bist_info.mpr_mode = 0;
- bist_info.prbs_mode = 1;
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- bist_info.write_weight = 255;
- bist_info.read_weight = 255;
- bist_info.bist_timer_us = 0;
- bist_info.bist_num_actions = 510;
- bist_info.bist_start_address = 0x00000000;
- bist_info.bist_end_address = 0x00FFFFFF;
- bist_info.mpr_mode = 0;
- bist_info.prbs_mode = 1;
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
-
- return soc_ydc_ddr_bist_config_set(unit, phy_ndx, &bist_info);
-}
-
-static int
-_run_bist(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, and28_shmoo_error_array_t *seaPtr)
-{
- ydc_ddr_bist_err_cnt_t be;
-
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
-
- if (shmoo_dram_info_ptr->interface_bitwidth == 16)
- {
- (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
- }
- else
- {
- (*seaPtr)[0] = be.bist_err_occur;
- }
- break;
- case SHMOO_AND28_RD_EXTENDED:
- SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
-
- if (shmoo_dram_info_ptr->interface_bitwidth == 16)
- {
- (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
- }
- else
- {
- (*seaPtr)[0] = be.bist_err_occur;
- }
- break;
- case SHMOO_AND28_WR_EXTENDED:
- SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
-
- if (shmoo_dram_info_ptr->interface_bitwidth == 16)
- {
- (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
- }
- else
- {
- (*seaPtr)[0] = be.bist_err_occur;
- }
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
-
- if (shmoo_dram_info_ptr->interface_bitwidth == 16)
- {
- (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
- }
- else
- {
- (*seaPtr)[0] = be.bist_err_occur;
- }
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- SOC_IF_ERROR_RETURN(soc_ydc_ddr_bist_run(unit, phy_ndx, &be));
-
- if (shmoo_dram_info_ptr->interface_bitwidth == 16)
- {
- (*seaPtr)[0] = (((be.bist_err_occur) >> 16) | (be.bist_err_occur)) & 0xFFFF;
- }
- else
- {
- (*seaPtr)[0] = be.bist_err_occur;
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_rd_en(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 x;
- uint32 y;
- uint32 jump;
- uint32 yCapMin;
- uint32 yCapMax;
- uint32 xStart;
- uint32 data;
- and28_shmoo_error_array_t sea;
-
- yCapMin = 0;
- yCapMax = (*scPtr).sizeY;
- jump = (*scPtr).yJump;
- xStart = 0;
-
- (*scPtr).engageUIshift = 0;
- (*scPtr).yCapMin = yCapMin;
- (*scPtr).yCapMax = yCapMax;
- (*scPtr).shmooType = SHMOO_AND28_RD_EN;
-
- _initialize_bist(unit, phy_ndx, -1, scPtr);
-
- for (y = yCapMin; y < yCapMax; y++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, y << jump);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
- #endif
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- (*scPtr).result2D[x + xStart] = sea[0];
- }
-
- xStart += (*scPtr).sizeX;
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_wr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 x;
- uint32 data;
- and28_shmoo_error_array_t sea;
-
- (*scPtr).engageUIshift = 0;
- (*scPtr).sizeY = 1;
- (*scPtr).yCapMin = 0;
- (*scPtr).yCapMax = 1;
- (*scPtr).shmooType = SHMOO_AND28_WR_EXTENDED;
-
- _initialize_bist(unit, phy_ndx, -1, scPtr);
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- (*scPtr).result2D[x] = sea[0];
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_rd_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 x;
- uint32 y;
- uint32 yCapMin;
- uint32 yCapMax;
- uint32 xStart;
- uint32 data, temp;
- uint32 rd_dqs_pos0, rd_dqs_pos1, rd_en_pos0, rd_en_pos1, rd_dqs_delta0, rd_dqs_delta1;
- uint32 rd_dq_fail_count0, rd_dq_fail_count1;
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- uint32 rd_dqs_pos2, rd_dqs_pos3, rd_en_pos2, rd_en_pos3, rd_dqs_delta2, rd_dqs_delta3;
- uint32 rd_dq_fail_count2, rd_dq_fail_count3;
- #endif
- and28_shmoo_error_array_t sea;
-
- yCapMin = 16;
- yCapMax = 49;
- xStart = 0;
-
- (*scPtr).engageUIshift = 0;
- (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE;
- (*scPtr).yCapMin = yCapMin;
- (*scPtr).yCapMax = yCapMax;
- (*scPtr).yJump = 0;
- (*scPtr).shmooType = SHMOO_AND28_RD_EXTENDED;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP);
- }
- #endif
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
- }
- #endif
-
- _initialize_bist(unit, phy_ndx, -1, scPtr);
-
- x = 0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
- }
- #endif
-
- rd_dqs_delta0 = x - rd_dqs_pos0;
- rd_dqs_delta1 = x - rd_dqs_pos1;
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- rd_dqs_delta2 = x - rd_dqs_pos2;
- rd_dqs_delta3 = x - rd_dqs_pos3;
- }
- #endif
-
- temp = rd_en_pos0 + rd_dqs_delta0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos1 + rd_dqs_delta1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- temp = rd_en_pos2 + rd_dqs_delta2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos3 + rd_dqs_delta3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- rd_dq_fail_count0 = 0;
- rd_dq_fail_count1 = 0;
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- rd_dq_fail_count2 = 0;
- rd_dq_fail_count3 = 0;
- }
- #endif
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, x);
- if (rd_dq_fail_count0 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
- if (rd_dq_fail_count1 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- if (rd_dq_fail_count2 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
- if (rd_dq_fail_count3 <= SHMOO_AND28_RD_DQ_FAIL_CAP)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- if ((sea[0] & 0x000000FF) == 0x000000FF)
- {
- rd_dq_fail_count0++;
- }
- if ((sea[0] & 0x0000FF00) == 0x0000FF00)
- {
- rd_dq_fail_count1++;
- }
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- if ((sea[0] & 0x00FF0000) == 0x00FF0000)
- {
- rd_dq_fail_count2++;
- }
- if ((sea[0] & 0xFF000000) == 0xFF000000)
- {
- rd_dq_fail_count3++;
- }
- }
- #endif
-
- if ((rd_dq_fail_count0 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count1 > SHMOO_AND28_RD_DQ_FAIL_CAP))
- {
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- if ((rd_dq_fail_count2 > SHMOO_AND28_RD_DQ_FAIL_CAP) && (rd_dq_fail_count3 > SHMOO_AND28_RD_DQ_FAIL_CAP))
- {
- break;
- }
- }
- else
- {
- break;
- }
- #else
- break;
- #endif
- }
- }
-
- for (y = yCapMin; y < yCapMax; y++)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, y);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, y);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
- }
- #endif
-
- rd_dqs_delta0 = x - rd_dqs_pos0;
- rd_dqs_delta1 = x - rd_dqs_pos1;
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- rd_dqs_delta2 = x - rd_dqs_pos2;
- rd_dqs_delta3 = x - rd_dqs_pos3;
- }
- #endif
-
- temp = rd_en_pos0 + rd_dqs_delta0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos1 + rd_dqs_delta1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- temp = rd_en_pos2 + rd_dqs_delta2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos3 + rd_dqs_delta3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- (*scPtr).result2D[x + xStart] = sea[0];
- }
-
- xStart += (*scPtr).sizeX;
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_addr_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 x;
- uint32 data;
- and28_shmoo_error_array_t sea;
-
- (*scPtr).engageUIshift = 0;
- (*scPtr).sizeY = 1;
- (*scPtr).yCapMin = 0;
- (*scPtr).yCapMax = 1;
- (*scPtr).shmooType = SHMOO_AND28_ADDR_EXTENDED;
-
- _initialize_bist(unit, phy_ndx, -1, scPtr);
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- (*scPtr).result2D[x] = sea[0];
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_ctrl_extended(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 x;
- uint32 data;
- and28_shmoo_error_array_t sea;
-
- (*scPtr).engageUIshift = 0;
- (*scPtr).sizeY = 1;
- (*scPtr).yCapMin = 0;
- (*scPtr).yCapMax = 1;
- (*scPtr).shmooType = SHMOO_AND28_CTRL_EXTENDED;
-
- _initialize_bist(unit, phy_ndx, -1, scPtr);
-
- for (x = 0; x < (*scPtr).sizeX; x++)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, x);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- _run_bist(unit, phy_ndx, scPtr, &sea);
-
- (*scPtr).result2D[x] = sea[0];
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_do(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- return _shmoo_and28_rd_en(unit, phy_ndx, scPtr);
- case SHMOO_AND28_RD_EXTENDED:
- return _shmoo_and28_rd_extended(unit, phy_ndx, scPtr);
- case SHMOO_AND28_WR_EXTENDED:
- return _shmoo_and28_wr_extended(unit, phy_ndx, scPtr);
- case SHMOO_AND28_ADDR_EXTENDED:
- return _shmoo_and28_addr_extended(unit, phy_ndx, scPtr);
- case SHMOO_AND28_CTRL_EXTENDED:
- if (!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
- {
- return _shmoo_and28_ctrl_extended(unit, phy_ndx, scPtr);
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
- return SOC_E_NONE;
-}
-
-static int
-_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 calibMode, uint32 calibPos)
-{
- uint32 x;
- uint32 y;
- uint32 xStart;
- uint32 sizeX;
- uint32 calibStart;
- uint32 yCapMin;
- uint32 yCapMax;
- uint32 i;
- uint32 iter;
- uint32 shiftAmount;
- uint32 dataMask;
- int32 passStart;
- int32 failStart;
- int32 passStartSeen;
- int32 failStartSeen;
- int32 passLength;
- int32 maxPassStart;
- int32 maxPassLength;
- int32 maxMidPointX;
- uint32 maxPassLengthArray[SHMOO_AND28_WORD];
-
- xStart = 0;
- sizeX = (*scPtr).sizeX;
- calibStart = (*scPtr).calibStart;
- yCapMin = (*scPtr).yCapMin;
- yCapMax = (*scPtr).yCapMax;
-
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- iter = shmoo_dram_info_ptr->interface_bitwidth;
- shiftAmount = 0;
- dataMask = 0x1;
- break;
- case SHMOO_AND28_BYTE:
- iter = shmoo_dram_info_ptr->interface_bitwidth >> 3;
- shiftAmount = 3;
- dataMask = 0xFF;
- break;
- case SHMOO_AND28_HALFWORD:
- iter = shmoo_dram_info_ptr->interface_bitwidth >> 4;
- shiftAmount = 4;
- dataMask = 0xFFFF;
- break;
- case SHMOO_AND28_WORD:
- iter = 1;
- shiftAmount = 5;
- dataMask = 0xFFFFFFFF;
- break;
- default:
- printf("Unsupported 2D calibration mode: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
-
- for (i = 0; i < iter; i++)
- {
- (*scPtr).resultData[i] = 0;
- maxPassLengthArray[i] = 0;
- }
-
- for (y = yCapMin; y < yCapMax; y++)
- {
- for (i = 0; i < iter; i++)
- {
- passStart = -1;
- failStart = -1;
- passLength = -1;
- passStartSeen = -1;
- failStartSeen = -1;
- maxPassStart = -2;
- maxPassLength = -2;
- maxMidPointX = -2;
- for (x = calibStart; x < sizeX; x++)
- {
- if (((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask)
- { /* FAIL */
- if (failStart < 0) {
- failStart = x;
- if (maxPassLength < passLength)
- {
- maxPassStart = passStart;
- maxPassLength = passLength;
- }
- passStart = -1;
- passLength = -1;
- if ((failStartSeen < 0) && (maxPassLength > 0))
- {
- failStartSeen = x;
- }
- }
- }
- else
- { /* PASS */
- if (passStart < 0)
- {
- passStart = x;
- passLength = 1;
- failStart = -1;
- if ((passStartSeen < 0) && (passLength < x))
- {
- passStartSeen = x;
- }
- }
- else
- {
- passLength++;
- }
-
- if (x == sizeX - 1)
- {
- if (maxPassLength < passLength)
- {
- maxPassStart = passStart;
- maxPassLength = passLength;
- }
- }
- }
- }
-
- switch (calibPos) {
- case SHMOO_AND28_CALIB_FAIL_START:
- case SHMOO_AND28_CALIB_RISING_EDGE:
- if (failStartSeen > 0)
- {
- maxMidPointX = failStartSeen;
- (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
- }
- break;
- case SHMOO_AND28_CALIB_PASS_START:
- case SHMOO_AND28_CALIB_FALLING_EDGE:
- if (passStartSeen > 0)
- {
- maxMidPointX = passStartSeen;
- (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
- }
- break;
- case SHMOO_AND28_CALIB_CENTER_PASS:
- if ((maxPassLength > 0) && (maxPassLengthArray[i] < maxPassLength))
- {
- maxMidPointX = (maxPassStart + maxPassStart + maxPassLength) >> 1;
- (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
- maxPassLengthArray[i] = maxPassLength;
- }
- break;
- case SHMOO_AND28_CALIB_VDL_ZERO:
- maxMidPointX = 0;
- (*scPtr).resultData[i] = (y << 16) | (maxMidPointX & 0xFFFF);
- break;
- default:
- printf("Unsupported calibration position: %02u\n", calibPos);
- return SOC_E_FAIL;
- }
- }
- xStart += sizeX;
- }
-
- (*scPtr).calibMode = calibMode;
- (*scPtr).calibPos = calibPos;
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_calib_2D(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
- case SHMOO_AND28_RD_EXTENDED:
- return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
- case SHMOO_AND28_WR_EXTENDED:
- return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE, SHMOO_AND28_CALIB_CENTER_PASS);
- case SHMOO_AND28_ADDR_EXTENDED:
- return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS);
- case SHMOO_AND28_CTRL_EXTENDED:
- if (!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
- {
- return _calib_2D(unit, phy_ndx, scPtr, SHMOO_AND28_WORD, SHMOO_AND28_CALIB_CENTER_PASS);
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_set_new_step(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- uint32 calibMode;
-/* uint32 engageUIshift; */
- uint32 val, yVal;
- uint32 data, temp;
- uint32 rd_dqs_pos0, rd_dqs_pos1, rd_en_pos0, rd_en_pos1, rd_dqs_delta0, rd_dqs_delta1;
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- uint32 rd_dqs_pos2, rd_dqs_pos3, rd_en_pos2, rd_en_pos3, rd_dqs_delta2, rd_dqs_delta3;
- #endif
-
- calibMode = (*scPtr).calibMode;
-/* engageUIshift = (*scPtr).engageUIshift; */
-
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_BYTE:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_HALFWORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_WORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- default:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_RD_EXTENDED:
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
- rd_dqs_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP);
- }
- #endif
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos0 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos1 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos2 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
- rd_en_pos3 = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP);
- }
- #endif
-
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_BYTE:
- val = (*scPtr).resultData[0] & 0xFFFF;
- rd_dqs_delta0 = val - rd_dqs_pos0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos0 + rd_dqs_delta0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- val = (*scPtr).resultData[1] & 0xFFFF;
- rd_dqs_delta1 = val - rd_dqs_pos1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos1 + rd_dqs_delta1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- val = (*scPtr).resultData[2] & 0xFFFF;
- rd_dqs_delta2 = val - rd_dqs_pos2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos2 + rd_dqs_delta2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- val = (*scPtr).resultData[3] & 0xFFFF;
- rd_dqs_delta3 = val - rd_dqs_pos3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos3 + rd_dqs_delta3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)
- + (((*scPtr).resultData[2] >> 16) & 0xFFFF) + (((*scPtr).resultData[3] >> 16) & 0xFFFF)) >> 2;
- }
- else
- {
- yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
- }
- #else
- yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_HALFWORD:
- val = (*scPtr).resultData[0] & 0xFFFF;
- rd_dqs_delta0 = val - rd_dqs_pos0;
- rd_dqs_delta1 = val - rd_dqs_pos1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos0 + rd_dqs_delta0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos1 + rd_dqs_delta1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- val = (*scPtr).resultData[1] & 0xFFFF;
- rd_dqs_delta2 = val - rd_dqs_pos2;
- rd_dqs_delta3 = val - rd_dqs_pos3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos2 + rd_dqs_delta2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos3 + rd_dqs_delta3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- yVal = ((((*scPtr).resultData[0] >> 16) & 0xFFFF) + (((*scPtr).resultData[1] >> 16) & 0xFFFF)) >> 1;
- }
- else
- {
- yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
- }
- #else
- yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_WORD:
- val = (*scPtr).resultData[0] & 0xFFFF;
- rd_dqs_delta0 = val - rd_dqs_pos0;
- rd_dqs_delta1 = val - rd_dqs_pos1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, val);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos0 + rd_dqs_delta0;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos1 + rd_dqs_delta1;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- rd_dqs_delta2 = val - rd_dqs_pos2;
- rd_dqs_delta3 = val - rd_dqs_pos3;
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
-
- temp = rd_en_pos2 + rd_dqs_delta2;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
-
- temp = rd_en_pos3 + rd_dqs_delta3;
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- if (temp & 0x80000000)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, 0);
- }
- else if (temp >= SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_RD_EN_CS0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- yVal = ((*scPtr).resultData[0] >> 16) & 0xFFFF;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, yVal);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, yVal);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- default:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_WR_EXTENDED:
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_BYTE:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_1, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[2] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_3, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[3] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_HALFWORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_2, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[1] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_WORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- default:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_BYTE:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_HALFWORD:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_WORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- default:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- if (SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- }
- else
- {
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_BYTE:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_HALFWORD:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- case SHMOO_AND28_WORD:
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, (*scPtr).resultData[0] & 0xFFFF);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- default:
- printf("Unsupported shmoo type and calibration mode combination during set new step: %02u / %02u\n", (*scPtr).shmooType, calibMode);
- return SOC_E_FAIL;
- }
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- return SOC_E_NONE;
-}
-
-#ifdef PLOT_SUPPORT
-static int
-_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 plotMode)
-{
- uint32 x;
- uint32 y;
- uint32 xStart;
- uint32 sizeX;
- uint32 sizeY;
- uint32 yCapMin;
- uint32 yCapMax;
- uint32 yJump;
- uint32 i;
- uint32 ui;
- uint32 iter;
- uint32 shiftAmount;
- uint32 dataMask;
- uint32 calibMode;
- uint32 calibPos;
- uint32 calibStart;
- uint32 engageUIshift;
- uint32 step1000;
- uint32 size1000UI;
- uint32 calibShiftAmount;
- uint32 maxMidPointX;
- uint32 maxMidPointY;
- char str0[SHMOO_AND28_STRING_LENGTH];
- char str1[SHMOO_AND28_STRING_LENGTH];
- char str2[SHMOO_AND28_STRING_LENGTH];
- char pass_low[2];
- char fail_high[2];
- char outOfSearch[2];
-
- outOfSearch[0] = ' ';
- outOfSearch[1] = 0;
-
- sizeX = (*scPtr).sizeX;
- sizeY = (*scPtr).sizeY;
- yCapMin = (*scPtr).yCapMin;
- yCapMax = (*scPtr).yCapMax;
- yJump = (*scPtr).yJump;
- calibMode = (*scPtr).calibMode;
- calibPos = (*scPtr).calibPos;
- calibStart = (*scPtr).calibStart;
- engageUIshift = (*scPtr).engageUIshift;
- step1000 = (*scPtr).step1000;
- size1000UI = (*scPtr).size1000UI;
-
- switch (calibPos) {
- case SHMOO_AND28_CALIB_RISING_EDGE:
- case SHMOO_AND28_CALIB_FALLING_EDGE:
- pass_low[0] = '_';
- pass_low[1] = 0;
- fail_high[0] = '|';
- fail_high[1] = 0;
- break;
- case SHMOO_AND28_CALIB_CENTER_PASS:
- case SHMOO_AND28_CALIB_PASS_START:
- case SHMOO_AND28_CALIB_FAIL_START:
- case SHMOO_AND28_CALIB_VDL_ZERO:
- pass_low[0] = '+';
- pass_low[1] = 0;
- fail_high[0] = '-';
- fail_high[1] = 0;
- break;
- default:
- printf("Unsupported calibration position: %02u\n", calibPos);
- return SOC_E_FAIL;
- }
-
- printf("\n\n");
-
- switch(plotMode)
- {
- case SHMOO_AND28_BIT:
- iter = shmoo_dram_info_ptr->interface_bitwidth;
- shiftAmount = 0;
- dataMask = 0x1;
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_BYTE:
- calibShiftAmount = 3;
- break;
- case SHMOO_AND28_HALFWORD:
- calibShiftAmount = 4;
- break;
- case SHMOO_AND28_WORD:
- calibShiftAmount = 5;
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_BYTE:
- iter = shmoo_dram_info_ptr->interface_bitwidth >> 3;
- shiftAmount = 3;
- dataMask = 0xFF;
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("WARNING: Plot mode coerced from byte mode to bit mode\n");
- iter = shmoo_dram_info_ptr->interface_bitwidth;
- shiftAmount = 0;
- dataMask = 0x1;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_BYTE:
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_HALFWORD:
- calibShiftAmount = 1;
- break;
- case SHMOO_AND28_WORD:
- calibShiftAmount = 2;
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_HALFWORD:
- iter = shmoo_dram_info_ptr->interface_bitwidth >> 4;
- shiftAmount = 4;
- dataMask = 0xFFFF;
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("WARNING: Plot mode coerced from halfword mode to bit mode\n");
- iter = 32;
- shiftAmount = 0;
- dataMask = 0x1;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_BYTE:
- printf("WARNING: Plot mode coerced from halfword mode to byte mode\n");
- iter = 4;
- shiftAmount = 3;
- dataMask = 0xFF;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_HALFWORD:
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_WORD:
- calibShiftAmount = 1;
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
- break;
- case SHMOO_AND28_WORD:
- iter = 1;
- shiftAmount = 5;
- dataMask = 0xFFFFFFFF;
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf("WARNING: Plot mode coerced from word mode to bit mode\n");
- iter = 32;
- shiftAmount = 0;
- dataMask = 0x1;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_BYTE:
- printf("WARNING: Plot mode coerced from word mode to byte mode\n");
- iter = 4;
- shiftAmount = 3;
- dataMask = 0xFF;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_HALFWORD:
- printf("WARNING: Plot mode coerced from word mode to halfword mode\n");
- iter = 2;
- shiftAmount = 4;
- dataMask = 0xFFFF;
- calibShiftAmount = 0;
- break;
- case SHMOO_AND28_WORD:
- calibShiftAmount = 0;
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
- break;
- default:
- printf("Unsupported plot mode: %02u\n", plotMode);
- return SOC_E_FAIL;
- }
-/*
- if (engageUIshift)
- { */
- ui = 0;
-
- for (x = 0; x < sizeX; x++)
- {
- if ((ui < SHMOO_AND28_MAX_VISIBLE_UI_COUNT) && (x > (*scPtr).endUI[ui]))
- {
- str0[x] = ' ';
- str1[x] = ' ';
- str2[x] = ' ';
- ui++;
- }
- else
- {
- str0[x] = '0' + (x / 100);
- str1[x] = '0' + ((x % 100) / 10);
- str2[x] = '0' + (x % 10);
- }
- }
-/* }
- else
- {
- for (x = 0; x < sizeX; x++)
- {
- str0[x] = '0' + (x / 100);
- str1[x] = '0' + ((x % 100) / 10);
- str2[x] = '0' + (x % 10);
- }
- } */
-
- str0[x] = 0;
- str1[x] = 0;
- str2[x] = 0;
-
- for (i = 0; i < iter; i++)
- {
- xStart = 0;
- maxMidPointX = (*scPtr).resultData[i >> calibShiftAmount] & 0xFFFF;
- maxMidPointY = ((*scPtr).resultData[i >> calibShiftAmount] >> 16) & 0xFFFF;
-
- if ((sizeY > 1) || (i == 0))
- {
- printf("***** Interface.......: %3d\n", phy_ndx);
- printf(" **** VDL step size...: %3u.%03u ps\n", (step1000 / 1000), (step1000 % 1000));
- printf(" **** UI size.........: %3u.%03u steps\n", (size1000UI / 1000), (size1000UI % 1000));
-
- switch((*scPtr).shmooType)
- {
- case SHMOO_AND28_RD_EN:
- printf(" **** Shmoo type......: RD_EN\n");
- break;
- case SHMOO_AND28_RD_EXTENDED:
- printf(" **** Shmoo type......: RD_EXTENDED\n");
- break;
- case SHMOO_AND28_WR_EXTENDED:
- printf(" **** Shmoo type......: WR_EXTENDED\n");
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- printf(" **** Shmoo type......: ADDR_EXTENDED\n");
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- printf(" **** Shmoo type......: CTRL_EXTENDED\n");
- printf(" *** Quick Shmoo.....: Off\n");
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
-
- if (engageUIshift)
- {
- printf(" *** UI shift........: On\n");
- }
- else
- {
- printf(" *** UI shift........: Off or N/A\n");
- }
- }
-
- if (sizeY > 1)
- {
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf(" *** Calib mode......: 2D Bit-wise\n");
- break;
- case SHMOO_AND28_BYTE:
- printf(" *** Calib mode......: 2D Byte-wise\n");
- break;
- case SHMOO_AND28_HALFWORD:
- printf(" *** Calib mode......: 2D Halfword-wise\n");
- break;
- case SHMOO_AND28_WORD:
- printf(" *** Calib mode......: 2D Word-wise\n");
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
-
- switch(plotMode)
- {
- case SHMOO_AND28_BIT:
- printf(" *** Plot mode.......: 2D Bit-wise\n");
- printf(" ** Bit.............: %03u\n", i);
- break;
- case SHMOO_AND28_BYTE:
- printf(" *** Plot mode.......: 2D Byte-wise\n");
- printf(" ** Byte............: %03u\n", i);
- break;
- case SHMOO_AND28_HALFWORD:
- printf(" *** Plot mode.......: 2D Halfword-wise\n");
- printf(" ** Halfword........: %03u\n", i);
- break;
- case SHMOO_AND28_WORD:
- printf(" *** Plot mode.......: 2D Word-wise\n");
- printf(" ** Word............: %03u\n", i);
- break;
- default:
- printf("Unsupported plot mode: %02u\n", plotMode);
- return SOC_E_FAIL;
- }
-
- printf(" * Center X........: %03u\n", maxMidPointX);
- printf(" * Center Y........: %03u\n", maxMidPointY);
- printf(" %s\n", str0);
- printf(" %s\n", str1);
- printf(" %s\n", str2);
-
- for (y = yCapMin; y < yCapMax; y++)
- {
- printf(" %03u ", y << yJump);
-
- for (x = 0; x < calibStart; x++)
- {
- printf("%s", outOfSearch);
- }
-
- for (x = calibStart; x < sizeX; x++)
- {
- if (((*scPtr).result2D[xStart + x] >> (i << shiftAmount)) & dataMask)
- { /* FAIL - RISING EDGE */
- if (x != maxMidPointX)
- { /* REGULAR FAIL */
- printf("%s", fail_high);
- }
- else
- { /* FAIL - RISING EDGE */
- if ((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START))
- { /* RISING EDGE */
- printf("X");
- }
- else
- { /* FAIL */
- printf("%s", fail_high);
- }
- }
- }
- else
- { /* PASS - MIDPOINT - FALLING EDGE */
- if (x != maxMidPointX)
- { /* REGULAR PASS */
- printf("%s", pass_low);
- }
- else
- { /* POTENTIAL MIDPOINT - FALLING EDGE */
- if (y == maxMidPointY)
- { /* MID POINT - FALLING EDGE */
- printf("X");
- }
- else
- { /* PASS */
- printf("%s", pass_low);
- }
- }
- }
- }
- printf("\n");
- xStart += sizeX;
- }
- printf("\n");
- }
- else
- {
- if (i == 0)
- {
- switch(calibMode)
- {
- case SHMOO_AND28_BIT:
- printf(" *** Calib mode......: 1D Bit-wise\n");
- break;
- case SHMOO_AND28_BYTE:
- printf(" *** Calib mode......: 1D Byte-wise\n");
- break;
- case SHMOO_AND28_HALFWORD:
- printf(" *** Calib mode......: 1D Halfword-wise\n");
- break;
- case SHMOO_AND28_WORD:
- printf(" *** Calib mode......: 1D Word-wise\n");
- break;
- default:
- printf("Unsupported calibration mode during plot: %02u\n", calibMode);
- return SOC_E_FAIL;
- }
-
- switch(plotMode)
- {
- case SHMOO_AND28_BIT:
- printf(" *** Plot mode.......: 1D Bit-wise\n");
- break;
- case SHMOO_AND28_BYTE:
- printf(" *** Plot mode.......: 1D Byte-wise\n");
- break;
- case SHMOO_AND28_HALFWORD:
- printf(" *** Plot mode.......: 1D Halfword-wise\n");
- break;
- case SHMOO_AND28_WORD:
- printf(" *** Plot mode.......: 1D Word-wise\n");
- break;
- default:
- printf("Unsupported plot mode: %02u\n", plotMode);
- return SOC_E_FAIL;
- }
- printf(" %s\n", str0);
- printf(" %s\n", str1);
- printf(" %s\n", str2);
- }
-
- printf(" %03u ", i);
-
- for (x = 0; x < calibStart; x++)
- {
- printf("%s", outOfSearch);
- }
-
- for (x = calibStart; x < sizeX; x++)
- {
- if (((*scPtr).result2D[x] >> (i << shiftAmount)) & dataMask)
- { /* FAIL - RISING EDGE */
- if (x != maxMidPointX)
- { /* REGULAR FAIL */
- printf("%s", fail_high);
- }
- else
- { /* FAIL - RISING EDGE */
- if ((calibPos == SHMOO_AND28_CALIB_RISING_EDGE) || (calibPos == SHMOO_AND28_CALIB_FAIL_START))
- { /* RISING EDGE */
- printf("X");
- }
- else
- { /* FAIL */
- printf("%s", fail_high);
- }
- }
- }
- else
- { /* PASS - MIDPOINT - FALLING EDGE */
- if (x != maxMidPointX)
- { /* REGULAR PASS */
- printf("%s", pass_low);
- }
- else
- { /* MID POINT - FALLING EDGE */
- printf("X");
- }
- }
- }
- printf("\n");
- }
- }
- printf("\n");
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_plot(int unit, int phy_ndx, and28_shmoo_container_t *scPtr)
-{
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE);
- case SHMOO_AND28_RD_EXTENDED:
- return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BYTE);
- case SHMOO_AND28_WR_EXTENDED:
- return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_BIT);
- case SHMOO_AND28_ADDR_EXTENDED:
- return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD);
- case SHMOO_AND28_CTRL_EXTENDED:
- if (!SHMOO_AND28_QUICK_SHMOO_CTRL_EXTENDED)
- {
- return _plot(unit, phy_ndx, scPtr, SHMOO_AND28_WORD);
- }
- else
- {
- printf("\n\n");
- printf("***** Interface.......: %3d\n", phy_ndx);
- printf(" **** Shmoo type......: CTRL_EXTENDED\n");
- printf(" *** Quick Shmoo.....: On\n");
- printf(" *** Plot............: Off\n");
- printf(" *** Copying.........: VDL_STEP\n");
- printf(" ** From............: AD00 - AD09\n");
- printf(" ** To..............: AD10 - WE_N\n");
- printf("\n");
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
- return SOC_E_NONE;
-}
-#endif
-
-int
-_and28_calculate_step_size(int unit, int phy_ndx, and28_step_size_t *ssPtr)
-{
- uint32 data;
- uint32 timeout;
-
- if (shmoo_dram_info_ptr->sim_system_mode)
- {
- (*ssPtr).step1000 = 8000;
- (*ssPtr).size1000UI = 78125;
-
- return SOC_E_NONE;
- }
-
- data = 0;
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, CALIB_ONCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_REGS, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIBRATE, UPDATE_FAST, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- timeout = 2000;
- do
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1, &data);
-
- if (DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_IDLE))
- {
- /* printf(" VDL calibration complete.\n"); */
- break;
- }
-
- if (timeout == 0)
- {
- printf(" VDL calibration failed!!! (Timeout)\n");
- return SOC_E_TIMEOUT;
- }
-
- timeout--;
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- }
- while (TRUE);
-
- if (DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_LOCK_4B) == 0)
- {
- printf(" VDL calibration failed!!! (No lock)\n");
- return SOC_E_FAIL;
- }
-
- (*ssPtr).size1000UI = DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CALIB_STATUS1, CALIB_TOTAL_STEPS) * 500;
- (*ssPtr).step1000 = ((1000000000 / shmoo_dram_info_ptr->data_rate_mbps) * 1000) / ((*ssPtr).size1000UI);
-
- data = 0;
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- return SOC_E_NONE;
-}
-
-int
-_and28_zq_calibration(int unit, int phy_ndx)
-{
- int i;
- uint32 data;
- uint32 p_drive, n_drive;
- uint32 p_term, n_term;
- uint32 p_idle, n_idle;
-
- p_drive = 16;
- n_drive = 16;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 31);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- for (i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, i);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
- if (DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_STATUS))
- {
- p_drive = i;
- break;
- }
- }
-
- if (i == SHMOO_AND28_MAX_ZQ_CAL_RANGE)
- {
- printf(" WARNING: ZQ calibration error (P) - Manual IO programming required for correct operation\n");
- /* return SOC_E_FAIL; */
- }
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 31);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- for (i = 0; i < SHMOO_AND28_MAX_ZQ_CAL_RANGE; i++)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, i);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, &data);
- if (DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_STATUS))
- {
- n_drive = i;
- break;
- }
- }
-
- if (i == SHMOO_AND28_MAX_ZQ_CAL_RANGE)
- {
- printf(" WARNING: ZQ calibration error (N) - Manual IO programming required for correct operation\n");
- /* return SOC_E_FAIL; */
- }
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_PCOMP_ENB, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_NCOMP_ENB, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_IDDQ, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_P, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, ZQ_CAL, ZQ_DRIVE_N, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- p_term = 6;
- n_term = 6;
-
- p_idle = 0;
- n_idle = 0;
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_IDLE_STRENGTH, p_idle);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_IDLE_STRENGTH, n_idle);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_TERM_STRENGTH, p_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_TERM_STRENGTH, n_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, DRIVE_PAD_CTL, ADDR_CTL_ND_STRENGTH, n_drive);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL, data);
-
- data = 0;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_IDLE_STRENGTH, p_idle);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_IDLE_STRENGTH, n_idle);
- #endif
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DRIVE_PAD_CTL, data);
- }
- #endif
-
- #ifdef PHY_AND28_F0
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, DQSP_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DQSP_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_DQSN_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DQSP_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_DQSN_DRIVE_PAD_CTL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DQSP_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_DQSN_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DQSP_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_DQSN_DRIVE_PAD_CTL, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_TERM_STRENGTH, p_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_TERM_STRENGTH, n_term);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ALERT_DRIVE_PAD_CTL, BL_ND_STRENGTH, n_drive);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_ALERT_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_ALERT_DRIVE_PAD_CTL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_ALERT_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_ALERT_DRIVE_PAD_CTL, data);
- }
- #endif
- #endif
-
- data = 0;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, EDC_RD_EN_ND_STRENGTH, n_drive);
- #endif
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_PD_STRENGTH, p_drive);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DRIVE_PAD_CTL, BL_RD_EN_ND_STRENGTH, n_drive);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DRIVE_PAD_CTL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DRIVE_PAD_CTL, data);
- }
- #endif
-
- printf(" P drive..........: 0x%02X\n", p_drive);
- printf(" N drive..........: 0x%02X\n", n_drive);
- printf(" P termination....: 0x%02X\n", p_term);
- printf(" N termination....: 0x%02X\n", n_term);
- printf(" P idle...........: 0x%02X\n", p_idle);
- printf(" N idle...........: 0x%02X\n", n_idle);
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_entry(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode)
-{
- /* Mode 0: Sequential entry
- * Mode 1: Single entry
- */
-
- uint32 i;
- uint32 data, temp;
- and28_step_size_t ss;
-
- (*scPtr).calibStart = 0;
-
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- /*A04*/ printf("R04. Configure reference voltage\n");
- /*R04*/ DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- /*A08*/ printf("R08. ZQ calibration\n");
- /*R08*/ if (shmoo_dram_info_ptr->sim_system_mode)
- {
- printf(" Skipped for emulation\n");
-
- goto SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END;
- }
-
- _and28_zq_calibration(unit, phy_ndx);
-
- SHMOO_AND28_RD_EN_ZQ_CALIBRATION_END:
-
- _and28_calculate_step_size(unit, phy_ndx, &ss);
- (*scPtr).step1000 = ss.step1000;
- (*scPtr).size1000UI = ss.size1000UI;
- temp = (ss.size1000UI * 3) / 1000; /* 300% */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
- }
- else
- {
- (*scPtr).sizeX = temp;
- }
-
- temp = (ss.size1000UI * 125) / 100000; /* 125% */
- (*scPtr).yJump = 2;
- temp = temp >> (*scPtr).yJump;
- if (temp > SHMOO_AND28_MAX_VREF_RANGE)
- {
- (*scPtr).sizeY = SHMOO_AND28_MAX_VREF_RANGE;
- }
- else
- {
- (*scPtr).sizeY = temp;
- }
-
- for (i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
- {
- (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
- }
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_CONTROL, MODE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_CONTROL, RD_DATA_DLY, SHMOO_AND28_RD_DATA_DLY_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS0_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, RD_EN_DLY_CYC, CS1_CYCLES, SHMOO_AND28_RD_EN_CYC_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS0, VDL_STEP, SHMOO_AND28_RD_EN_VDL_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS1, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_EN_CS1, VDL_STEP, SHMOO_AND28_RD_EN_VDL_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS1, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQ0P, VDL_STEP, SHMOO_AND28_RD_DQ_VDL_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EDCN, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EDCN, data);
- #endif
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, FORCE, 1);
- temp = (((*scPtr).size1000UI * 3) / 4000) + SHMOO_AND28_RD_DQS_VDL_OFFSET; /* 75% + Offset */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_RD_DQSP, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_CHAN_DLY_CYC, CYCLES, SHMOO_AND28_WR_CYC_INIT);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, data);
- }
- #endif
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, FORCE, 1);
- temp = (*scPtr).size1000UI / 2000;
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, VDL_CONTROL_WR_DQ0, VDL_STEP, temp);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- break;
- case SHMOO_AND28_RD_EXTENDED:
- _and28_calculate_step_size(unit, phy_ndx, &ss);
- (*scPtr).step1000 = ss.step1000;
- (*scPtr).size1000UI = ss.size1000UI;
- temp = (ss.size1000UI * 125) / 100000; /* 125% */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
- }
- else
- {
- (*scPtr).sizeX = temp;
- }
-
- for (i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
- {
- (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
- }
- break;
- case SHMOO_AND28_WR_EXTENDED:
- _and28_calculate_step_size(unit, phy_ndx, &ss);
- (*scPtr).step1000 = ss.step1000;
- (*scPtr).size1000UI = ss.size1000UI;
- temp = (ss.size1000UI * 125) / 100000; /* 125% */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
- }
- else
- {
- (*scPtr).sizeX = temp;
- }
-
- for (i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
- {
- (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
- }
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- _and28_calculate_step_size(unit, phy_ndx, &ss);
- (*scPtr).step1000 = ss.step1000;
- (*scPtr).size1000UI = ss.size1000UI;
- temp = (ss.size1000UI * 25) / 10000; /* 250% */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
- }
- else
- {
- (*scPtr).sizeX = temp;
- }
-
- for (i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
- {
- (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
- }
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- _and28_calculate_step_size(unit, phy_ndx, &ss);
- (*scPtr).step1000 = ss.step1000;
- (*scPtr).size1000UI = ss.size1000UI;
- temp = (ss.size1000UI * 25) / 10000; /* 250% */
- if (temp > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- (*scPtr).sizeX = SHMOO_AND28_MAX_VDL_LENGTH;
- }
- else
- {
- (*scPtr).sizeX = temp;
- }
-
- for (i = 0; i < SHMOO_AND28_MAX_VISIBLE_UI_COUNT; i++)
- {
- (*scPtr).endUI[i] = ((i + 1) * (ss.size1000UI)) / 1000;
- }
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_exit(int unit, int phy_ndx, and28_shmoo_container_t *scPtr, uint32 mode)
-{
- /* Mode 0: Sequential exit
- * Mode 1: Single exit
- */
-
- switch ((*scPtr).shmooType) {
- case SHMOO_AND28_RD_EN:
- break;
- case SHMOO_AND28_RD_EXTENDED:
- break;
- case SHMOO_AND28_WR_EXTENDED:
- break;
- case SHMOO_AND28_ADDR_EXTENDED:
- break;
- case SHMOO_AND28_CTRL_EXTENDED:
- break;
- default:
- printf("Unsupported shmoo type: %02u\n", (*scPtr).shmooType);
- return SOC_E_FAIL;
- }
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_save(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param)
-{
- uint32 data;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, &data);
- (*config_param).control_regs_ad[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, &data);
- (*config_param).control_regs_ad[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, &data);
- (*config_param).control_regs_ad[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, &data);
- (*config_param).control_regs_ad[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, &data);
- (*config_param).control_regs_ad[4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, &data);
- (*config_param).control_regs_ad[5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, &data);
- (*config_param).control_regs_ad[6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, &data);
- (*config_param).control_regs_ad[7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, &data);
- (*config_param).control_regs_ad[8] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, &data);
- (*config_param).control_regs_ad[9] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, &data);
- (*config_param).control_regs_ad[10] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, &data);
- (*config_param).control_regs_ad[11] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, &data);
- (*config_param).control_regs_ad[12] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, &data);
- (*config_param).control_regs_ad[13] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, &data);
- (*config_param).control_regs_ad[14] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, &data);
- (*config_param).control_regs_ad[15] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, &data);
- (*config_param).control_regs_ba[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, &data);
- (*config_param).control_regs_ba[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, &data);
- (*config_param).control_regs_ba[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, &data);
- (*config_param).control_regs_aux[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, &data);
- (*config_param).control_regs_aux[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, &data);
- (*config_param).control_regs_aux[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, &data);
- (*config_param).control_regs_cs[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, &data);
- (*config_param).control_regs_cs[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, &data);
- (*config_param).control_regs_par = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, &data);
- (*config_param).control_regs_ras_n = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, &data);
- (*config_param).control_regs_cas_n = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, &data);
- (*config_param).control_regs_cke = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, &data);
- (*config_param).control_regs_rst_n = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, &data);
- (*config_param).control_regs_odt = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, &data);
- (*config_param).control_regs_we_n = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- (*config_param).control_regs_vref_dac_control = data;
-
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, &data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, &data);
- #endif
- (*config_param).wr_vdl_dqsp[0] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, &data);
- (*config_param).wr_vdl_dqsn[0] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, &data);
- (*config_param).wr_vdl_dq[0][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, &data);
- (*config_param).wr_vdl_dq[0][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, &data);
- (*config_param).wr_vdl_dq[0][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, &data);
- (*config_param).wr_vdl_dq[0][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, &data);
- (*config_param).wr_vdl_dq[0][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, &data);
- (*config_param).wr_vdl_dq[0][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, &data);
- (*config_param).wr_vdl_dq[0][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, &data);
- (*config_param).wr_vdl_dq[0][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, &data);
- (*config_param).wr_vdl_dm[0] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, &data);
- (*config_param).wr_vdl_edc[0] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, &data);
- (*config_param).wr_chan_dly_cyc[0] = (uint8) data;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, &data);
- (*config_param).rd_vdl_dqsp[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, &data);
- (*config_param).rd_vdl_dqsn[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, &data);
- (*config_param).rd_vdl_dqp[0][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, &data);
- (*config_param).rd_vdl_dqp[0][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, &data);
- (*config_param).rd_vdl_dqp[0][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, &data);
- (*config_param).rd_vdl_dqp[0][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, &data);
- (*config_param).rd_vdl_dqp[0][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, &data);
- (*config_param).rd_vdl_dqp[0][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, &data);
- (*config_param).rd_vdl_dqp[0][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, &data);
- (*config_param).rd_vdl_dqp[0][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, &data);
- (*config_param).rd_vdl_dqn[0][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, &data);
- (*config_param).rd_vdl_dqn[0][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, &data);
- (*config_param).rd_vdl_dqn[0][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, &data);
- (*config_param).rd_vdl_dqn[0][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, &data);
- (*config_param).rd_vdl_dqn[0][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, &data);
- (*config_param).rd_vdl_dqn[0][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, &data);
- (*config_param).rd_vdl_dqn[0][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, &data);
- (*config_param).rd_vdl_dqn[0][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, &data);
- (*config_param).rd_vdl_dmp[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, &data);
- (*config_param).rd_vdl_dmn[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[0][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[0][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, &data);
- (*config_param).rd_en_dly_cyc[0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, &data);
- (*config_param).rd_control[0] = (uint8) data;
-
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, &data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, &data);
- #endif
- (*config_param).wr_vdl_dqsp[1] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, &data);
- (*config_param).wr_vdl_dqsn[1] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, &data);
- (*config_param).wr_vdl_dq[1][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, &data);
- (*config_param).wr_vdl_dq[1][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, &data);
- (*config_param).wr_vdl_dq[1][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, &data);
- (*config_param).wr_vdl_dq[1][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, &data);
- (*config_param).wr_vdl_dq[1][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, &data);
- (*config_param).wr_vdl_dq[1][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, &data);
- (*config_param).wr_vdl_dq[1][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, &data);
- (*config_param).wr_vdl_dq[1][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, &data);
- (*config_param).wr_vdl_dm[1] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, &data);
- (*config_param).wr_vdl_edc[1] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, &data);
- (*config_param).wr_chan_dly_cyc[1] = (uint8) data;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, &data);
- (*config_param).rd_vdl_dqsp[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, &data);
- (*config_param).rd_vdl_dqsn[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, &data);
- (*config_param).rd_vdl_dqp[1][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, &data);
- (*config_param).rd_vdl_dqp[1][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, &data);
- (*config_param).rd_vdl_dqp[1][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, &data);
- (*config_param).rd_vdl_dqp[1][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, &data);
- (*config_param).rd_vdl_dqp[1][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, &data);
- (*config_param).rd_vdl_dqp[1][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, &data);
- (*config_param).rd_vdl_dqp[1][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, &data);
- (*config_param).rd_vdl_dqp[1][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, &data);
- (*config_param).rd_vdl_dqn[1][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, &data);
- (*config_param).rd_vdl_dqn[1][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, &data);
- (*config_param).rd_vdl_dqn[1][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, &data);
- (*config_param).rd_vdl_dqn[1][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, &data);
- (*config_param).rd_vdl_dqn[1][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, &data);
- (*config_param).rd_vdl_dqn[1][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, &data);
- (*config_param).rd_vdl_dqn[1][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, &data);
- (*config_param).rd_vdl_dqn[1][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, &data);
- (*config_param).rd_vdl_dmp[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, &data);
- (*config_param).rd_vdl_dmn[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[1][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[1][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, &data);
- (*config_param).rd_en_dly_cyc[1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, &data);
- (*config_param).rd_control[1] = (uint8) data;
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, &data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, &data);
- #endif
- (*config_param).wr_vdl_dqsp[2] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, &data);
- (*config_param).wr_vdl_dqsn[2] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, &data);
- (*config_param).wr_vdl_dq[2][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, &data);
- (*config_param).wr_vdl_dq[2][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, &data);
- (*config_param).wr_vdl_dq[2][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, &data);
- (*config_param).wr_vdl_dq[2][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, &data);
- (*config_param).wr_vdl_dq[2][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, &data);
- (*config_param).wr_vdl_dq[2][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, &data);
- (*config_param).wr_vdl_dq[2][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, &data);
- (*config_param).wr_vdl_dq[2][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, &data);
- (*config_param).wr_vdl_dm[2] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, &data);
- (*config_param).wr_vdl_edc[2] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, &data);
- (*config_param).wr_chan_dly_cyc[2] = (uint8) data;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, &data);
- (*config_param).rd_vdl_dqsp[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, &data);
- (*config_param).rd_vdl_dqsn[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, &data);
- (*config_param).rd_vdl_dqp[2][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, &data);
- (*config_param).rd_vdl_dqp[2][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, &data);
- (*config_param).rd_vdl_dqp[2][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, &data);
- (*config_param).rd_vdl_dqp[2][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, &data);
- (*config_param).rd_vdl_dqp[2][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, &data);
- (*config_param).rd_vdl_dqp[2][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, &data);
- (*config_param).rd_vdl_dqp[2][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, &data);
- (*config_param).rd_vdl_dqp[2][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, &data);
- (*config_param).rd_vdl_dqn[2][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, &data);
- (*config_param).rd_vdl_dqn[2][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, &data);
- (*config_param).rd_vdl_dqn[2][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, &data);
- (*config_param).rd_vdl_dqn[2][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, &data);
- (*config_param).rd_vdl_dqn[2][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, &data);
- (*config_param).rd_vdl_dqn[2][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, &data);
- (*config_param).rd_vdl_dqn[2][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, &data);
- (*config_param).rd_vdl_dqn[2][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, &data);
- (*config_param).rd_vdl_dmp[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, &data);
- (*config_param).rd_vdl_dmn[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[2][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[2][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, &data);
- (*config_param).rd_en_dly_cyc[2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, &data);
- (*config_param).rd_control[2] = (uint8) data;
-
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, &data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, &data);
- #endif
- (*config_param).wr_vdl_dqsp[3] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, &data);
- (*config_param).wr_vdl_dqsn[3] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, &data);
- (*config_param).wr_vdl_dq[3][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, &data);
- (*config_param).wr_vdl_dq[3][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, &data);
- (*config_param).wr_vdl_dq[3][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, &data);
- (*config_param).wr_vdl_dq[3][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, &data);
- (*config_param).wr_vdl_dq[3][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, &data);
- (*config_param).wr_vdl_dq[3][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, &data);
- (*config_param).wr_vdl_dq[3][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, &data);
- (*config_param).wr_vdl_dq[3][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, &data);
- (*config_param).wr_vdl_dm[3] = (uint16) data;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, &data);
- (*config_param).wr_vdl_edc[3] = (uint16) data;
- #endif
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, &data);
- (*config_param).wr_chan_dly_cyc[3] = (uint8) data;
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, &data);
- (*config_param).rd_vdl_dqsp[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, &data);
- (*config_param).rd_vdl_dqsn[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, &data);
- (*config_param).rd_vdl_dqp[3][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, &data);
- (*config_param).rd_vdl_dqp[3][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, &data);
- (*config_param).rd_vdl_dqp[3][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, &data);
- (*config_param).rd_vdl_dqp[3][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, &data);
- (*config_param).rd_vdl_dqp[3][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, &data);
- (*config_param).rd_vdl_dqp[3][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, &data);
- (*config_param).rd_vdl_dqp[3][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, &data);
- (*config_param).rd_vdl_dqp[3][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, &data);
- (*config_param).rd_vdl_dqn[3][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, &data);
- (*config_param).rd_vdl_dqn[3][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, &data);
- (*config_param).rd_vdl_dqn[3][2] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, &data);
- (*config_param).rd_vdl_dqn[3][3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, &data);
- (*config_param).rd_vdl_dqn[3][4] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, &data);
- (*config_param).rd_vdl_dqn[3][5] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, &data);
- (*config_param).rd_vdl_dqn[3][6] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, &data);
- (*config_param).rd_vdl_dqn[3][7] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, &data);
- (*config_param).rd_vdl_dmp[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, &data);
- (*config_param).rd_vdl_dmn[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[3][0] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, &data);
- (*config_param).rd_en_vdl_cs[3][1] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, &data);
- (*config_param).rd_en_dly_cyc[3] = (uint16) data;
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, &data);
- (*config_param).rd_control[3] = (uint8) data;
- }
- #endif
-
- return SOC_E_NONE;
-}
-
-static int
-_shmoo_and28_restore(int unit, int phy_ndx, and28_shmoo_config_param_t *config_param)
-{
- uint32 data;
-
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[8]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[9]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[10]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[11]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[12]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[13]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[14]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ad[15]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ba[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_aux[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cs[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_par);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_ras_n);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cas_n);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_cke);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_rst_n);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_odt);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
- data = SET_ADDR_VDL_FORCE((uint32) (*config_param).control_regs_we_n);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
- data = SET_VREF_DAC_CONTROL((*config_param).control_regs_vref_dac_control);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
-
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[0]);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P, data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS, data);
- #endif
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N, data);
- #endif
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[0][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC, data);
- #endif
- data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC, data);
-
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[0][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[0][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[0][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC, data);
- data = SET_RD_CONTROL((uint32) (*config_param).rd_control[0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL, data);
-
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[1]);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P, data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS, data);
- #endif
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N, data);
- #endif
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[1][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC, data);
- #endif
- data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC, data);
-
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[1][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[1][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[1][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC, data);
- data = SET_RD_CONTROL((uint32) (*config_param).rd_control[1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[2]);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_P, data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS, data);
- #endif
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQS_N, data);
- #endif
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ0, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ1, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ2, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ3, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ4, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ5, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ6, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[2][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DQ7, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_WR_EDC, data);
- #endif
- data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_CHAN_DLY_CYC, data);
-
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQSN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[2][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ0N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ1N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ2N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ3N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ4N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ5N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ6N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[2][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DQ7N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_DMN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[2][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_RD_EN_DLY_CYC, data);
- data = SET_RD_CONTROL((uint32) (*config_param).rd_control[2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_CONTROL, data);
-
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsp[3]);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_P, data);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS, data);
- #endif
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dqsn[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQS_N, data);
- #endif
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ0, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ1, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ2, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ3, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ4, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ5, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ6, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dq[3][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DQ7, data);
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_dm[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_DM, data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- data = SET_WR_VDL_FORCE((uint32) (*config_param).wr_vdl_edc[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_WR_EDC, data);
- #endif
- data = SET_WR_CHAN_DLY_CYC_FORCE((uint32) (*config_param).wr_chan_dly_cyc[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_CHAN_DLY_CYC, data);
-
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsp[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqsn[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQSN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqp[3][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7P, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ0N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ1N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][2]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ2N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ3N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][4]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ4N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][5]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ5N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][6]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ6N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dqn[3][7]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DQ7N, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmp[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMP, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_vdl_dmn[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_DMN, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][0]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_VDL_FORCE((uint32) (*config_param).rd_en_vdl_cs[3][1]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_VDL_CONTROL_RD_EN_CS0, data);
- data = SET_RD_EN_DLY_CYC_FORCE((uint32) (*config_param).rd_en_dly_cyc[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_RD_EN_DLY_CYC, data);
- data = SET_RD_CONTROL((uint32) (*config_param).rd_control[3]);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_CONTROL, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, READ_FIFO_CLEAR, CLEAR, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR, data);
-
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_READ_FIFO_CLEAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_READ_FIFO_CLEAR, data);
- }
- #endif
-
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- return SOC_E_NONE;
-}
-
-/*
- * Function:
- * soc_and28_shmoo_ctl
- * Purpose:
- * Perform shmoo (PHY calibration) on specific DRC index.
- * Parameters:
- * unit - unit number
- * phy_ndx - DRC index to perform shmoo on.
- * shmoo_type - Selects shmoo sub-section to be performs (-1 for full shmoo)
- * stat - RFU
- * plot - Plot shmoo results when not equal to 0
- * action - Save/restore functionality
- * *config_param - PHY configuration saved/restored
- * Returns:
- * SOC_E_XXX
- * This routine may be called after a device is attached
- * or whenever a chip reset is required.
- */
-
-int
-soc_and28_shmoo_ctl(int unit, int phy_ndx, int shmoo_type, int stat, int plot, int action, and28_shmoo_config_param_t *config_param)
-{
- and28_shmoo_container_t *scPtr = NULL;
- uint32 dramType;
- uint32 ctlType;
- uint32 i;
- int ndx, ndxEnd;
- const uint32 *seqPtr;
- uint32 seqCount;
-
- dramType = shmoo_dram_info_ptr->dram_type;
- ctlType = shmoo_dram_info_ptr->ctl_type;
-
- if (!stat)
- {
- scPtr = &shmoo_container;
- if (scPtr == NULL)
- {
- return SOC_E_MEMORY;
- }
- sal_memset(scPtr, 0, sizeof(and28_shmoo_container_t));
-
- if (phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
- {
- ndx = phy_ndx;
- ndxEnd = phy_ndx + 1;
- }
- else
- {
- ndx = 0;
- ndxEnd = SHMOO_AND28_MAX_INTERFACES;
- }
-
- for (; ndx < ndxEnd; ndx++)
- {
- if (!_shmoo_and28_check_dram(ndx)) {
- continue;
- }
-
- if (action == SHMOO_AND28_ACTION_RESTORE)
- {
- switch(ctlType)
- {
- case SHMOO_AND28_CTL_TYPE_RSVP:
- break;
- case SHMOO_AND28_CTL_TYPE_1:
- _shmoo_and28_restore(unit, phy_ndx, config_param);
- break;
- default:
- if (scPtr != NULL)
- {
- /* sal_free(scPtr); */
- scPtr = NULL;
- }
-
- printf("Unsupported controller type: %02u\n", ctlType);
- return SOC_E_FAIL;
- }
- }
- else if ((action == SHMOO_AND28_ACTION_RUN) || (action == SHMOO_AND28_ACTION_RUN_AND_SAVE))
- {
- switch(ctlType)
- {
- case SHMOO_AND28_CTL_TYPE_RSVP:
- break;
- case SHMOO_AND28_CTL_TYPE_1:
- switch(dramType)
- {
-#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3)
- case SHMOO_AND28_DRAM_TYPE_DDR3:
- seqPtr = &shmoo_order_and28_ddr3[0];
- seqCount = SHMOO_AND28_DDR3_SEQUENCE_COUNT;
- break;
-#endif
-#if (SHMOO_AND28_DRAM_TYPE == SHMOO_AND28_DRAM_TYPE_DDR3L)
- case SHMOO_AND28_DRAM_TYPE_DDR3L:
- seqPtr = &shmoo_order_and28_ddr3l[0];
- seqCount = SHMOO_AND28_DDR3L_SEQUENCE_COUNT;
- break;
-#endif
- default:
- printf("Unsupported dram type: %02u\n", dramType);
- return SOC_E_FAIL;
- }
-
- (*scPtr).dramType = dramType;
- (*scPtr).ctlType = ctlType;
-
- if (shmoo_type != SHMOO_AND28_SHMOO_RSVP)
- {
- (*scPtr).shmooType = shmoo_type;
- _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SINGLE);
- _shmoo_and28_do(unit, ndx, scPtr);
- _shmoo_and28_calib_2D(unit, ndx, scPtr);
- _shmoo_and28_set_new_step(unit, ndx, scPtr);
-#ifdef PLOT_SUPPORT
- if (plot)
- {
- _shmoo_and28_plot(unit, ndx, scPtr);
- }
-#endif
- _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SINGLE);
- }
- else
- {
- for (i = 0; i < seqCount; i++)
- {
- (*scPtr).shmooType = seqPtr[i];
- _shmoo_and28_entry(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL);
- _shmoo_and28_do(unit, ndx, scPtr);
- _shmoo_and28_calib_2D(unit, ndx, scPtr);
- _shmoo_and28_set_new_step(unit, ndx, scPtr);
-#ifdef PLOT_SUPPORT
- if (plot)
- {
- _shmoo_and28_plot(unit, ndx, scPtr);
- }
-#endif
- _shmoo_and28_exit(unit, ndx, scPtr, SHMOO_AND28_SEQUENTIAL);
- }
- }
-
- break;
- default:
- if (scPtr != NULL)
- {
- /* sal_free(scPtr); */
- scPtr = NULL;
- }
-
- printf("Unsupported controller type: %02u\n", ctlType);
- return SOC_E_FAIL;
- }
- }
-
- if ((action == SHMOO_AND28_ACTION_RUN_AND_SAVE) || (action == SHMOO_AND28_ACTION_SAVE))
- {
- _shmoo_and28_save(unit, phy_ndx, config_param);
- }
- }
-
- if (scPtr != NULL)
- {
- /* sal_free(scPtr); */
- scPtr = NULL;
- }
-
- printf("DDR Tuning Complete\n");
- }
- else
- {
- /* Report only */
- switch(ctlType)
- {
- case SHMOO_AND28_CTL_TYPE_RSVP:
- break;
- case SHMOO_AND28_CTL_TYPE_1:
- break;
- default:
- printf("Unsupported controller type: %02u\n", ctlType);
- return SOC_E_FAIL;
- }
- }
- return SOC_E_NONE;
-}
-
-/* Set Dram Parameters/Info to Shmoo driver */
-int
-soc_and28_shmoo_dram_info_set(int unit, and28_shmoo_dram_info_t *sdi)
-{
-
-#if (!SHMOO_AND28_PHY_CONSTANT_CONFIG)
- shmoo_dram_info_ptr = &shmoo_dram_info;
- shmoo_dram_info_ptr->ctl_type = (*sdi).ctl_type;
- shmoo_dram_info_ptr->dram_type = (*sdi).dram_type;
- shmoo_dram_info_ptr->dram_bitmap = (*sdi).dram_bitmap;
- shmoo_dram_info_ptr->interface_bitwidth = (*sdi).interface_bitwidth;
- shmoo_dram_info_ptr->num_columns = (*sdi).num_columns;
- shmoo_dram_info_ptr->num_rows = (*sdi).num_rows;
- shmoo_dram_info_ptr->num_banks = (*sdi).num_banks;
- shmoo_dram_info_ptr->data_rate_mbps = (*sdi).data_rate_mbps;
- shmoo_dram_info_ptr->ref_clk_mhz = (*sdi).ref_clk_mhz;
- shmoo_dram_info_ptr->refi = (*sdi).refi;
- shmoo_dram_info_ptr->command_parity_latency = (*sdi).command_parity_latency;
- shmoo_dram_info_ptr->sim_system_mode = (*sdi).sim_system_mode;
-#endif
- return SOC_E_NONE;
-}
-
-/* Configure PHY PLL and wait for lock */
-int
-_soc_and28_shmoo_phy_cfg_pll(int unit, int phy_ndx)
-{
- int ndx, ndxEnd;
- uint32 data;
- uint32 timeout;
- uint32 pll_config;
- uint32 pll_control2;
- uint32 pll_dividers;
- uint32 pll_frac_divider;
-
- if (shmoo_dram_info_ptr->ref_clk_mhz != 50)
- {
- printf(" Unsupported reference flock frequency: %4d MHz\n", shmoo_dram_info_ptr->ref_clk_mhz);
- return SOC_E_FAIL;
- }
-
- switch(shmoo_dram_info_ptr->data_rate_mbps)
- {
- case 800:
- pll_config = 0x018D0012;
- pll_control2 = 0x94000000;
- pll_dividers = 0x004030C0;
- pll_frac_divider = 0x00000000;
- break;
- case 1066:
- pll_config = 0x018D0012;
- pll_control2 = 0x94000000;
- pll_dividers = 0x003030BF;
- pll_frac_divider = 0x000E147A;
- break;
- case 1333:
- pll_config = 0x018D0012;
- pll_control2 = 0x94000000;
- pll_dividers = 0x002030A0;
- pll_frac_divider = 0x000147AE;
- break;
- case 1600:
- pll_config = 0x018D0012;
- pll_control2 = 0x94000000;
- pll_dividers = 0x002030C0;
- pll_frac_divider = 0x00000000;
- break;
- default:
- printf(" Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
- return SOC_E_FAIL;
- }
-
- printf(" PHY PLL Configuration\n");
- printf(" Fref.............: %4d MHz\n", shmoo_dram_info_ptr->ref_clk_mhz);
- printf(" Data rate........: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
-
- if (phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
- {
- ndx = phy_ndx;
- ndxEnd = phy_ndx + 1;
- }
- else
- {
- ndx = 0;
- ndxEnd = SHMOO_AND28_MAX_INTERFACES;
- }
-
- for (; ndx < ndxEnd; ndx++)
- {
- if (!_shmoo_and28_check_dram(ndx))
- {
- continue;
- }
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, pll_config);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2, pll_control2);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS, pll_dividers);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER, pll_frac_divider);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_CONFIG, RESET, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, data);
-
- timeout = 2000;
- do
- {
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS, &data);
-
- if (DDR_PHY_GET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_STATUS, LOCK))
- {
- printf(" PLL locked.\n");
- break;
- }
-
- if (timeout == 0)
- {
- printf(" PLL not locked!!! (Timeout)\n");
- return SOC_E_TIMEOUT;
- }
-
- timeout--;
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
- }
- while (TRUE);
-
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, PLL_CONFIG, RESET_POST_DIV, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG, data);
- }
-
- return SOC_E_NONE;
-}
-
-int
-soc_and28_shmoo_phy_init(int unit, int phy_ndx)
-{
- int ndx, ndxEnd;
- uint32 data;
- uint32 dfi_ctrl;
- uint32 dram_config;
- uint32 dram_timing1;
- uint32 dram_timing2;
- uint32 dram_timing3;
- uint32 dram_timing4;
- uint32 size1000UI, sizeUI;
- and28_step_size_t ss;
-
- if (phy_ndx != SHMOO_AND28_INTERFACE_RSVP)
- {
- ndx = phy_ndx;
- ndxEnd = phy_ndx + 1;
- }
- else
- {
- ndx = 0;
- ndxEnd = SHMOO_AND28_MAX_INTERFACES;
- }
-
- for (; ndx < ndxEnd; ndx++)
- {
- if (!_shmoo_and28_check_dram(ndx))
- {
- continue;
- }
-
- printf("A Series - PHY Initialization (PHY index: %02d)\n", ndx);
-
-/*A01*/ printf("A01. Turn off CKE\n");
- dfi_ctrl = 0;
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 1);
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS0 , 1);
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CS1 , 1);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_F0))
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE , 0);
- #elif defined(PHY_AND28_E2)
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE0 , 0);
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, DFI_CKE1 , 0);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL, dfi_ctrl);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A02*/ printf("A02. Configure timing parameters\n");
- if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- {
- switch(shmoo_dram_info_ptr->data_rate_mbps)
- {
- case 800:
- dram_timing1 = 0x0F040606;
- dram_timing2 = 0x04060506;
- dram_timing3 = 0x00044068;
- dram_timing4 = 0x00000000;
- break;
- case 1066:
- dram_timing1 = 0x14040707;
- dram_timing2 = 0x04080607;
- dram_timing3 = 0x0004408C;
- dram_timing4 = 0x00000000;
- break;
- case 1333:
- dram_timing1 = 0x18050909;
- dram_timing2 = 0x050A0709;
- dram_timing3 = 0x000450B0;
- dram_timing4 = 0x00000000;
- break;
- case 1600:
- dram_timing1 = 0x1C060B0B;
- dram_timing2 = 0x060C080B;
- dram_timing3 = 0x000460D0;
- dram_timing4 = 0x00000000;
- break;
- default:
- printf("Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
- return SOC_E_FAIL;
- }
- }
- else
- {
- switch(shmoo_dram_info_ptr->data_rate_mbps)
- {
- case 800:
- dram_timing1 = 0x0F040606;
- dram_timing2 = 0x04060506;
- dram_timing3 = 0x00044068;
- dram_timing4 = 0x00000000;
- break;
- case 1066:
- dram_timing1 = 0x14040707;
- dram_timing2 = 0x04080607;
- dram_timing3 = 0x0004408C;
- dram_timing4 = 0x00000000;
- break;
- case 1333:
- dram_timing1 = 0x18040909;
- dram_timing2 = 0x050A0709;
- dram_timing3 = 0x000450B0;
- dram_timing4 = 0x00000000;
- break;
- case 1600:
- dram_timing1 = 0x1C050B0B;
- dram_timing2 = 0x060C080B;
- dram_timing3 = 0x000460D0;
- dram_timing4 = 0x00000000;
- break;
- default:
- printf("Unsupported data rate: %4d Mbps\n", shmoo_dram_info_ptr->data_rate_mbps);
- return SOC_E_FAIL;
- }
- }
-
- dram_config = 0x00001000;
- if (!SHMOO_AND28_PHY_BITWIDTH_IS_32)
- dram_config |= 0x02000000;
- switch(shmoo_dram_info_ptr->num_rows)
- {
- case 4096: dram_config |= 0x00000000; break;
- case 8192: dram_config |= 0x00000010; break;
- case 16384: dram_config |= 0x00000020; break;
- case 32768: dram_config |= 0x00000030; break;
- case 65536: dram_config |= 0x00000040; break;
- default:
- printf("Unsupported number of rows: %d\n", shmoo_dram_info_ptr->num_rows);
- return SOC_E_FAIL;
- }
- switch(shmoo_dram_info_ptr->num_columns)
- {
- case 512: dram_config |= 0x00000000; break;
- case 1024: dram_config |= 0x00000100; break;
- case 2048: dram_config |= 0x00000200; break;
- default:
- printf("Unsupported number of columns: %d\n", shmoo_dram_info_ptr->num_columns);
- return SOC_E_FAIL;
- }
- switch(shmoo_dram_info_ptr->num_banks)
- {
- case 4: dram_config |= 0x00000000; break;
- case 8: dram_config |= 0x00000400; break;
- default:
- printf("Unsupported number of banks: %d\n", shmoo_dram_info_ptr->num_banks);
- return SOC_E_FAIL;
- }
- printf("DRAM config: 0x%X\n", dram_config);
-
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG, dram_config);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1, dram_timing1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2, dram_timing2);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3, dram_timing3);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4, dram_timing4);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A03*/ printf("A03. Configure PHY PLL\n");
- _soc_and28_shmoo_phy_cfg_pll(unit, ndx);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A04*/ printf("A04. Configure reference voltage\n");
-/*R04*/ DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC0, 32);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, DAC1, 32);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN0, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN1, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN2, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VREF_DAC_CONTROL, PDN3, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A05*/ printf("A05. Compute VDL step size\n");
- _and28_calculate_step_size(unit, ndx, &ss);
-
- size1000UI = ss.size1000UI;
- sizeUI = size1000UI / 1000;
- printf(" VDL calibration complete.\n");
- printf(" VDL step size....: %3u.%03u ps\n", (ss.step1000 / 1000), (ss.step1000 % 1000));
- printf(" UI size..........: %3u.%03u steps\n", sizeUI, (size1000UI % 1000));
-
-/*A06*/ printf("A06. Configure ADDR/CTRL VDLs\n");
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, FORCE, 1);
- if (sizeUI > SHMOO_AND28_MAX_VDL_LENGTH)
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, SHMOO_AND28_MAX_VDL_LENGTH - 1);
- }
- else
- {
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VDL_CONTROL_AD00, VDL_STEP, sizeUI);
- }
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N, data);
-
-/*A07*/ printf("A07. Disable Virtual VTT\n");
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CTL_IDLE, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CS_IDLE, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, VIRTUAL_VTT_CONTROL, ENABLE_CKE_IDLE, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL, data);
-
-/*A08*/ printf("A08. ZQ calibration\n");
-/*R08*/ if (shmoo_dram_info_ptr->sim_system_mode)
- {
- printf(" Skipped for emulation\n");
-
- goto SHMOO_AND28_ZQ_CALIBRATION_END;
- }
-
- _and28_zq_calibration(unit, ndx);
-
- SHMOO_AND28_ZQ_CALIBRATION_END:
-
-/*A09*/ printf("A09. Configure Static Pad Control\n");
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL, &data);
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, STATIC_PAD_CTL, IDDQ_CLK1, 1);
- #endif
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, STATIC_PAD_CTL, AUTO_OEB, 1);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A10*/ printf("A10. Configure ODT\n");
- data = 0;
- #if (defined(PHY_AND28_E0) || defined(PHY_AND28_E2))
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT_FORCE_VALUE, 1);
- #elif defined(PHY_AND28_F0)
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT0_FORCE_VALUE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_CONTROL_REGS, WRITE_ODT_CNTRL, ODT1_FORCE_VALUE, 1);
- #endif
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL, data);
-
- data = 0;
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_ENABLE, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_DELAY, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_POST_LENGTH, 2);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, ODT_CONTROL, ODT_PRE_LENGTH, 4);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL, data);
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_ODT_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_ODT_CONTROL, data);
- }
- #endif
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A11*/ printf("A11. Configure Write Pre-/Post-amble\n");
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_POSTAM_BITS, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQ_PREAM_BITS, 1);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS, 0xE);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_POSTAM_BITS, 0);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, WR_PREAMBLE_MODE, DQS_PREAM_BITS, 2);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, data);
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_WR_PREAMBLE_MODE, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_WR_PREAMBLE_MODE, data);
- }
- #endif
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A12*/ printf("A12. Configure Auto Idle\n");
- DDR_PHY_REG_READ(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, &data);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_RXENB_MODE, 3);
- DDR_PHY_SET_FIELD(data, DDR34_CORE_PHY_BYTE_LANE_0, IDLE_PAD_CONTROL, AUTO_DQ_IDDQ_MODE, 3);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, data);
- #if (SHMOO_AND28_PHY_BITWIDTH_IS_32)
- if (shmoo_dram_info_ptr->interface_bitwidth == 32)
- {
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_2_IDLE_PAD_CONTROL, data);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_BYTE_LANE_3_IDLE_PAD_CONTROL, data);
- }
- #endif
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
-/*A13*/ printf("A13. Release PHY control\n");
- DDR_PHY_SET_FIELD(dfi_ctrl, DDR34_CORE_PHY_CONTROL_REGS, DFI_CNTRL, ASSERT_REQ, 0);
- DDR_PHY_REG_WRITE(unit, SHMOO_AND28_PHY_REG_BASE, 0, DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL, data);
- sal_usleep(SHMOO_AND28_SHORT_SLEEP);
-
- printf("A Series - PHY Initialization complete (PHY index: %02d)\n", ndx);
- }
-
- return SOC_E_NONE;
-}
diff --git a/src/soc/broadcom/cygnus/soc.c b/src/soc/broadcom/cygnus/soc.c
deleted file mode 100644
index 090d122..0000000
--- a/src/soc/broadcom/cygnus/soc.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <soc/cygnus.h>
-#include <soc/sdram.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <symbols.h>
-
-static void soc_init(struct device *dev)
-{
- ram_resource(dev, 0, (uintptr_t)_dram/KiB, sdram_size_mb()*(MiB/KiB));
- usb_init();
-}
-
-static void soc_noop(struct device *dev)
-{
-}
-
-static struct device_operations soc_ops = {
- .read_resources = soc_noop,
- .set_resources = soc_noop,
- .enable_resources = soc_noop,
- .init = soc_init,
- .scan_bus = 0,
-};
-
-static void enable_cygnus_dev(struct device *dev)
-{
- dev->ops = &soc_ops;
-}
-
-struct chip_operations soc_broadcom_cygnus_ops = {
- CHIP_NAME("SOC Broadcom Cygnus")
- .enable_dev = enable_cygnus_dev,
-};
diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c
deleted file mode 100644
index 65c9c96..0000000
--- a/src/soc/broadcom/cygnus/spi.c
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <timer.h>
-#include <delay.h>
-#include <stdlib.h>
-#include <spi-generic.h>
-#include <spi_flash.h>
-#include <soc/addressmap.h>
-
-#define IPROC_QSPI_CLK 100000000
-
-/* SPI mode flags */
-#define SPI_CPHA 0x01 /* clock phase */
-#define SPI_CPOL 0x02 /* clock polarity */
-#define SPI_MODE_0 (0|0) /* original MicroWire */
-#define SPI_MODE_1 (0|SPI_CPHA)
-#define SPI_MODE_2 (SPI_CPOL|0)
-#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
-
-#define QSPI_MAX_HZ 50000000
-#define QSPI_MODE SPI_MODE_3
-
-#define QSPI_WAIT_TIMEOUT 200U /* msec */
-
-/* Controller attributes */
-#define SPBR_MIN 8U
-#define SPBR_MAX 255U
-#define NUM_TXRAM 32
-#define NUM_RXRAM 32
-#define NUM_CDRAM 16
-
-/*
- * Register fields
- */
-#define MSPI_SPCR0_MSB_BITS_8 0x00000020
-
-/* BSPI registers */
-#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
-#define BSPI_BUSY_STATUS_REG 0x00c
-
-/* MSPI registers */
-#define MSPI_SPCR0_LSB_REG 0x200
-#define MSPI_SPCR0_MSB_REG 0x204
-#define MSPI_SPCR1_LSB_REG 0x208
-#define MSPI_SPCR1_MSB_REG 0x20c
-#define MSPI_NEWQP_REG 0x210
-#define MSPI_ENDQP_REG 0x214
-#define MSPI_SPCR2_REG 0x218
-#define MSPI_STATUS_REG 0x220
-#define MSPI_CPTQP_REG 0x224
-#define MSPI_TXRAM_REG 0x240
-#define MSPI_RXRAM_REG 0x2c0
-#define MSPI_CDRAM_REG 0x340
-#define MSPI_WRITE_LOCK_REG 0x380
-#define MSPI_DISABLE_FLUSH_GEN_REG 0x384
-
-/*
- * Register access macros
- */
-#define REG_RD(x) read32(x)
-#define REG_WR(x, y) write32((x), (y))
-#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y))
-#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y))
-
-/* QSPI private data */
-struct qspi_priv {
- /* Specified SPI parameters */
- unsigned int max_hz;
- unsigned int spi_mode;
-
- int mspi_enabled;
- int mspi_16bit;
-
- int bus_claimed;
-
- /* Registers */
- void *reg;
-};
-
-static struct qspi_priv qspi_slave;
-
-static struct qspi_priv *to_qspi_slave(const struct spi_slave *slave)
-{
- return &qspi_slave;
-}
-
-static int mspi_enable(struct qspi_priv *priv)
-{
- struct stopwatch sw;
-
- /* Switch to MSPI if not yet */
- if ((REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
- stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
- while (!stopwatch_expired(&sw)) {
- if ((REG_RD(priv->reg + BSPI_BUSY_STATUS_REG) & 1)
- == 0) {
- REG_WR(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG,
- 1);
- udelay(1);
- break;
- }
- udelay(1);
- }
- if (REG_RD(priv->reg + BSPI_MAST_N_BOOT_CTRL_REG) != 1)
- return -1;
- }
- priv->mspi_enabled = 1;
- return 0;
-}
-
-static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
-{
- struct qspi_priv *priv = to_qspi_slave(slave);
-
- if (priv->bus_claimed)
- return -1;
-
- if (!priv->mspi_enabled)
- if (mspi_enable(priv))
- return -1;
-
- /* MSPI: Enable write lock */
- REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 1);
-
- priv->bus_claimed = 1;
-
- return 0;
-}
-
-static void spi_ctrlr_release_bus(const struct spi_slave *slave)
-{
- struct qspi_priv *priv = to_qspi_slave(slave);
-
- /* MSPI: Disable write lock */
- REG_WR(priv->reg + MSPI_WRITE_LOCK_REG, 0);
-
- priv->bus_claimed = 0;
-}
-
-#define RXRAM_16B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + ((i) << 2)) & 0xff)
-#define RXRAM_8B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + \
- ((((i) << 1) + 1) << 2)) & 0xff)
-
-static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
- size_t bytesout, void *din, size_t bytesin)
-{
- struct qspi_priv *priv = to_qspi_slave(slave);
- const u8 *tx = (const u8 *)dout;
- u8 *rx = (u8 *)din;
- unsigned int bytes = bytesout + bytesin;
- unsigned int rx_idx = 0;
- unsigned int tx_idx = 0;
- unsigned int in = 0;
- unsigned int chunk;
- unsigned int queues;
- unsigned int i;
- struct stopwatch sw;
-
- if (!priv->bus_claimed)
- return -1;
-
- if (bytes & 1) {
- /* Use 8-bit queue for odd-bytes transfer */
- if (priv->mspi_16bit) {
- REG_SET(priv->reg + MSPI_SPCR0_MSB_REG,
- MSPI_SPCR0_MSB_BITS_8);
- priv->mspi_16bit = 0;
- }
- } else {
- /* Use 16-bit queue for even-bytes transfer */
- if (!priv->mspi_16bit) {
- REG_CLR(priv->reg + MSPI_SPCR0_MSB_REG,
- MSPI_SPCR0_MSB_BITS_8);
- priv->mspi_16bit = 1;
- }
- }
-
- while (bytes) {
- /* Separate code for 16bit and 8bit transfers for performance */
- if (priv->mspi_16bit) {
- /* Determine how many bytes to process this time */
- chunk = min(bytes, NUM_CDRAM * 2);
- queues = (chunk - 1) / 2 + 1;
- bytes -= chunk;
-
- /* Fill CDRAMs */
- for (i = 0; i < queues; i++)
- REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
- 0xc2);
-
- /* Fill TXRAMs */
- for (i = 0; i < chunk; i++) {
- REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 2),
- (tx && (tx_idx < bytesout)) ?
- tx[tx_idx] : 0xff);
- tx_idx++;
- }
- } else {
- /* Determine how many bytes to process this time */
- chunk = min(bytes, NUM_CDRAM);
- queues = chunk;
- bytes -= chunk;
-
- /* Fill CDRAMs and TXRAMS */
- for (i = 0; i < chunk; i++) {
- REG_WR(priv->reg + MSPI_CDRAM_REG + (i << 2),
- 0x82);
- REG_WR(priv->reg + MSPI_TXRAM_REG + (i << 3),
- (tx && (tx_idx < bytesout)) ?
- tx[tx_idx] : 0xff);
- tx_idx++;
- }
- }
-
- /* Setup queue pointers */
- REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
- REG_WR(priv->reg + MSPI_ENDQP_REG, queues - 1);
-
- /* Deassert CS */
- if (bytes == 0)
- REG_CLR(priv->reg + MSPI_CDRAM_REG +
- ((queues - 1) << 2), 0x0);
-
- /* Kick off */
- REG_WR(priv->reg + MSPI_STATUS_REG, 0);
- REG_WR(priv->reg + MSPI_SPCR2_REG, 0xc0); /* cont | spe */
-
- /* Wait for completion */
- stopwatch_init_msecs_expire(&sw, QSPI_WAIT_TIMEOUT);
- while (!stopwatch_expired(&sw)) {
- if (REG_RD(priv->reg + MSPI_STATUS_REG) & 1)
- break;
- }
- if ((REG_RD(priv->reg + MSPI_STATUS_REG) & 1) == 0) {
- /* Make sure no operation is in progress */
- REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
- udelay(1);
- return -1;
- }
-
- /* Read data */
- if (rx) {
- if (priv->mspi_16bit) {
- for (i = 0; i < chunk; i++) {
- if (rx_idx >= bytesout) {
- rx[in] = RXRAM_16B(priv, i);
- in++;
- }
- rx_idx++;
- }
- } else {
- for (i = 0; i < chunk; i++) {
- if (rx_idx >= bytesout) {
- rx[in] = RXRAM_8B(priv, i);
- in++;
- }
- rx_idx++;
- }
- }
- }
- }
-
- return 0;
-}
-
-static int spi_ctrlr_setup(const struct spi_slave *slave)
-{
- struct qspi_priv *priv = &qspi_slave;
- unsigned int spbr;
-
- priv->max_hz = QSPI_MAX_HZ;
- priv->spi_mode = QSPI_MODE;
- priv->reg = (void *)(IPROC_QSPI_BASE);
- priv->mspi_enabled = 0;
- priv->bus_claimed = 0;
-
- /* MSPI: Basic hardware initialization */
- REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0);
- REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0);
- REG_WR(priv->reg + MSPI_NEWQP_REG, 0);
- REG_WR(priv->reg + MSPI_ENDQP_REG, 0);
- REG_WR(priv->reg + MSPI_SPCR2_REG, 0);
-
- /* MSPI: SCK configuration */
- spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1;
- REG_WR(priv->reg + MSPI_SPCR0_LSB_REG,
- MAX(MIN(spbr, SPBR_MAX), SPBR_MIN));
-
- /* MSPI: Mode configuration (8 bits by default) */
- priv->mspi_16bit = 0;
- REG_WR(priv->reg + MSPI_SPCR0_MSB_REG,
- 0x80 | /* Master */
- (8 << 2) | /* 8 bits per word */
- (priv->spi_mode & 3)); /* mode: CPOL / CPHA */
-
- return 0;
-}
-
-static const struct spi_ctrlr spi_ctrlr = {
- .setup = spi_ctrlr_setup,
- .claim_bus = spi_ctrlr_claim_bus,
- .release_bus = spi_ctrlr_release_bus,
- .xfer = spi_ctrlr_xfer,
- .max_xfer_size = 65535,
-};
-
-const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
- {
- .ctrlr = &spi_ctrlr,
- .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
- .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS,
- },
-};
-
-const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/soc/broadcom/cygnus/timer.c b/src/soc/broadcom/cygnus/timer.c
deleted file mode 100644
index 78d996f..0000000
--- a/src/soc/broadcom/cygnus/timer.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <delay.h>
-#include <soc/addressmap.h>
-#include <timer.h>
-
-#define TIMER_GLB_TIM_CTRL_PRESC_MASK 0x0000FF00
-#define TIMER_GLB_TIM_CTRL_TIM_EN 0x00000001
-#define TIMER_GLB_TIM_CTRL_PRESC 0x0
-/*
- * arm clk is 1GHz, periph_clk=arm_clk/2, tick per usec.
- * arm clk is set by the bootrom. See util/broadcom/unauth.cfg for details.
- */
-#define PERIPH_CLOCK 500
-#define CLOCKS_PER_USEC (PERIPH_CLOCK / \
- (((TIMER_GLB_TIM_CTRL_PRESC & TIMER_GLB_TIM_CTRL_PRESC_MASK) >> 8) + 1))
-
-struct cygnus_timer {
- u32 gtim_glob_low;
- u32 gtim_glob_hi;
- u32 gtim_glob_ctrl;
-};
-
-static struct cygnus_timer * const timer_ptr =
- (void *)IPROC_PERIPH_GLB_TIM_REG_BASE;
-
-static inline uint64_t timer_raw_value(void)
-{
- uint64_t cur_tick;
- uint32_t count_h;
- uint32_t count_l;
-
- do {
- count_h = read32(&timer_ptr->gtim_glob_hi);
- count_l = read32(&timer_ptr->gtim_glob_low);
- cur_tick = read32(&timer_ptr->gtim_glob_hi);
- } while (cur_tick != count_h);
-
- return (cur_tick << 32) + count_l;
-}
-
-void timer_monotonic_get(struct mono_time *mt)
-{
- mono_time_set_usecs(mt, timer_raw_value() / CLOCKS_PER_USEC);
-}
-
-void init_timer(void)
-{
- write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_PRESC);
- write32(&timer_ptr->gtim_glob_low, 0);
- write32(&timer_ptr->gtim_glob_hi, 0);
- write32(&timer_ptr->gtim_glob_ctrl, TIMER_GLB_TIM_CTRL_TIM_EN);
-}
diff --git a/src/soc/broadcom/cygnus/tz.c b/src/soc/broadcom/cygnus/tz.c
deleted file mode 100644
index 644b68b..0000000
--- a/src/soc/broadcom/cygnus/tz.c
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/tz.h>
-
-#define TZPC_TZPCR0SIZE 0x18034000
-#define TZPC_TZPCR0SIZE_MASK 0x000003ff
-
-#define TZPC_TZPCDECPROT0SET 0x18034804
-#define TZPC_TZPCDECPROT0CLR 0x18034808
-#define TZPC_TZPCDECPROT1SET 0x18034810
-#define TZPC_TZPCDECPROT1CLR 0x18034814
-#define TZPC_TZPCDECPROT2SET 0x1803481c
-#define TZPC_TZPCDECPROT2CLR 0x18034820
-
-#define TZPCDECPROT0_MASK 0x000000FF
-#define TZPCDECPROT1_MASK 0x000000FF
-#define TZPCDECPROT2_MASK 0x000000FF
-
-#define AXIIC_Ihost_acp_security 0x1a000008
-#define AXIIC_PCIe0_s0_security 0x1a000010
-#define AXIIC_PCIe1_s0_security 0x1a000014
-#define AXIIC_APBY_s0_security 0x1a00002c
-#define AXIIC_APBZ_s0_security 0x1a000030
-#define AXIIC_APBX_s0_security 0x1a000034
-#define AXIIC_ihost_s0_security 0x1a000038
-#define AXIIC_A9jtag_s0_security 0x1a00003c
-#define AXIIC_APB_W1_security 0x1a000040
-#define AXIIC_APB_W2_security 0x1a000044
-#define AXIIC_APB_W3_security 0x1a000048
-#define AXIIC_APB_W4_security 0x1a00004c
-#define AXIIC_APBR_s0_security 0x1a00006c
-#define AXIIC_APBS_s0_security 0x1a000070
-#define AXIIC_CMICd_s0_security 0x1a000074
-#define AXIIC_mhost0_s0_security 0x1a000078
-#define AXIIC_mhost1_s0_security 0x1a00007c
-#define AXIIC_Crypto_s0_security 0x1a000080
-#define AXIIC_DMU_s0_security 0x1a000084
-#define AXIIC_ext_s0_security 0x1a000088
-#define AXIIC_ext_s1_security 0x1a00008c
-
-#define AXIIC_APBY_s0_security_MASK 0x00003f1f
-#define AXIIC_APBZ_s0_security_MASK 0x0000003f
-#define AXIIC_APBX_s0_security_MASK 0x0000cfff
-#define AXIIC_ext_s0_security_MASK 0xffffffff
-#define AXIIC_ext_s1_security_MASK 0xffffffff
-#define AXIIC_APBR_s0_security_MASK 0x0000436d
-#define AXIIC_APBS_s0_security_MASK 0x000057ee
-#define AXIIC_APB_W1_security_MASK 0x0000ffff
-#define AXIIC_APB_W2_security_MASK 0x0000000f
-#define AXIIC_APB_W3_security_MASK 0x00003fff
-#define AXIIC_APB_W4_security_MASK 0x0000007f
-
-/*
- * Note: the order need to match corresponding definitions for
- * non virtual slave slave_vector in tz.h
- */
-static uint32_t non_virtual_slave_regs[] = {
- AXIIC_Ihost_acp_security,
- AXIIC_PCIe0_s0_security,
- AXIIC_PCIe1_s0_security,
- AXIIC_ihost_s0_security,
- AXIIC_A9jtag_s0_security,
- AXIIC_CMICd_s0_security,
- AXIIC_mhost0_s0_security,
- AXIIC_mhost1_s0_security,
- AXIIC_Crypto_s0_security,
- AXIIC_DMU_s0_security
-};
-
-/*
- * Set master security.
- * Use defines in tz.h for both parameters.
- */
-void tz_set_masters_security(uint32_t masters, uint32_t ns_bit)
-{
- uint32_t val;
-
- /* Check any TZPCDECPROT0 is set and then write to TZPCDECPROT0 */
- if (masters & TZPCDECPROT0_MASK) {
- val = masters & TZPCDECPROT0_MASK;
- if (ns_bit)
- write32((void *)TZPC_TZPCDECPROT0SET, val);
- else
- write32((void *)TZPC_TZPCDECPROT0CLR, val);
- }
- /* Check any TZPCDECPROT1 is set and then write to TZPCDECPROT1 */
- if ((masters >> 8) & TZPCDECPROT1_MASK) {
- val = (masters >> 8) & TZPCDECPROT1_MASK;
- if (ns_bit)
- write32((void *)TZPC_TZPCDECPROT1SET, val);
- else
- write32((void *)TZPC_TZPCDECPROT1CLR, val);
- }
- /* Check any TZPCDECPROT2 is set and then write to TZPCDECPROT2 */
- if ((masters >> 16) & TZPCDECPROT2_MASK) {
- val = (masters >> 16) & TZPCDECPROT2_MASK;
- if (ns_bit)
- write32((void *)TZPC_TZPCDECPROT2SET, val);
- else
- write32((void *)TZPC_TZPCDECPROT2CLR, val);
- }
-}
-
-/*
- * Set non virtual slave security.
- * Use defines in tz.h for both parameters.
- */
-void tz_set_non_virtual_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
-{
- uint32_t i;
- uint32_t total = sizeof(non_virtual_slave_regs) /
- sizeof(non_virtual_slave_regs[0]);
- uint32_t mask = ~(0xffffffff << total);
-
- ns_bit &= 0x1;
- slave_vector = slave_vector & mask;
- for (i = 0; i < total; i++) {
- if (slave_vector & (0x1 << i))
- write32((void *)(non_virtual_slave_regs[i]), ns_bit);
- }
-}
-
-/*
- * Set peripheral security.
- * Use defines in tz.h for both parameters.
- */
-void tz_set_periph_security(uint32_t slave_vector, uint32_t ns_bit)
-{
- uint32_t val;
- uint32_t mask_x = AXIIC_APBX_s0_security_MASK;
- uint32_t mask_y = AXIIC_APBY_s0_security_MASK;
- uint32_t tz_periphs_sec_status =
- (mask_x & read32((void *)AXIIC_APBX_s0_security)) |
- ((mask_y & read32((void *)AXIIC_APBY_s0_security)) << 16);
-
- if (ns_bit == TZ_STATE_SECURE)
- tz_periphs_sec_status &= ~slave_vector;
- else
- tz_periphs_sec_status |= slave_vector;
-
- val = tz_periphs_sec_status & mask_x;
- write32((void *)AXIIC_APBX_s0_security, val);
-
- val = (tz_periphs_sec_status >> 16) & mask_y;
- write32((void *)AXIIC_APBY_s0_security, val);
-}
-
-/*
- * Set sec peripheral security.
- * Use defines in tz.h for both parameters.
- */
-void tz_set_sec_periphs_security(uint32_t slave_vector, uint32_t ns_bit)
-{
- uint32_t val;
- uint32_t mask = AXIIC_APBZ_s0_security_MASK;
- uint32_t tz_sec_periphs_sec_status =
- read32((void *)AXIIC_APBZ_s0_security);
-
- if (ns_bit == TZ_STATE_SECURE)
- tz_sec_periphs_sec_status &= ~slave_vector;
- else
- tz_sec_periphs_sec_status |= slave_vector;
-
- val = tz_sec_periphs_sec_status & mask;
- write32((void *)AXIIC_APBZ_s0_security, val);
-}
-
-/*
- * Set external slave security.
- * Use defines in tz.h for both parameters.
- */
-void tz_set_ext_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
-{
- uint32_t val;
- uint32_t mask_s0 = AXIIC_ext_s0_security_MASK;
- uint32_t mask_s1 = AXIIC_ext_s1_security_MASK;
- uint32_t tz_ext_slaves_sec_status =
- (mask_s0 & read32((void *)AXIIC_ext_s0_security)) |
- ((mask_s1 & read32((void *)AXIIC_ext_s0_security)) << 16);
-
- if (ns_bit == TZ_STATE_SECURE)
- tz_ext_slaves_sec_status &= ~slave_vector;
- else
- tz_ext_slaves_sec_status |= slave_vector;
-
- val = tz_ext_slaves_sec_status & mask_s0;
- write32((void *)AXIIC_ext_s0_security, val);
-
- val = (tz_ext_slaves_sec_status >> 16) & mask_s1;
- write32((void *)AXIIC_ext_s1_security, val);
-}
-
-/*
- * Set cfg slave security
- * Use defines in tz.h for both parameters.
- */
-void tz_set_cfg_slaves_security(uint32_t slave_vector, uint32_t ns_bit)
-{
- uint32_t val;
- uint32_t mask_r = AXIIC_APBR_s0_security_MASK;
- uint32_t mask_s = AXIIC_APBS_s0_security_MASK;
- uint32_t tz_cfg_slaves_sec_status =
- (mask_r & read32((void *)AXIIC_APBR_s0_security)) |
- ((mask_s & read32((void *)AXIIC_APBS_s0_security)) << 16);
-
- if (ns_bit == TZ_STATE_SECURE)
- tz_cfg_slaves_sec_status &= ~slave_vector;
- else
- tz_cfg_slaves_sec_status |= slave_vector;
-
- val = tz_cfg_slaves_sec_status & mask_r;
- write32((void *)AXIIC_APBR_s0_security, val);
-
- val = (tz_cfg_slaves_sec_status >> 16) & mask_s;
- write32((void *)AXIIC_APBS_s0_security, val);
-}
-
-/*
- * Set SRAM secure region
- * parameter 'r0size' specify the secure RAM region in 4KB steps:
- * 0x00000000 = no secure region
- * 0x00000001 = 4KB secure region
- * 0x00000002 = 8KB secure region
- * .......
- * 0x000001FF = 2044KB secure region.
- * 0x00000200 or above sets the entire SRAM to secure regardless of size
- */
-void tz_set_sram_sec_region(uint32_t r0size)
-{
- uint32_t mask = TZPC_TZPCR0SIZE_MASK;
-
- write32((void *)TZPC_TZPCR0SIZE, r0size & mask);
-}
-
-/*
- * Set wrapper security
- * Use defines in tz.h for all parameters.
- */
-void tz_set_wrapper_security(uint32_t wrapper1, uint32_t wrapper2,
- uint32_t wrapper3, uint32_t wrapper4,
- uint32_t ns_bit)
-{
- uint32_t mask_w4 = AXIIC_APB_W4_security_MASK;
- uint32_t mask_w3 = AXIIC_APB_W3_security_MASK;
- uint32_t mask_w2 = AXIIC_APB_W2_security_MASK;
- uint32_t mask_w1 = AXIIC_APB_W1_security_MASK;
- uint32_t tz_wrapper1_sec_status = read32((void *)AXIIC_APB_W1_security);
- uint32_t tz_wrapper2_sec_status = read32((void *)AXIIC_APB_W2_security);
- uint32_t tz_wrapper3_sec_status = read32((void *)AXIIC_APB_W3_security);
- uint32_t tz_wrapper4_sec_status = read32((void *)AXIIC_APB_W4_security);
-
- if (ns_bit == TZ_STATE_SECURE) {
- tz_wrapper1_sec_status &= ~wrapper1;
- tz_wrapper2_sec_status &= ~wrapper2;
- tz_wrapper3_sec_status &= ~wrapper3;
- tz_wrapper4_sec_status &= ~wrapper4;
- } else {
- tz_wrapper1_sec_status |= wrapper1;
- tz_wrapper2_sec_status |= wrapper2;
- tz_wrapper3_sec_status |= wrapper3;
- tz_wrapper4_sec_status |= wrapper4;
- }
- write32((void *)AXIIC_APB_W1_security,
- tz_wrapper1_sec_status & mask_w1);
- write32((void *)AXIIC_APB_W2_security,
- tz_wrapper2_sec_status & mask_w2);
- write32((void *)AXIIC_APB_W3_security,
- tz_wrapper3_sec_status & mask_w3);
- write32((void *)AXIIC_APB_W4_security,
- tz_wrapper4_sec_status & mask_w4);
-}
diff --git a/src/soc/broadcom/cygnus/usb.c b/src/soc/broadcom/cygnus/usb.c
deleted file mode 100644
index 5b93604..0000000
--- a/src/soc/broadcom/cygnus/usb.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (C) 2014 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <delay.h>
-#include <console/console.h>
-#include <soc/cygnus.h>
-
-#define CDRU_USBPHY_CLK_RST_SEL_OFFSET 0x11b4
-#define CDRU_USBPHY2_HOST_DEV_SEL_OFFSET 0x11b8
-#define CDRU_SPARE_REG_0_OFFSET 0x1238
-#define CRMU_USB_PHY_AON_CTRL_OFFSET 0x00028
-#define CDRU_USB_DEV_SUSPEND_RESUME_CTRL_OFFSET 0x1210
-#define CDRU_USBPHY_P2_STATUS_OFFSET 0x1200
-
-#define CDRU_USB_DEV_SUSPEND_RESUME_CTRL_DISABLE 0
-#define PHY2_DEV_HOST_CTRL_SEL_DEVICE 0
-#define PHY2_DEV_HOST_CTRL_SEL_HOST 1
-#define CDRU_USBPHY_P2_STATUS__USBPHY_ILDO_ON_FLAG 1
-#define CDRU_USBPHY_P2_STATUS__USBPHY_PLL_LOCK 0
-#define CRMU_USBPHY_P0_AFE_CORERDY_VDDC 1
-#define CRMU_USBPHY_P0_RESETB 2
-#define CRMU_USBPHY_P1_AFE_CORERDY_VDDC 9
-#define CRMU_USBPHY_P1_RESETB 10
-#define CRMU_USBPHY_P2_AFE_CORERDY_VDDC 17
-#define CRMU_USBPHY_P2_RESETB 18
-
-#define USB2_IDM_IDM_IO_CONTROL_DIRECT_OFFSET 0x0408
-#define USB2_IDM_IDM_IO_CONTROL_DIRECT__clk_enable 0
-#define USB2_IDM_IDM_RESET_CONTROL_OFFSET 0x0800
-#define USB2_IDM_IDM_RESET_CONTROL__RESET 0
-
-#define PLL_LOCK_RETRY_COUNT 1000
-#define MAX_REGULATOR_NAME_LEN 25
-#define NUM_PHYS 3
-
-struct bcm_phy_instance {
- struct phy *generic_phy;
- int port;
- int host_mode; /* 1 - Host, 0 - device */
- int power; /* 1 -powered_on 0 -powered off */
- struct regulator *vbus_supply;
-};
-
-struct bcm_phy_driver {
- void *usbphy_regs;
- void *usb2h_idm_regs;
- void *usb2d_idm_regs;
- int num_phys, idm_host_enabled;
- struct bcm_phy_instance instances[NUM_PHYS];
-};
-
-static struct bcm_phy_driver phy_driver;
-
-static int bcm_phy_init(struct bcm_phy_instance *instance_ptr)
-{
- /* Only PORT 2 is capabale of being device and host
- * Default setting is device, check if it is set to host */
- if (instance_ptr->port == 2) {
- if (instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_HOST)
- write32(phy_driver.usbphy_regs + CDRU_USBPHY2_HOST_DEV_SEL_OFFSET,
- PHY2_DEV_HOST_CTRL_SEL_HOST);
- else
- die("usb device mode unsupported\n");
- }
-
- return 0;
-}
-
-static int bcm_phy_poweron(struct bcm_phy_instance *instance_ptr)
-{
- int clock_reset_flag = 1;
- u32 val;
-
- /* Bring the AFE block out of reset to start powering up the PHY */
- val = read32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET);
- if (instance_ptr->port == 0)
- val |= (1 << CRMU_USBPHY_P0_AFE_CORERDY_VDDC);
- else if (instance_ptr->port == 1)
- val |= (1 << CRMU_USBPHY_P1_AFE_CORERDY_VDDC);
- else if (instance_ptr->port == 2)
- val |= (1 << CRMU_USBPHY_P2_AFE_CORERDY_VDDC);
- write32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET, val);
-
- instance_ptr->power = 1;
-
- /* Check if the port 2 is configured for device */
- if (instance_ptr->port == 2 &&
- instance_ptr->host_mode == PHY2_DEV_HOST_CTRL_SEL_DEVICE)
- die("usb device mode unsupported\n");
-
- val = read32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET);
-
- /* Check if the phy that is configured
- * to provide clock and reset is powered on*/
- if (val >= 0 && val < phy_driver.num_phys) {
- if (phy_driver.instances[val].power == 1)
- clock_reset_flag = 0;
- }
-
- /* if not set the current phy */
- if (clock_reset_flag) {
- val = instance_ptr->port;
- write32(phy_driver.usbphy_regs + CDRU_USBPHY_CLK_RST_SEL_OFFSET,
- val);
- }
-
- if (phy_driver.idm_host_enabled != 1) {
- /* Enable clock to USB and get the USB out of reset */
- setbits_le32(phy_driver.usb2h_idm_regs +
- USB2_IDM_IDM_IO_CONTROL_DIRECT_OFFSET,
- (1 << USB2_IDM_IDM_IO_CONTROL_DIRECT__clk_enable));
- clrbits_le32(phy_driver.usb2h_idm_regs +
- USB2_IDM_IDM_RESET_CONTROL_OFFSET,
- (1 << USB2_IDM_IDM_RESET_CONTROL__RESET));
- phy_driver.idm_host_enabled = 1;
- }
-
- return 0;
-}
-
-static int bcm_phy_probe(void)
-{
- int i;
-
- phy_driver.num_phys = NUM_PHYS;
- phy_driver.usbphy_regs = (void *)0x0301c000;
- phy_driver.usb2h_idm_regs = (void *)0x18115000;
- phy_driver.usb2d_idm_regs = (void *)0x18111000;
- phy_driver.idm_host_enabled = 0;
-
- /* Shutdown all ports. They can be powered up as required */
- clrbits_le32(phy_driver.usbphy_regs + CRMU_USB_PHY_AON_CTRL_OFFSET,
- (1 << CRMU_USBPHY_P0_AFE_CORERDY_VDDC) |
- (1 << CRMU_USBPHY_P0_RESETB) |
- (1 << CRMU_USBPHY_P1_AFE_CORERDY_VDDC) |
- (1 << CRMU_USBPHY_P1_RESETB) |
- (1 << CRMU_USBPHY_P2_AFE_CORERDY_VDDC) |
- (1 << CRMU_USBPHY_P2_RESETB));
-
- for (i = 0; i < phy_driver.num_phys; i++) {
- phy_driver.instances[i].port = i;
- phy_driver.instances[i].host_mode = PHY2_DEV_HOST_CTRL_SEL_HOST;
- }
-
- return 0;
-}
-
-void usb_init(void)
-{
- bcm_phy_probe();
- /* currently, we only need thus support port 0 */
- bcm_phy_init(&phy_driver.instances[0]);
- bcm_phy_poweron(&phy_driver.instances[0]);
- printk(BIOS_INFO, "usb phy[%d] is powered on\n", 0);
-}
diff --git a/src/soc/broadcom/cygnus/ydc_ddr_bist.c b/src/soc/broadcom/cygnus/ydc_ddr_bist.c
deleted file mode 100644
index 5eaa221..0000000
--- a/src/soc/broadcom/cygnus/ydc_ddr_bist.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-* GNU General Public License for more details.
-*/
-
-#include <soc/cygnus_types.h>
-#include <console/console.h>
-
-#define SOC_IF_ERROR_RETURN(x) (x)
-#define sal_alloc(x,y) malloc(x)
-#define sal_memset(x,y,z) memset(x,y,z)
-#define sal_free(x) free(x)
-#define sal_usleep(x) udelay(x)
-
-/* BEGIN: TEMPORARY */
-#ifndef BCM_AND28_SUPPORT
-#define BCM_AND28_SUPPORT
-#endif
-/* END: TEMPORARY */
-
-#ifdef BCM_AND28_SUPPORT
-#include <soc/shmoo_and28/ydc_ddr_bist.h>
-#include <soc/shmoo_and28/phy_reg_access.h>
-#endif
-
-/* BEGIN: HELPER FUNCTIONS */
-static uint32
-_get_random28(void)
-{
- static uint32 m_w = 6483; /* must not be zero */
- static uint32 m_z = 31245; /* must not be zero */
-
- m_z = 36969 * (m_z & 65535) + (m_z >> 16);
- m_w = 18000 * (m_w & 65535) + (m_w >> 16);
- return (m_z << 16) + m_w; /* 32-bit result */
-}
-/* END: HELPER FUNCTIONS */
-
-int
-soc_ydc_ddr_bist_config_set(int unit, int phy_ndx, ydc_ddr_bist_info_t *bist_info)
-{
- uint32 data;
-
- READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, WRITE_WEIGHT, (*bist_info).write_weight);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, READ_WEIGHT, (*bist_info).read_weight);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PATTERN_BIT_MODE, 0);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, PRBS_MODE, (*bist_info).prbs_mode);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, CONS_ADDR_8_BANKS, 1);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, ADDRESS_SHIFT_MODE, 0);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_SHIFT_MODE, 0);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, DATA_ADDR_MODE, 0);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, IND_WR_RD_ADDR_MODE, 1);
- WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- if (!((*bist_info).prbs_mode))
- {
- if ((*bist_info).mpr_mode)
- {
- if (YDC_DDR_BIST_PHY_BITWITDH_IS_32)
- {
- WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFFFFFF);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0x00000000);
- }
- else
- {
- WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, 0xFFFF0000);
- }
- }
- else
- {
- WRITE_YDC_DDR_BIST_PATTERN_WORD_0r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_1r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_2r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_3r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_4r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_5r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_6r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- WRITE_YDC_DDR_BIST_PATTERN_WORD_7r(0, YDC_DDR_BIST_REG_BASE, _get_random28());
- }
- }
-
- READ_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, NUMBER_OF_ACTIONS, BIST_NUM_ACTIONS, (*bist_info).bist_num_actions);
- WRITE_YDC_DDR_BIST_NUMBER_OF_ACTIONSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- READ_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, START_ADDRESS, BIST_START_ADDRESS, (*bist_info).bist_start_address);
- WRITE_YDC_DDR_BIST_START_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- READ_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, END_ADDRESS, BIST_END_ADDRESS, (*bist_info).bist_end_address);
- WRITE_YDC_DDR_BIST_END_ADDRESSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- return SOC_E_NONE;
-}
-
-int
-soc_ydc_ddr_bist_run(int unit, int phy_ndx, ydc_ddr_bist_err_cnt_t *error_count)
-{
- uint32 data;
- uint32 poll_count;
-
- READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 1);
- WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- poll_count = 0;
-
- while (TRUE)
- {
- READ_YDC_DDR_BIST_STATUSESr(0, YDC_DDR_BIST_REG_BASE, &data);
-
- if (YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, STATUSES, BIST_FINISHED))
- {
- READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
- WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
- break;
- }
-
- if (poll_count > YDC_DDR_BIST_POLL_COUNT_LIMIT)
- {
- READ_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, &data);
- YDC_DDR_BIST_SET_FIELD(data, YDC_DDR_BIST, CONFIGURATIONS, BIST_EN, 0);
- WRITE_YDC_DDR_BIST_CONFIGURATIONSr(0, YDC_DDR_BIST_REG_BASE, data);
-
- printk(BIOS_ERR, "ERROR: YDC DDR BIST timeout!!!\n");
- return SOC_E_TIMEOUT;
- }
-
- poll_count++;
- sal_usleep(YDC_DDR_BIST_POLL_INTERVAL_US);
- }
-
- READ_YDC_DDR_BIST_ERROR_OCCURREDr(0, YDC_DDR_BIST_REG_BASE, &data);
- (*error_count).bist_err_occur = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, ERROR_OCCURRED, ERR_OCCURRED);
-
- READ_YDC_DDR_BIST_FULL_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
- (*error_count).bist_full_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, FULL_MASK_ERROR_COUNTER, FULL_ERR_CNT);
-
- READ_YDC_DDR_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
- (*error_count).bist_single_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, SINGLE_BIT_MASK_ERROR_COUNTER, SINGLE_ERR_CNT);
-
- READ_YDC_DDR_BIST_GLOBAL_ERROR_COUNTERr(0, YDC_DDR_BIST_REG_BASE, &data);
- (*error_count).bist_global_err_cnt = YDC_DDR_BIST_GET_FIELD(data, YDC_DDR_BIST, GLOBAL_ERROR_COUNTER, GLOBAL_ERR_CNT);
-
- return SOC_E_NONE;
-}
diff --git a/util/README.md b/util/README.md
index 7cdb5e5..2fe0afc 100644
--- a/util/README.md
+++ b/util/README.md
@@ -16,7 +16,6 @@
`Yacc`
* __board_status__ - Tools to collect logs and upload them to the board
status repository `Bash` `Go`
-* __broadcom__ - Generate Broadcom secure boot image. `C`
* __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
file `Python`
* __cbfstool__
diff --git a/util/broadcom/Makefile.inc b/util/broadcom/Makefile.inc
deleted file mode 100644
index 4ec8a52..0000000
--- a/util/broadcom/Makefile.inc
+++ /dev/null
@@ -1 +0,0 @@
-subdirs-$(CONFIG_SOC_BROADCOM_CYGNUS) += secimage
diff --git a/util/broadcom/description.md b/util/broadcom/description.md
deleted file mode 100644
index 572b412..0000000
--- a/util/broadcom/description.md
+++ /dev/null
@@ -1 +0,0 @@
-Generate Broadcom secure boot image. `C`
diff --git a/util/broadcom/khmacsha256 b/util/broadcom/khmacsha256
deleted file mode 100644
index c491120..0000000
--- a/util/broadcom/khmacsha256
+++ /dev/null
Binary files differ
diff --git a/util/broadcom/secimage/Makefile b/util/broadcom/secimage/Makefile
deleted file mode 100644
index ab8a1a4..0000000
--- a/util/broadcom/secimage/Makefile
+++ /dev/null
@@ -1,42 +0,0 @@
-#
-# Copyright (C) 2015 Broadcom Corporation
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation version 2.
-#
-# This program is distributed "as is" WITHOUT ANY WARRANTY of any
-# kind, whether express or implied; without even the implied warranty
-# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-
-TARGET = secimage
-OBJS = crypto.o io.o misc.o sbi.o
-CC = gcc
-RM = rm
-CFLAGS += -Wall -g
-
-LIBS = -lssl -lcrypto -lz
-
-%.o : %.c
- $(CC) -c $(CFLAGS) -o $@ $<
-
-all: $(TARGET)
-
-$(TARGET): $(OBJS)
- $(CC) -o $@ $(OBJS) $(LIBS)
-
-install:
- install -d $(DESTDIR)/usr/bin
- install $(TARGET) $(DESTDIR)/usr/bin
-
-.PHONY: test
-test: $(TARGET)
- @find test -maxdepth 1 -type f -executable \
- | xargs -I "{}" sh -c "{} $$(realpath $<)"
-
-.PHONY: clean distclean
-
-clean distclean:
- $(RM) -f $(TARGET) $(OBJS)
diff --git a/util/broadcom/secimage/Makefile.inc b/util/broadcom/secimage/Makefile.inc
deleted file mode 100644
index fefe576..0000000
--- a/util/broadcom/secimage/Makefile.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-secimageobj :=
-secimageobj += crypto.o
-secimageobj += io.o
-secimageobj += misc.o
-secimageobj += sbi.o
-
-LIBS = -lssl -lcrypto -lz
-
-additional-dirs += $(objutil)/broadcom/secimage
-
-$(objutil)/broadcom/secimage/%.o: $(top)/util/broadcom/secimage/%.c
- printf " HOSTCC $(subst $(objutil)/,,$(@))\n"
- $(HOSTCC) $(HOSTCFLAGS) -c -o $@ $<
-
-$(objutil)/broadcom/secimage/secimage: \
- $(addprefix $(objutil)/broadcom/secimage/,$(secimageobj))
- printf " HOSTCC $(subst $(objutil)/,,$(@)) (link)\n"
- $(HOSTCC) -o $@ $^ $(LIBS)
diff --git a/util/broadcom/secimage/crypto.c b/util/broadcom/secimage/crypto.c
deleted file mode 100644
index 2fe52b6..0000000
--- a/util/broadcom/secimage/crypto.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include <stdint.h>
-#include "secimage.h"
-#include <openssl/hmac.h>
-
-/*----------------------------------------------------------------------
- * Name : HmacSha256Hash
- * Purpose :
- * Input : none
- * Output : none
- *---------------------------------------------------------------------*/
-int HmacSha256Hash(uint8_t *data, uint32_t len, uint8_t *hash, uint8_t *key)
-{
- unsigned int hash_len = 0;
-
- if (!HMAC(EVP_sha256(), key, 32, data, len, hash, &hash_len)) {
- printf("HMAC failed\n");
- return -1;
- } else if (hash_len != 32) {
- printf("HMAC reported unexpected md_len of %u\n", hash_len);
- return -2;
- }
-
- return 0;
-}
-
-/*----------------------------------------------------------------------
- * Name : AppendHMACSignature
- * Purpose : Appends HMAC signature at the end of the data
- *---------------------------------------------------------------------*/
-int AppendHMACSignature(uint8_t *data, uint32_t length, char *filename,
- uint32_t offset)
-{
- uint8_t hmackey[32];
- uint32_t len;
- uint32_t status;
- uint8_t *digest = data + length;
-
- len = ReadBinaryFile(filename, hmackey, 32);
- if (len != 32) {
- printf("Error reading hmac key file\n");
- return 0;
- }
-
- status = HmacSha256Hash(&data[offset], length - offset, digest,
- hmackey);
-
- if (status) {
- printf("HMAC-SHA256 hash error\n");
- return 0;
- }
-
- return 32;
-}
diff --git a/util/broadcom/secimage/io.c b/util/broadcom/secimage/io.c
deleted file mode 100644
index f5be50a..0000000
--- a/util/broadcom/secimage/io.c
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include "secimage.h"
-
-/*----------------------------------------------------------------------
- * Name : ReadBinaryFile
- * Purpose : Read some data from file of raw binary
- * Input : fname : file to be read
- * buf : buffer which is the data desitnation
- * maxlen : maiximum length of data to be read
- * Output : none
- *---------------------------------------------------------------------*/
-int ReadBinaryFile(char *fname, uint8_t *buf, int maxlen)
-{
- FILE *fp = NULL;
- int len = 0;
-
- fp = fopen(fname, "rb");
- if (fp == NULL)
- return 0;
- printf("fname=%s, len=%d\n", fname, maxlen);
- len = fread(buf, 1, maxlen, fp);
- fclose(fp);
-
- return len;
-}
-
-/*----------------------------------------------------------------------
- * Name : FileSizeGet
- * Purpose : Return the size of the file
- * Input : file: FILE * to the file to be processed
- * Output : none
- *---------------------------------------------------------------------*/
-size_t FileSizeGet(FILE *file)
-{
- long length;
-
- fseek(file, 0, SEEK_END);
- length = ftell(file);
- rewind(file);
- return (size_t)length;
-}
-
-/*----------------------------------------------------------------------
- * Name : DataRead
- * Purpose : Read all the data from a file
- * Input : filename : file to be read
- * buf : buffer which is the data destination
- * length : length of data to be read
- * Output : none
- *---------------------------------------------------------------------*/
-int DataRead(char *filename, uint8_t *buf, int *length)
-{
- FILE *file;
- int len = *length;
-
- file = fopen(filename, "rb");
- if (file == NULL) {
- printf("Unable to open file: %s\n", filename);
- return -1;
- }
- len = FileSizeGet(file);
- if (len < 0) {
- printf("Unable to seek in file: %s\n", filename);
- fclose(file);
- return -1;
- }
- if (len < *length)
- *length = len;
- else
- /* Do not exceed the maximum length of the buffer */
- len = *length;
- if (fread((uint8_t *)buf, 1, len, file) != len) {
- printf("Error reading data (%d bytes) from file: %s\n",
- len, filename);
- fclose(file);
- return -1;
- }
- fclose(file);
- return 0;
-}
-
-/*----------------------------------------------------------------------
- * Name : DataWrite
- * Purpose : Write some binary data to a file
- * Input : filename : file to be written
- * buf : buffer which is the data source
- * length : length of data to be written
- * Output : none
- *---------------------------------------------------------------------*/
-int DataWrite(char *filename, char *buf, int length)
-{
- FILE *file;
-
- file = fopen(filename, "wb");
- if (file == NULL) {
- printf("Unable to open output file %s\n", filename);
- return -1;
- }
- if (fwrite(buf, 1, length, file) < length) {
- printf("Unable to write %d bytes to output file %s (0x%X).\n",
- length, filename, ferror(file));
- fclose(file);
- return -1;
- }
-
- fflush(file);
- fclose(file);
- return 0;
-}
diff --git a/util/broadcom/secimage/misc.c b/util/broadcom/secimage/misc.c
deleted file mode 100644
index 0d0cf0b..0000000
--- a/util/broadcom/secimage/misc.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdio.h>
-#include <string.h>
-#include "secimage.h"
-
-static unsigned char filebuffer[2049];
-
-void FillHeaderFromConfigFile(char *h, char *ConfigFileName)
-{
-
- int byte_count = 0;
- char *ptr;
- FILE *fp;
- unsigned int Tag;
- unsigned int Length;
- unsigned int Reserved;
- HEADER *h1 = (HEADER *)h;
-
- fp = fopen(ConfigFileName, "rb");
- if (fp != NULL) {
- printf("\r\n Reading config information from file \r\n");
- byte_count = fread(filebuffer, 1, 2048, fp);
- filebuffer[2048] = 0;
- if (byte_count > 0) {
- ptr = strstr((char *)filebuffer, "Tag=");
- if (ptr) {
- ptr += strlen("Tag=");
- sscanf(ptr, "%x", &Tag);
- h1->Tag = Tag;
- }
- ptr = strstr((char *)filebuffer, "Length=");
- if (ptr) {
- ptr += strlen("Length=");
- sscanf(ptr, "%x", &Length);
- h1->Length = Length;
- }
- ptr = strstr((char *)filebuffer, "Reserved=");
- if (ptr) {
- ptr += strlen("Reserved=");
- sscanf(ptr, "%x", &Reserved);
- h1->Reserved = Reserved;
- }
- }
- fclose(fp);
- }
-}
diff --git a/util/broadcom/secimage/sbi.c b/util/broadcom/secimage/sbi.c
deleted file mode 100644
index f156ed5..0000000
--- a/util/broadcom/secimage/sbi.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <zlib.h>
-#include "secimage.h"
-
-#define MIN_SIZE (1024*120)
-
-/*----------------------------------------------------------------------
- * Name : SBIUsage
- * Purpose :
- * Input : none
- * Output : none
- *---------------------------------------------------------------------*/
-int SBIUsage(void)
-{
- printf("\nTo create a Secure Boot Image:\n");
- printf("secimage: -out <output binary> [-hmac hmac_binary_key] <-config configfile>");
- printf("\n\t\t[-bl input binary]\n");
- return 0;
-}
-
-/*----------------------------------------------------------------------
- * Name : AddImagePayload
- * Purpose :
- * Input : none
- * Output : none
- *---------------------------------------------------------------------*/
-int AddImagePayload(char *h, char *filename, unsigned int filesize)
-{
- uint32_t totalLen;
- int length = filesize;
- int padlen = 0;
- int status = 0;
-
- totalLen = 0x40;
-
- status = DataRead(filename, (uint8_t *)h + totalLen, &length);
- printf("\r\n Adding file %s ... \r\n", filename);
- if (!status) {
- if (length & 15) {
- padlen = 16 - (length & 15);
- memset((uint8_t *)h + totalLen + length, 0, padlen);
- length += padlen;
- }
-
- *(uint32_t *)&h[FIELD5_OFFSET] = length;
- *(uint32_t *)&h[FIELD6_OFFSET] += length;
-
- } else
- printf("Error reading image Payload from %s\n", filename);
-
- return status;
-}
-
-/*----------------------------------------------------------------------
- * Name : CreateSecureBootImage
- * Purpose :
- * Input : none
- * Output : none
- *---------------------------------------------------------------------*/
-int CreateSecureBootImage(int ac, char **av)
-{
- char *configfile = NULL, *arg, *privkey = NULL, *bl = NULL;
- int status = 0;
- uint32_t sbiLen;
- struct stat file_stat;
- uint32_t add_header = 1;
- char *outfile = *av;
- unsigned int filesize;
- char *buf;
- --ac; ++av;
-
- if (ac <= 0)
- return SBIUsage();
-
- while (ac) {
- arg = *av;
- if (!strcmp(arg, "-bl")) {
- --ac, ++av;
- bl = *av;
- } else if (!strcmp(arg, "-hmac")) {
- --ac, ++av;
- privkey = *av;
- } else if (!strcmp(arg, "-config")) {
- --ac, ++av;
- configfile = *av;
- } else if (!strcmp(arg, "-noheader")) {
- add_header = 0;
- } else {
- return SBIUsage();
- }
- --ac, ++av;
- }
-
- if (!bl) {
- puts("-bl not set");
- return -1;
- }
-
- if (!privkey) {
- puts("-hmac not set");
- return -1;
- }
-
- if (stat(bl, &file_stat) == -1) {
- puts("Can't stat bl");
- return -1;
- }
- filesize = file_stat.st_size + MIN_SIZE;
- buf = calloc(sizeof(uint8_t), filesize);
-
- if (buf == NULL) {
- puts("Memory allocation error");
- status = -1;
- goto done;
- }
-
- *(uint32_t *)&buf[FIELD6_OFFSET] = 0x40;
- *(uint32_t *)&buf[FIELD9_OFFSET] = 0x45F2D99A;
- *(uint32_t *)&buf[FIELD3_OFFSET] = 0x900FFFFF;
- *(uint16_t *)&buf[FIELD1_OFFSET] = 0x40;
- *(uint32_t *)&buf[FIELD4_OFFSET] = 0x40;
- *(uint16_t *)&buf[FIELD2_OFFSET] = 0x10;
- *(uint16_t *)&buf[FIELD8_OFFSET] = 0x20;
- *(uint16_t *)&buf[FIELD7_OFFSET] = 0x10;
-
- if (status == 0) {
-
- if (configfile)
- FillHeaderFromConfigFile(buf, configfile);
-
- status = AddImagePayload(buf, bl, filesize);
- if (status) {
- status = -1;
- goto done;
- }
-
- sbiLen = *(uint32_t *)&buf[FIELD6_OFFSET];
-
- printf("HMAC signing %d bytes\n", sbiLen);
- status = AppendHMACSignature((uint8_t *)buf, sbiLen, privkey,
- add_header ? 0x10 : 0x40);
- if (status > 0) {
- sbiLen += status;
- status = 0;
- }
-
- if (!status) {
- ((HEADER *)buf)->Length = sbiLen;
- ((HEADER *)buf)->crc = crc32(0xFFFFFFFF,
- (uint8_t *)buf, 12);
-
- printf("Generating Image file %s: %d bytes\n",
- outfile, sbiLen);
- if (!add_header)
- status = DataWrite(outfile, &buf[0x40],
- sbiLen - 0x40);
- else
- status = DataWrite(outfile, buf, sbiLen);
- }
- }
- if (status < 0)
- printf("Generation error %d\n", status);
-
-done:
- free(buf);
- return status;
-}
-
-int main(int argc, char **argv)
-{
- argc--;
- argv++;
- if (argc > 0) {
- if (!strcmp(*argv, "-out"))
- return CreateSecureBootImage(--argc, ++argv);
- }
- SBIUsage();
- return 0;
-}
diff --git a/util/broadcom/secimage/secimage.h b/util/broadcom/secimage/secimage.h
deleted file mode 100644
index 395e66a..0000000
--- a/util/broadcom/secimage/secimage.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SECIMAGE_H_
-#define _SECIMAGE_H_
-
-#include <stdint.h>
-#include <sys/types.h>
-
-#define FIELD1_OFFSET 16
-#define FIELD2_OFFSET 18
-#define FIELD3_OFFSET 20
-#define FIELD4_OFFSET 36
-#define FIELD5_OFFSET 40
-#define FIELD6_OFFSET 44
-#define FIELD7_OFFSET 48
-#define FIELD8_OFFSET 50
-#define FIELD9_OFFSET 60
-
-typedef struct Header_t {
- uint32_t Tag;
- uint32_t Length;
- uint32_t Reserved;
- uint32_t crc;
-} HEADER;
-
-int DataWrite(char *filename, char *buf, int length);
-int DataRead(char *filename, uint8_t *buf, int *length);
-int AppendHMACSignature(uint8_t *data, uint32_t length, char *filename,
- uint32_t offset);
-int ReadBinaryFile(char *fname, uint8_t *buf, int maxlen);
-void FillHeaderFromConfigFile(char *h, char *ConfigFileName);
-
-#endif /* _SECIMAGE_H_ */
diff --git a/util/broadcom/secimage/test/data/expected/binary.xxdump b/util/broadcom/secimage/test/data/expected/binary.xxdump
deleted file mode 100644
index 0a1bbff..0000000
--- a/util/broadcom/secimage/test/data/expected/binary.xxdump
+++ /dev/null
@@ -1,1097 +0,0 @@
-00000000: a5a5 a5a5 9044 0000 0200 0000 db01 0f4b .....D.........K |
-00000010: 4000 1000 ffff 0f90 0000 0000 0000 0000 @............... |
-00000020: 0000 0000 4000 0000 3044 0000 7044 0000 ....@...0D..pD.. |
-00000030: 1000 2000 0000 0000 0000 0000 9ad9 f245 .. ............E |
-00000040: dff0 2be3 4c00 00fa 342e 362d 3234 3830 ..+.L...4.6-2480 |
-00000050: 2d67 6430 3738 3530 3938 6632 3931 2d64 -gd0785098f291-d |
-00000060: 6972 7479 0047 6f6f 676c 6500 5075 7269 irty.Google.Puri |
-00000070: 6e00 3a00 0000 1d00 0000 1600 0000 0000 n.:............. |
-00000080: 2000 0000 0000 0000 0000 0000 0000 0000 ............... |
-00000090: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000000a0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000000b0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000000c0: 0600 00ea 0700 00ea 0800 00ea 0900 00ea ................ |
-000000d0: 0a00 00ea 0b00 00ea 0c00 00ea 0d00 00ea ................ |
-000000e0: 78d0 9fe5 0d00 00ea 60d0 9fe5 0b00 00ea x.......`....... |
-000000f0: 5cd0 9fe5 0900 00ea 58d0 9fe5 0700 00ea \.......X....... |
-00000100: 54d0 9fe5 0500 00ea 50d0 9fe5 0300 00ea T.......P....... |
-00000110: 4cd0 9fe5 0100 00ea 48d0 9fe5 ffff ffea L.......H....... |
-00000120: 48d0 8fe5 40d0 9fe5 04e0 2de5 0060 4de9 H...@.....-..`M. |
-00000130: 08d0 4de2 ff1f 2de9 0d00 a0e1 0fe0 a0e1 ..M...-......... |
-00000140: 28f0 9fe5 ff1f bde8 08d0 8de2 0080 fde8 (............... |
-00000150: e1a8 0002 0da9 0002 35a9 0002 91a9 0002 ........5....... |
-00000160: eda9 0002 15aa 0002 41aa 0002 0000 0000 ........A....... |
-00000170: 0000 0000 0cee 100f 7047 00bf 8246 00f0 ........pG...F.. |
-00000180: 43f8 10ee b01f 01f0 0301 0029 11d1 0a48 C..........)...H |
-00000190: 0a49 0b4a 0260 00f1 0400 8842 fad1 0948 .I.J.`.....B...H |
-000001a0: c0f8 00a0 dff8 14d0 4ff0 0000 84b0 02f0 ........O....... |
-000001b0: 7efa 30bf f746 0000 0030 0302 0060 0302 ~.0..F...0...`.. |
-000001c0: efbe adde 20e7 0002 11ee 103f 43f0 0503 .... ......?C... |
-000001d0: 01ee 103f bff3 6f8f 7047 08b5 11ee 103f ...?..o.pG.....? |
-000001e0: 5a07 09d5 00f0 76f8 0023 07ee 153f bff3 Z.....v..#...?.. |
-000001f0: 4f8f bff3 6f8f 08bd db04 f5d5 00f0 baf8 O...o........... |
-00000200: f2e7 fff7 eabf 0000 7546 11ee 104f 44f4 ........uF...OD. |
-00000210: c054 01ee 104f 00f0 0df8 24f0 0704 01ee .T...O....$..... |
-00000220: 104f 07ee 150f 08ee 170f bff3 4f8f bff3 .O..........O... |
-00000230: 6f8f 2847 bff3 4f8f 6ff0 0103 03f1 0203 o.(G..O.o....... |
-00000240: 30ee 300f 00f0 e06c 4fea dc5c 6345 37da 0.0....lO..\cE7. |
-00000250: 03eb 5302 20fa 02f1 01f0 0701 0229 eddb ..S. ........).. |
-00000260: 40ee 103f bff3 6f8f 30ee 100f c0f3 020c @..?..o.0....... |
-00000270: 0cf1 040c c0f3 4e32 02fa 0cf2 43ea 0203 ......N2....C... |
-00000280: 4ff0 0101 01fa 0cf1 c0f3 c90c bcfa 8cf2 O............... |
-00000290: 0cfa 02fc 4ff0 0100 00fa 02f2 1846 43ea ....O........FC. |
-000002a0: 0c03 6ff3 0300 a2eb 0002 07ee 563f 0f2b ..o.........V?.+ |
-000002b0: c4d9 4fea 1310 8003 14bf 5b1a 9b1a f4e7 ..O.......[..... |
-000002c0: 4ff0 0000 40ee 100f bff3 4f8f bff3 6f8f O...@.....O...o. |
-000002d0: 7047 00bf bff3 4f8f 6ff0 0103 03f1 0203 pG....O.o....... |
-000002e0: 30ee 300f 00f0 e06c 4fea dc5c 6345 37da 0.0....lO..\cE7. |
-000002f0: 03eb 5302 20fa 02f1 01f0 0701 0229 eddb ..S. ........).. |
-00000300: 40ee 103f bff3 6f8f 30ee 100f c0f3 020c @..?..o.0....... |
-00000310: 0cf1 040c c0f3 4e32 02fa 0cf2 43ea 0203 ......N2....C... |
-00000320: 4ff0 0101 01fa 0cf1 c0f3 c90c bcfa 8cf2 O............... |
-00000330: 0cfa 02fc 4ff0 0100 00fa 02f2 1846 43ea ....O........FC. |
-00000340: 0c03 6ff3 0300 a2eb 0002 07ee 5a3f 0f2b ..o.........Z?.+ |
-00000350: c4d9 4fea 1310 8003 14bf 5b1a 9b1a f4e7 ..O.......[..... |
-00000360: 4ff0 0000 40ee 100f bff3 4f8f bff3 6f8f O...@.....O...o. |
-00000370: 7047 00bf bff3 4f8f 6ff0 0103 03f1 0203 pG....O.o....... |
-00000380: 30ee 300f 00f0 e06c 4fea dc5c 6345 37da 0.0....lO..\cE7. |
-00000390: 03eb 5302 20fa 02f1 01f0 0701 0229 eddb ..S. ........).. |
-000003a0: 40ee 103f bff3 6f8f 30ee 100f c0f3 020c @..?..o.0....... |
-000003b0: 0cf1 040c c0f3 4e32 02fa 0cf2 43ea 0203 ......N2....C... |
-000003c0: 4ff0 0101 01fa 0cf1 c0f3 c90c bcfa 8cf2 O............... |
-000003d0: 0cfa 02fc 4ff0 0100 00fa 02f2 1846 43ea ....O........FC. |
-000003e0: 0c03 6ff3 0300 a2eb 0002 07ee 5e3f 0f2b ..o.........^?.+ |
-000003f0: c4d9 4fea 1310 8003 14bf 5b1a 9b1a f4e7 ..O.......[..... |
-00000400: 4ff0 0000 40ee 100f bff3 4f8f bff3 6f8f O...@.....O...o. |
-00000410: 7047 00bf f8b5 0546 124e 0024 124f 0f2c pG.....F.N.$.O., |
-00000420: 0dd1 1249 0320 01f0 45fa 55f8 2420 0320 ...I. ..E.U.$ . |
-00000430: 0f49 0134 01f0 3efa 102c f0d1 f8bd 0e2c .I.4..>..,....., |
-00000440: 01d1 0c49 eee7 0d2c 01d1 0b49 eae7 0c2c ...I...,...I..., |
-00000450: 01d1 3946 e6e7 2246 3146 0320 01f0 2afa ..9F.."F1F. ..*. |
-00000460: e3e7 00bf 4adc 0002 47dc 0002 3edc 0002 ....J...G...>... |
-00000470: 4edc 0002 41dc 0002 44dc 0002 2de9 f843 N...A...D...-..C |
-00000480: 20f0 1f06 1249 0320 01f0 14fa dff8 4c80 ....I. ......L. |
-00000490: 104f 8024 06eb 8402 4146 0320 04f1 0709 .O.$....AF. .... |
-000004a0: 01f0 08fa 2546 4d45 09dd 0b49 0320 083c ....%FME...I. .< |
-000004b0: 01f0 00fa 14f1 080f ecd1 bde8 f883 56f8 ..............V. |
-000004c0: 2520 3946 0320 0135 01f0 f4f9 ebe7 00bf % 9F. .5........ |
-000004d0: 18db 0002 2ddb 0002 03e2 0002 28db 0002 ....-.......(... |
-000004e0: 0446 0849 08b5 0320 01f0 e4f9 e36b 2046 .F.I... .....k F |
-000004f0: 023b e363 fff7 8eff 606b fff7 bfff 0248 .;.c....`k.....H |
-00000500: 01f0 aef9 12dc 0002 34dc 0002 08b5 0446 ........4......F |
-00000510: 0649 0320 01f0 cef9 2046 fff7 7bff 606b .I. .... F..{.`k |
-00000520: fff7 acff 0248 01f0 9bf9 00bf f3db 0002 .....H.......... |
-00000530: 34dc 0002 0446 1149 08b5 0320 01f0 baf9 4....F.I... .... |
-00000540: e36b 2046 043b e363 fff7 64ff 16ee 502f .k F.;.c..d...P/ |
-00000550: 0b49 0320 01f0 aef9 15ee 302f 0949 0320 .I. ......0/.I. |
-00000560: 01f0 a8f9 15ee 312f 0749 0320 01f0 a2f9 ......1/.I. .... |
-00000570: 606b fff7 83ff 0548 01f0 72f9 bbdb 0002 `k.....H..r..... |
-00000580: d6db 0002 e5db 0002 e4db 0002 34dc 0002 ............4... |
-00000590: 0446 1149 08b5 0320 01f0 8cf9 e36b 2046 .F.I... .....k F |
-000005a0: 083b e363 fff7 36ff 16ee 102f 0b49 0320 .;.c..6..../.I. |
-000005b0: 01f0 80f9 15ee 102f 0949 0320 01f0 7af9 ......./.I. ..z. |
-000005c0: 15ee 112f 0749 0320 01f0 74f9 606b fff7 .../.I. ..t.`k.. |
-000005d0: 55ff 0548 01f0 44f9 33db 0002 4adb 0002 U..H..D.3...J... |
-000005e0: 59db 0002 58db 0002 34dc 0002 08b5 0446 Y...X...4......F |
-000005f0: 0649 0320 01f0 5ef9 2046 fff7 0bff 606b .I. ..^. F....`k |
-00000600: fff7 3cff 0248 01f0 2bf9 00bf a6db 0002 ..<..H..+....... |
-00000610: 34dc 0002 0446 0849 08b5 0320 01f0 4af9 4....F.I... ..J. |
-00000620: e36b 2046 043b e363 fff7 f4fe 606b fff7 .k F.;.c....`k.. |
-00000630: 25ff 0248 01f0 14f9 96db 0002 34dc 0002 %..H........4... |
-00000640: 0446 0849 08b5 0320 01f0 34f9 e36b 2046 .F.I... ..4..k F |
-00000650: 043b e363 fff7 defe 606b fff7 0fff 0248 .;.c....`k.....H |
-00000660: 01f0 fef8 67db 0002 34dc 0002 08b5 11ee ....g...4....... |
-00000670: 103f 23f0 8043 23f4 0053 01ee 103f bff3 .?#..C#..S...?.. |
-00000680: 6f8f 0648 fff7 76fd 054b 064a 0720 0649 o..H..v..K.J. .I |
-00000690: 1a60 bde8 0840 01f0 0db9 00bf c0a4 0002 .`...@.......... |
-000006a0: 6ca5 0002 28e8 0002 77db 0002 f0b5 0125 l...(...w......% |
-000006b0: 059c 0f46 a540 01fa 04f4 2344 0c46 9e46 ...F.@....#D.F.F |
-000006c0: a242 0cd8 00eb 8100 8a42 10d8 bff3 4f8f .B.......B....O. |
-000006d0: ba42 11d8 bff3 4f8f bff3 6f8f f0bd 069e .B....O...o..... |
-000006e0: 46ea 0e06 ae44 40f8 2460 0134 e8e7 07ee F....D@.$`.4.... |
-000006f0: 3a0f 0131 0430 e7e7 08ee 773f 0137 2b44 :..1.0....w?.7+D |
-00000700: e6e7 0000 2de9 f341 0139 0144 334b 344e ....-..A.9.D3K4N |
-00000710: 4140 870a 1942 06eb 8708 56f8 2740 02d1 A@...B....V.'@.. |
-00000720: b0f5 800f 05d3 c723 2e4a 2f49 0020 01f0 .......#.J/I. .. |
-00000730: c1f8 56f8 2750 c5f3 0903 012b 0fd1 24f4 ..V.'P.....+..$. |
-00000740: 7f74 24f0 0304 2046 02b0 bde8 f081 04f5 .t$... F........ |
-00000750: 8064 0a1b 032a 05dc 2448 01f0 81f8 244c .d...*..$H....$L |
-00000760: 244b 2549 2268 9a42 f1d1 2d0d 2246 2349 $K%I"h.B..-."F#I |
-00000770: 0720 2d05 05f5 8013 0093 2b46 01f0 9af8 . -.......+F.... |
-00000780: 56f8 2720 0021 2046 d306 52bf c2f3 1303 V.' .! F..R..... |
-00000790: 1b4b 1340 40f6 0242 48bf 43f0 0103 1342 .K.@@..BH.C....B |
-000007a0: 4ff4 8072 1ebf 23f4 4363 23f0 0203 43f0 O..r..#.Cc#...C. |
-000007b0: 3203 0193 0c23 0093 2b46 fff7 77ff 44f0 2....#..+F..w.D. |
-000007c0: 0103 46f8 2730 07ee 3a8f bff3 4f8f 08ee ..F.'0..:...O... |
-000007d0: 775f bff3 4f8f bff3 6f8f b4e7 00fc 3f00 w_..O...o.....?. |
-000007e0: 0040 0002 badc 0002 d3dc 0002 f8dc 0002 .@.............. |
-000007f0: 0080 0002 e0a6 dbba 0084 0002 23dd 0002 ............#... |
-00000800: eeff 0f00 2de9 f341 1746 0646 0c46 fff7 ....-..A.F.F.F.. |
-00000810: 79ff 1b4b 3444 1b49 53f8 3750 ea06 03eb y..K4D.IS.7P.... |
-00000820: c702 26f4 7f77 48bf 25f0 1105 5368 27f0 ..&..wH.%...Sh'. |
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-00000840: 0334 24f0 0304 e41b 8046 0720 01f0 32f8 .4$......F. ..2. |
-00000850: b4f5 806f 05d9 e023 0b4a 0c49 0020 01f0 ...o...#.J.I. .. |
-00000860: 29f8 45f0 3205 0c23 0195 a208 0093 c6f3 ).E.2..#........ |
-00000870: 8701 bb02 4046 fff7 19ff 02b0 bde8 f081 ....@F.......... |
-00000880: 5cdc 0002 74dc 0002 badc 0002 d3dc 0002 \...t........... |
-00000890: f7b5 4618 134c 0546 1746 1349 04eb c203 ..F..L.F.F.I.... |
-000008a0: 0205 0720 5b68 0093 3305 01f0 03f8 b6f5 ... [h..3....... |
-000008b0: 805f 06d9 4ff4 8173 0c4a 0d49 0020 00f0 ._..O..s.J.I. .. |
-000008c0: f9ff 54f8 3730 3246 2946 0a48 43f4 4063 ..T.702F)F.HC.@c |
-000008d0: 43f0 0203 0193 1423 0093 0023 fff7 e6fe C......#...#.... |
-000008e0: 03b0 f0bd 5cdc 0002 74dc 0002 badc 0002 ....\...t....... |
-000008f0: d3dc 0002 0040 0002 0c4b 0d49 0d48 10b5 .....@...K.I.H.. |
-00000900: ca1a 032a 0edc 0c4c 0720 0c49 2246 00f0 ...*...L. .I"F.. |
-00000910: d1ff 02ee 104f 0023 02ee 503f 0523 03ee .....O.#..P?.#.. |
-00000920: 103f 10bd 1860 03f5 8063 e9e7 0080 0002 .?...`...c...... |
-00000930: 0084 0002 e0a6 dbba 0040 0002 9fdc 0002 .........@...... |
-00000940: 10b5 0446 fff7 49fc a369 e069 bde8 1040 ...F..I..i.i...@ |
-00000950: 1847 0000 0149 0020 00f0 acbf 71dd 0002 .G...I. ....q... |
-00000960: 4a1e 08bf f746 c0f0 b080 8842 30d9 1142 J....F.....B0..B |
-00000970: 32d0 b1fa 81f3 b0fa 80f2 a3eb 0202 4ff0 2.............O. |
-00000980: 0103 01fa 02f1 03fa 02f3 4ff0 0002 8842 ..........O....B |
-00000990: 24bf 401a 1a43 b0eb 510f 24bf a0eb 5100 $.@..C..Q.$...Q. |
-000009a0: 42ea 5302 b0eb 910f 24bf a0eb 9100 42ea B.S.....$.....B. |
-000009b0: 9302 b0eb d10f 24bf a0eb d100 42ea d302 ......$.....B... |
-000009c0: 0028 1ebf 5fea 1313 0909 e0e7 1046 f746 .(.._........F.F |
-000009d0: 0cbf 0120 0020 f746 b1fa 81f2 c2f1 1f02 ... . .F........ |
-000009e0: 20fa 02f0 f746 00bf 0029 80ea 010c 00f0 ....F...)...... |
-000009f0: 6c80 48bf 4942 4a1e 38d0 0300 48bf 4342 l.H.IBJ.8...H.CB |
-00000a00: 8b42 38d9 1142 3ed0 b1fa 81f2 b3fa 83f0 .B8..B>......... |
-00000a10: a2eb 0000 4ff0 0102 01fa 00f1 02fa 00f2 ....O........... |
-00000a20: 4ff0 0000 8b42 24bf 5b1a 1043 b3eb 510f O....B$.[..C..Q. |
-00000a30: 24bf a3eb 5103 40ea 5200 b3eb 910f 24bf $...Q.@.R.....$. |
-00000a40: a3eb 9103 40ea 9200 b3eb d10f 24bf a3eb ....@.......$... |
-00000a50: d103 40ea d200 002b 1ebf 5fea 1212 0909 ..@....+.._..... |
-00000a60: e0e7 bcf1 000f 48bf 4042 f746 9cea 000f ......H.@B.F.... |
-00000a70: 48bf 4042 f746 38bf 0020 04bf 4fea ec70 H.@B.F8.. ..O..p |
-00000a80: 40f0 0100 f746 b1fa 81f2 c2f1 1f02 bcf1 @....F.......... |
-00000a90: 000f 23fa 02f0 48bf 4042 f746 2de9 0350 ..#...H.@B.F-..P |
-00000aa0: fff7 5eff bde8 0650 00fb 02f3 a1eb 0301 ..^....P........ |
-00000ab0: f746 00bf 2de9 0350 fff7 96ff bde8 0650 .F..-..P.......P |
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-00003660: 059b 0434 2468 3bbb 27ea 0000 26ea 0101 ...4$h;.'...&... |
-00003670: 25ea 0202 24ea 0e03 80b2 bff3 5f8f 114c %...$......._..L |
-00003680: 2060 bff3 5f8f 01f0 0f01 bff3 5f8f 0e48 `.._......._..H |
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-000036a0: 0a60 bff3 5f8f 03f0 7f03 bff3 5f8f 084a .`.._......._..J |
-000036b0: 1360 bff3 5f8f f0bd 3843 3143 2a43 4eea .`.._...8C1C*CN. |
-000036c0: 0403 d9e7 4000 001a 4400 001a 4800 001a ....@...D...H... |
-000036d0: 4c00 001a 0000 0000 0400 0000 0100 0000 L............... |
-000036e0: 0200 0000 0100 0000 0400 0000 0400 0000 ................ |
-000036f0: 0400 0000 0400 0000 0000 0000 0000 0000 ................ |
-00003700: 0000 0000 ffff ffff 0000 0000 0100 0000 ................ |
-00003710: 0200 0000 0300 0000 4475 6d70 696e 6720 ........Dumping |
-00003720: 7374 6163 6b3a 0a00 2570 3a20 0025 3038 stack:..%p: .%08 |
-00003730: 7820 0065 7863 6570 7469 6f6e 205f 6461 x .exception _da |
-00003740: 7461 5f61 626f 7274 0a00 4446 4152 203d ta_abort..DFAR = |
-00003750: 2025 232e 3878 0a00 4144 4653 5220 3d20 %#.8x..ADFSR = |
-00003760: 2523 2e38 780a 0065 7863 6570 7469 6f6e %#.8x..exception |
-00003770: 205f 6669 710a 0045 7863 6570 7469 6f6e _fiq..Exception |
-00003780: 2068 616e 646c 6572 7320 696e 7374 616c handlers instal |
-00003790: 6c65 642e 0a00 6578 6365 7074 696f 6e20 led...exception |
-000037a0: 5f69 7271 0a00 6578 6365 7074 696f 6e20 _irq..exception |
-000037b0: 5f6e 6f74 5f75 7365 640a 0065 7863 6570 _not_used..excep |
-000037c0: 7469 6f6e 205f 7072 6566 6574 6368 5f61 tion _prefetch_a |
-000037d0: 626f 7274 0a00 4946 4152 203d 2025 232e bort..IFAR = %#. |
-000037e0: 3878 0a00 4149 4653 5220 3d20 2523 2e38 8x..AIFSR = %#.8 |
-000037f0: 780a 0065 7863 6570 7469 6f6e 205f 736f x..exception _so |
-00003800: 6674 7761 7265 5f69 6e74 6572 7275 7074 ftware_interrupt |
-00003810: 0a00 6578 6365 7074 696f 6e20 5f75 6e64 ..exception _und |
-00003820: 6566 696e 6564 5f69 6e73 7472 7563 7469 efined_instructi |
-00003830: 6f6e 0a00 6578 6365 7074 696f 6e00 5043 on..exception.PC |
-00003840: 004c 5200 5350 0049 5000 5225 6400 203d .LR.SP.IP.R%d. = |
-00003850: 2030 7825 3038 780a 0000 0000 1000 0000 0x%08x......... |
-00003860: 51dd 0002 0c00 0000 5add 0002 0800 0000 Q.......Z....... |
-00003870: 64dd 0002 4d61 7070 696e 6720 6164 6472 d...Mapping addr |
-00003880: 6573 7320 7261 6e67 6520 5b25 232e 3878 ess range [%#.8x |
-00003890: 3a25 232e 3878 2920 6173 2025 730a 0054 :%#.8x) as %s..T |
-000038a0: 7261 6e73 6c61 7469 6f6e 2074 6162 6c65 ranslation table |
-000038b0: 2069 7320 4020 2570 0a00 7372 632f 6172 is @ %p..src/ar |
-000038c0: 6368 2f61 726d 2f61 726d 7637 2f6d 6d75 ch/arm/armv7/mmu |
-000038d0: 2e63 0041 5353 4552 5449 4f4e 2045 5252 .c.ASSERTION ERR |
-000038e0: 4f52 3a20 6669 6c65 2027 2573 272c 206c OR: file '%s', l |
-000038f0: 696e 6520 2564 0a00 4e6f 7420 656e 6f75 ine %d..Not enou |
-00003900: 6768 2072 6f6f 6d20 666f 7220 616e 6f74 gh room for anot |
-00003910: 6865 7220 7375 622d 7061 6765 7461 626c her sub-pagetabl |
-00003920: 6521 0043 7265 6174 696e 6720 6e65 7720 e!.Creating new |
-00003930: 7375 6274 6162 6c65 2040 2570 2066 6f72 subtable @%p for |
-00003940: 205b 2523 2e38 783a 2523 2e38 6c78 290a [%#.8x:%#.8lx). |
-00003950: 0075 6e63 6163 6865 6400 7772 6974 6562 .uncached.writeb |
-00003960: 6163 6b00 7772 6974 6574 6872 6f75 6768 ack.writethrough |
-00003970: 0044 4956 4944 4520 4259 205a 4552 4f21 .DIVIDE BY ZERO! |
-00003980: 2063 6f6e 7469 6e75 696e 6720 2e2e 2e0a continuing .... |
-00003990: 004c 4152 4348 4956 4500 4342 4653 3a20 .LARCHIVE.CBFS: |
-000039a0: 4c6f 6361 7469 6e67 2027 2573 270a 0043 Locating '%s'..C |
-000039b0: 4246 533a 2046 6f75 6e64 2040 206f 6666 BFS: Found @ off |
-000039c0: 7365 7420 257a 7820 7369 7a65 2025 7a78 set %zx size %zx |
-000039d0: 0a00 4342 4653 3a20 2725 7327 206e 6f74 ..CBFS: '%s' not |
-000039e0: 2066 6f75 6e64 2e0a 0000 0000 9bba 0002 found.......... |
-000039f0: a3ba 0002 a7ba 0002 0000 0000 0000 0000 ................ |
-00003a00: 2573 000a 0a63 6f72 6562 6f6f 742d 2573 %s...coreboot-%s |
-00003a10: 2573 2025 7320 626f 6f74 626c 6f63 6b20 %s %s bootblock |
-00003a20: 7374 6172 7469 6e67 2e2e 2e0a 0030 3132 starting.....012 |
-00003a30: 3334 3536 3738 3961 6263 6465 6667 6869 3456789abcdefghi |
-00003a40: 6a6b 6c6d 6e6f 7071 7273 7475 7677 7879 jklmnopqrstuvwxy |
-00003a50: 7a00 3031 3233 3435 3637 3839 4142 4344 z.0123456789ABCD |
-00003a60: 4546 4748 494a 4b4c 4d4e 4f50 5152 5354 EFGHIJKLMNOPQRST |
-00003a70: 5556 5758 595a 003c 4e55 4c4c 3e00 0000 UVWXYZ.<NULL>... |
-00003a80: dfbb 0002 1dbc 0002 21c2 0002 fdc1 0002 ........!....... |
-00003a90: e1c1 0002 0000 1302 0000 0000 9dc2 0002 ................ |
-00003aa0: 0001 0001 1000 0000 0ae0 0002 0000 1402 ................ |
-00003ab0: 0000 0000 9dc2 0002 0001 0001 2000 0000 ............ ... |
-00003ac0: 14e0 0002 0000 1502 0000 0000 9dc2 0002 ................ |
-00003ad0: 0001 0001 4000 0000 1ee0 0002 0000 1602 ....@........... |
-00003ae0: 0000 0000 9dc2 0002 0001 0001 8000 0000 ................ |
-00003af0: 28e0 0002 0000 1820 0103 0000 9dc2 0002 (...... ........ |
-00003b00: 0001 0001 0001 0000 32e0 0002 0000 1820 ........2...... |
-00003b10: 0003 0000 9dc2 0002 0001 0004 4000 0000 ............@... |
-00003b20: 40e0 0002 0000 1902 014d 0000 9dc2 0002 @........M...... |
-00003b30: 0001 0001 0002 0000 4fe0 0002 0000 1502 ........O....... |
-00003b40: 004d 0000 9dc2 0002 0001 0001 4000 0000 .M..........@... |
-00003b50: 5ee0 0002 0000 1820 014d 0000 9dc2 0002 ^...... .M...... |
-00003b60: 0001 0001 0001 0000 68e0 0002 0100 1540 ........h......@ |
-00003b70: 0000 0000 c3c2 0002 0001 0001 2000 0000 ............ ... |
-00003b80: 71e0 0002 5346 3a20 456e 6162 6c69 6e67 q...SF: Enabling |
-00003b90: 2057 7269 7465 2066 6169 6c65 640a 0053 Write failed..S |
-00003ba0: 463a 2053 5041 4e53 494f 4e20 5061 6765 F: SPANSION Page |
-00003bb0: 2050 726f 6772 616d 2066 6169 6c65 640a Program failed. |
-00003bc0: 0000 0000 f5c6 0002 e1c2 0002 b9c7 0002 ................ |
-00003bd0: 5dc8 0002 5346 3a20 556e 7375 7070 6f72 ]...SF: Unsuppor |
-00003be0: 7465 6420 5350 414e 5349 4f4e 2049 4420 ted SPANSION ID |
-00003bf0: 2530 3278 2025 3032 7820 2530 3278 2025 %02x %02x %02x % |
-00003c00: 3032 7820 2530 3278 0a00 5332 3546 4c30 02x %02x..S25FL0 |
-00003c10: 3038 4100 5332 3546 4c30 3136 4100 5332 08A.S25FL016A.S2 |
-00003c20: 3546 4c30 3332 4100 5332 3546 4c30 3634 5FL032A.S25FL064 |
-00003c30: 4100 5332 3546 4c31 3238 505f 3634 4b00 A.S25FL128P_64K. |
-00003c40: 5332 3546 4c31 3238 505f 3235 364b 0053 S25FL128P_256K.S |
-00003c50: 3235 464c 3132 3853 5f32 3536 4b00 5332 25FL128S_256K.S2 |
-00003c60: 3546 4c30 3332 5000 3235 4653 3132 3853 5FL032P.25FS128S |
-00003c70: 0053 3235 464c 3131 364b 5f31 364d 0073 .S25FL116K_16M.s |
-00003c80: 7263 2f64 7269 7665 7273 2f73 7069 2f73 rc/drivers/spi/s |
-00003c90: 7069 2d67 656e 6572 6963 2e63 0000 0000 pi-generic.c.... |
-00003ca0: 0001 0000 91c3 0002 0020 0000 f9c9 0002 ......... ...... |
-00003cb0: 00ff 0000 f9c9 0002 5346 3a20 4661 696c ........SF: Fail |
-00003cc0: 6564 2074 6f20 7365 6e64 2063 6f6d 6d61 ed to send comma |
-00003cd0: 6e64 2025 3032 783a 2025 640a 0053 463a nd %02x: %d..SF: |
-00003ce0: 2045 7261 7365 206f 6666 7365 742f 6c65 Erase offset/le |
-00003cf0: 6e67 7468 206e 6f74 206d 756c 7469 706c ngth not multipl |
-00003d00: 6520 6f66 2065 7261 7365 2073 697a 650a e of erase size. |
-00003d10: 0053 463a 2053 7563 6365 7373 6675 6c6c .SF: Successfull |
-00003d20: 7920 6572 6173 6564 2025 7a75 2062 7974 y erased %zu byt |
-00003d30: 6573 2040 2025 2378 0a00 5346 3a20 7469 es @ %#x..SF: ti |
-00003d40: 6d65 6f75 7420 6174 2025 6c64 206d 7365 meout at %ld mse |
-00003d50: 630a 0053 463a 2046 6169 6c65 6420 746f c..SF: Failed to |
-00003d60: 2073 656e 6420 7265 6164 2063 6f6d 6d61 send read comma |
-00003d70: 6e64 2028 257a 7520 6279 7465 7329 3a20 nd (%zu bytes): |
-00003d80: 2564 0a00 5346 3a20 4661 696c 6564 2074 %d..SF: Failed t |
-00003d90: 6f20 7365 6e64 2077 7269 7465 2063 6f6d o send write com |
-00003da0: 6d61 6e64 2028 257a 7520 6279 7465 7329 mand (%zu bytes) |
-00003db0: 3a20 2564 0a00 4d61 6e75 6661 6374 7572 : %d..Manufactur |
-00003dc0: 6572 3a20 2530 3278 0a00 5346 3a20 4661 er: %02x..SF: Fa |
-00003dd0: 696c 6564 2074 6f20 7365 7420 7570 2073 iled to set up s |
-00003de0: 6c61 7665 0a00 5346 3a20 556e 7375 7070 lave..SF: Unsupp |
-00003df0: 6f72 7465 6420 6d61 6e75 6661 6374 7572 orted manufactur |
-00003e00: 6572 210a 0053 463a 2044 6574 6563 7465 er!..SF: Detecte |
-00003e10: 6420 2573 2077 6974 6820 7365 6374 6f72 d %s with sector |
-00003e20: 2073 697a 6520 3078 2578 2c20 746f 7461 size 0x%x, tota |
-00003e30: 6c20 3078 2578 0a00 adc6 0002 49c9 0002 l 0x%x......I... |
-00003e40: b9c7 0002 0000 0000 5346 3a20 556e 7375 ........SF: Unsu |
-00003e50: 7070 6f72 7465 6420 5354 4d69 6372 6f20 pported STMicro |
-00003e60: 4944 2025 3032 7825 3032 780a 0000 0000 ID %02x%02x..... |
-00003e70: 1120 d800 0001 8000 0400 0000 51e3 0002 . ..........Q... |
-00003e80: 1520 d800 0001 0001 2000 0000 58e3 0002 . ...... ...X... |
-00003e90: 1220 d800 0001 0001 0400 0000 5fe3 0002 . .........._... |
-00003ea0: 1620 d800 0001 0001 4000 0000 66e3 0002 . ......@...f... |
-00003eb0: 1320 d800 0001 0001 0800 0000 6de3 0002 . ..........m... |
-00003ec0: 1720 d800 0001 0001 8000 0000 74e3 0002 . ..........t... |
-00003ed0: 1420 d800 0001 0001 1000 0000 7be3 0002 . ..........{... |
-00003ee0: 1820 d800 0001 0004 4000 0000 82e3 0002 . ......@....... |
-00003ef0: 17bb 2000 0001 1000 0008 0000 8ae3 0002 .. ............. |
-00003f00: 18bb 2000 0001 1000 0010 0000 92e3 0002 .. ............. |
-00003f10: 18ba 2000 0001 1000 0010 0000 9ae3 0002 .. ............. |
-00003f20: 19ba 2000 0001 1000 0020 0000 a3e3 0002 .. ...... ...... |
-00003f30: 5346 3a20 5354 4d69 6372 6f20 5061 6765 SF: STMicro Page |
-00003f40: 2050 726f 6772 616d 2066 6169 6c65 640a Program failed. |
-00003f50: 004d 3235 5031 3000 4d32 3550 3136 004d .M25P10.M25P16.M |
-00003f60: 3235 5032 3000 4d32 3550 3332 004d 3235 25P20.M25P32.M25 |
-00003f70: 5034 3000 4d32 3550 3634 004d 3235 5038 P40.M25P64.M25P8 |
-00003f80: 3000 4d32 3550 3132 3800 4e32 3551 3036 0.M25P128.N25Q06 |
-00003f90: 3400 4e32 3551 3132 3800 4e32 3551 3132 4.N25Q128.N25Q12 |
-00003fa0: 3841 004e 3235 5132 3536 0043 4246 533a 8A.N25Q256.CBFS: |
-00003fb0: 2027 2573 2720 6c6f 6361 7465 6420 4342 '%s' located CB |
-00003fc0: 4653 2061 7420 5b25 7a78 3a25 7a78 290a FS at [%zx:%zx). |
-00003fd0: 0000 0000 04e4 0002 0000 0000 c1ca 0002 ................ |
-00003fe0: 4342 4653 2040 2025 7a78 2073 697a 6520 CBFS @ %zx size |
-00003ff0: 257a 780a 0073 7263 2f6c 6962 2f63 6266 %zx..src/lib/cbf |
-00004000: 732e 6300 4d61 7374 6572 2048 6561 6465 s.c.Master Heade |
-00004010: 7220 4c6f 6361 746f 7200 0000 0000 0000 r Locator....... |
-00004020: 0000 0000 ecdd 0002 0000 0000 ffff ffff ................ |
-00004030: 6661 6c6c 6261 636b 2f72 6f6d 7374 6167 fallback/romstag |
-00004040: 6500 436f 756c 646e 2774 206c 6f61 6420 e.Couldn't load |
-00004050: 726f 6d73 7461 6765 2e0a 0057 6564 204a romstage...Wed J |
-00004060: 616e 2020 3320 3036 3a32 393a 3532 2055 an 3 06:29:52 U |
-00004070: 5443 2032 3031 3800 0034 2e36 2d32 3438 TC 2018..4.6-248 |
-00004080: 302d 6764 3037 3835 3039 3866 3239 312d 0-gd0785098f291- |
-00004090: 6469 7274 7900 0000 0000 0019 0800 0019 dirty........... |
-000040a0: 0c00 0019 1000 0019 1400 0019 1800 0019 ................ |
-000040b0: 1c00 0019 2000 0019 2400 0019 3400 0019 .... ...$...4... |
-000040c0: 3800 0019 3c00 0019 4000 0019 4400 0019 8...<...@...D... |
-000040d0: 0001 0019 0002 0019 0402 0019 1002 0019 ................ |
-000040e0: 0003 0019 0004 0019 000a 0019 040a 0019 ................ |
-000040f0: 080a 0019 0c0a 0019 100a 0019 140a 0019 ................ |
-00004100: 000c 0019 040c 0019 080c 0019 0c0c 0019 ................ |
-00004110: 100c 0019 140c 0019 180c 0019 1c0c 0019 ................ |
-00004120: 200c 0019 240c 0019 000e 0019 040e 0019 ...$........... |
-00004130: 080e 0019 100e 0019 200e 0019 240e 0019 ........ ...$... |
-00004140: 400e 0019 480e 0019 640e 0019 c00e 0019 @...H...d....... |
-00004150: c40e 0019 000f 0019 040f 0019 080f 0019 ................ |
-00004160: 7472 7573 747a 6f6e 6520 696e 6974 6961 trustzone initia |
-00004170: 6c69 7a65 640a 0046 6169 6c65 6420 746f lized..Failed to |
-00004180: 2062 7269 6e67 2050 4c33 3330 2044 4d41 bring PL330 DMA |
-00004190: 4320 6f75 7420 6f66 2072 6573 6574 0a00 C out of reset.. |
-000041a0: 504c 3333 3020 444d 4143 2069 6e69 7469 PL330 DMAC initi |
-000041b0: 616c 697a 6564 0a00 4c43 4420 696e 6974 alized..LCD init |
-000041c0: 6961 6c69 7a65 640a 0056 3344 2069 6e69 ialized..V3D ini |
-000041d0: 7469 616c 697a 6564 0a00 6175 6469 6f20 tialized..audio |
-000041e0: 696e 6974 6961 6c69 7a65 640a 0046 6169 initialized..Fai |
-000041f0: 6c65 6420 746f 2061 636b 204e 454f 4e20 led to ack NEON |
-00004200: 706f 7765 7220 6f6e 0a00 4661 696c 6564 power on..Failed |
-00004210: 2074 6f20 6163 6b20 4e45 4f4e 2070 6f77 to ack NEON pow |
-00004220: 6572 206f 6b0a 006e 656f 6e20 696e 6974 er ok..neon init |
-00004230: 6961 6c69 7a65 640a 0050 4349 6520 696e ialized..PCIe in |
-00004240: 6974 6961 6c69 7a65 640a 004d 3020 696e itialized..M0 in |
-00004250: 6974 6961 6c69 7a65 640a 0043 4355 2069 itialized..CCU i |
-00004260: 6e69 7469 616c 697a 6564 0a00 5344 494f nitialized..SDIO |
-00004270: 2069 6e69 7469 616c 697a 6564 0a00 4661 initialized..Fa |
-00004280: 696c 6564 2074 6f20 6272 696e 6720 5344 iled to bring SD |
-00004290: 494f 206f 7574 206f 6620 7265 7365 740a IO out of reset. |
-000042a0: 0000 0000 51d7 0002 e5d4 0002 35d4 0002 ....Q.......5... |
-000042b0: 01d5 0002 39c5 0002 ffff 0000 0000 0000 ....9........... |
-000042c0: 0000 0000 0000 0000 a4e6 0002 0000 0000 ................ |
-000042d0: 0000 0000 0100 0000 0800 001a 1000 001a ................ |
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-000042f0: 7800 001a 7c00 001a 8000 001a 8400 001a x...|........... |
-00004300: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004310: 0000 0000 80de 0002 0000 0000 0000 2000 .............. . |
-00004320: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004330: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004340: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004350: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004360: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004370: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004380: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004390: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043a0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043b0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043c0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043d0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043f0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004400: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004410: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004420: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004430: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004440: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004450: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004460: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004470: 9c65 2962 ce5a 1cde 3ad7 51fa 5792 319c .e)b.Z..:.Q.W.1. |
-00004480: 94fa e470 9db7 3834 a825 01f0 7cc8 1259 ...p..84.%..|..Y |
diff --git a/util/broadcom/secimage/test/data/input/binary.xxdump b/util/broadcom/secimage/test/data/input/binary.xxdump
deleted file mode 100644
index 8ea9217..0000000
--- a/util/broadcom/secimage/test/data/input/binary.xxdump
+++ /dev/null
@@ -1,1091 +0,0 @@
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-00003450: bff3 5f8f c0f3 0740 30b1 71b1 bff3 5f8f .._....@0.q..._. |
-00003460: 0a4b 1860 bff3 5f8f 7047 bff3 5f8f 084a .K.`.._.pG.._..J |
-00003470: e3e7 bff3 5f8f 074a e9e7 bff3 5f8f 064b ...._..J...._..K |
-00003480: efe7 00bf 0448 0318 1048 0318 1c48 0318 .....H...H...H.. |
-00003490: 0848 0318 1448 0318 2048 0318 30b5 01f0 .H...H.. H..0... |
-000034a0: 0101 0a4d c0f3 0900 0023 0124 04fa 03f2 ...M.....#.$.... |
-000034b0: 0242 06d0 55f8 2320 bff3 5f8f 1160 bff3 .B..U.# .._..`.. |
-000034c0: 5f8f 0133 0a2b f1d1 30bd 00bf d8e6 0002 _..3.+..0....... |
-000034d0: 30b5 bff3 5f8f 114c 2568 bff3 5f8f 104b 0..._..L%h.._..K |
-000034e0: 1a68 104b 03ea 0243 4cf6 ff72 1540 2b43 .h.K...CL..r.@+C |
-000034f0: 91b9 23ea 0000 0240 bff3 5f8f 2260 bff3 ..#....@.._."`.. |
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-00003510: 1860 bff3 5f8f 30bd 1843 ece7 3400 001a .`.._.0..C..4... |
-00003520: 2c00 001a 0000 1f3f bff3 5f8f 074b 1a68 ,......?.._..K.h |
-00003530: 49b9 22ea 0000 00f0 3f00 bff3 5f8f 1860 I.".....?..._..` |
-00003540: bff3 5f8f 7047 1043 f5e7 00bf 3000 001a .._.pG.C....0... |
-00003550: 10b5 bff3 5f8f 0c4a 1368 bff3 5f8f 1468 ...._..J.h.._..h |
-00003560: 43ea 0443 71b9 23ea 0000 bff3 5f8f 1060 C..Cq.#....._..` |
-00003570: bff3 5f8f 000c bff3 5f8f 044b 1860 bff3 .._....._..K.`.. |
-00003580: 5f8f 10bd 1843 f0e7 8800 001a 8c00 001a _....C.......... |
-00003590: 30b5 bff3 5f8f 114c 2568 bff3 5f8f 104b 0..._..L%h.._..K |
-000035a0: 1a68 104b 03ea 0243 44f2 6d32 1540 2b43 .h.K...CD.m2.@+C |
-000035b0: 91b9 23ea 0000 0240 bff3 5f8f 2260 bff3 ..#....@.._."`.. |
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-000035e0: 7000 001a 0000 ee57 c0f3 0900 bff3 5f8f p......W......_. |
-000035f0: 024b 1860 bff3 5f8f 7047 00bf 0040 0318 .K.`.._.pG...@.. |
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-00003610: 0434 2668 bff3 5f8f 0434 2568 bff3 5f8f .4&h.._..4%h.._. |
-00003620: 059b 0434 2468 3bbb 27ea 0000 26ea 0101 ...4$h;.'...&... |
-00003630: 25ea 0202 24ea 0e03 80b2 bff3 5f8f 114c %...$......._..L |
-00003640: 2060 bff3 5f8f 01f0 0f01 bff3 5f8f 0e48 `.._......._..H |
-00003650: 0160 bff3 5f8f c2f3 0d02 bff3 5f8f 0b49 .`.._......._..I |
-00003660: 0a60 bff3 5f8f 03f0 7f03 bff3 5f8f 084a .`.._......._..J |
-00003670: 1360 bff3 5f8f f0bd 3843 3143 2a43 4eea .`.._...8C1C*CN. |
-00003680: 0403 d9e7 4000 001a 4400 001a 4800 001a ....@...D...H... |
-00003690: 4c00 001a 0000 0000 0400 0000 0100 0000 L............... |
-000036a0: 0200 0000 0100 0000 0400 0000 0400 0000 ................ |
-000036b0: 0400 0000 0400 0000 0000 0000 0000 0000 ................ |
-000036c0: 0000 0000 ffff ffff 0000 0000 0100 0000 ................ |
-000036d0: 0200 0000 0300 0000 4475 6d70 696e 6720 ........Dumping |
-000036e0: 7374 6163 6b3a 0a00 2570 3a20 0025 3038 stack:..%p: .%08 |
-000036f0: 7820 0065 7863 6570 7469 6f6e 205f 6461 x .exception _da |
-00003700: 7461 5f61 626f 7274 0a00 4446 4152 203d ta_abort..DFAR = |
-00003710: 2025 232e 3878 0a00 4144 4653 5220 3d20 %#.8x..ADFSR = |
-00003720: 2523 2e38 780a 0065 7863 6570 7469 6f6e %#.8x..exception |
-00003730: 205f 6669 710a 0045 7863 6570 7469 6f6e _fiq..Exception |
-00003740: 2068 616e 646c 6572 7320 696e 7374 616c handlers instal |
-00003750: 6c65 642e 0a00 6578 6365 7074 696f 6e20 led...exception |
-00003760: 5f69 7271 0a00 6578 6365 7074 696f 6e20 _irq..exception |
-00003770: 5f6e 6f74 5f75 7365 640a 0065 7863 6570 _not_used..excep |
-00003780: 7469 6f6e 205f 7072 6566 6574 6368 5f61 tion _prefetch_a |
-00003790: 626f 7274 0a00 4946 4152 203d 2025 232e bort..IFAR = %#. |
-000037a0: 3878 0a00 4149 4653 5220 3d20 2523 2e38 8x..AIFSR = %#.8 |
-000037b0: 780a 0065 7863 6570 7469 6f6e 205f 736f x..exception _so |
-000037c0: 6674 7761 7265 5f69 6e74 6572 7275 7074 ftware_interrupt |
-000037d0: 0a00 6578 6365 7074 696f 6e20 5f75 6e64 ..exception _und |
-000037e0: 6566 696e 6564 5f69 6e73 7472 7563 7469 efined_instructi |
-000037f0: 6f6e 0a00 6578 6365 7074 696f 6e00 5043 on..exception.PC |
-00003800: 004c 5200 5350 0049 5000 5225 6400 203d .LR.SP.IP.R%d. = |
-00003810: 2030 7825 3038 780a 0000 0000 1000 0000 0x%08x......... |
-00003820: 51dd 0002 0c00 0000 5add 0002 0800 0000 Q.......Z....... |
-00003830: 64dd 0002 4d61 7070 696e 6720 6164 6472 d...Mapping addr |
-00003840: 6573 7320 7261 6e67 6520 5b25 232e 3878 ess range [%#.8x |
-00003850: 3a25 232e 3878 2920 6173 2025 730a 0054 :%#.8x) as %s..T |
-00003860: 7261 6e73 6c61 7469 6f6e 2074 6162 6c65 ranslation table |
-00003870: 2069 7320 4020 2570 0a00 7372 632f 6172 is @ %p..src/ar |
-00003880: 6368 2f61 726d 2f61 726d 7637 2f6d 6d75 ch/arm/armv7/mmu |
-00003890: 2e63 0041 5353 4552 5449 4f4e 2045 5252 .c.ASSERTION ERR |
-000038a0: 4f52 3a20 6669 6c65 2027 2573 272c 206c OR: file '%s', l |
-000038b0: 696e 6520 2564 0a00 4e6f 7420 656e 6f75 ine %d..Not enou |
-000038c0: 6768 2072 6f6f 6d20 666f 7220 616e 6f74 gh room for anot |
-000038d0: 6865 7220 7375 622d 7061 6765 7461 626c her sub-pagetabl |
-000038e0: 6521 0043 7265 6174 696e 6720 6e65 7720 e!.Creating new |
-000038f0: 7375 6274 6162 6c65 2040 2570 2066 6f72 subtable @%p for |
-00003900: 205b 2523 2e38 783a 2523 2e38 6c78 290a [%#.8x:%#.8lx). |
-00003910: 0075 6e63 6163 6865 6400 7772 6974 6562 .uncached.writeb |
-00003920: 6163 6b00 7772 6974 6574 6872 6f75 6768 ack.writethrough |
-00003930: 0044 4956 4944 4520 4259 205a 4552 4f21 .DIVIDE BY ZERO! |
-00003940: 2063 6f6e 7469 6e75 696e 6720 2e2e 2e0a continuing .... |
-00003950: 004c 4152 4348 4956 4500 4342 4653 3a20 .LARCHIVE.CBFS: |
-00003960: 4c6f 6361 7469 6e67 2027 2573 270a 0043 Locating '%s'..C |
-00003970: 4246 533a 2046 6f75 6e64 2040 206f 6666 BFS: Found @ off |
-00003980: 7365 7420 257a 7820 7369 7a65 2025 7a78 set %zx size %zx |
-00003990: 0a00 4342 4653 3a20 2725 7327 206e 6f74 ..CBFS: '%s' not |
-000039a0: 2066 6f75 6e64 2e0a 0000 0000 9bba 0002 found.......... |
-000039b0: a3ba 0002 a7ba 0002 0000 0000 0000 0000 ................ |
-000039c0: 2573 000a 0a63 6f72 6562 6f6f 742d 2573 %s...coreboot-%s |
-000039d0: 2573 2025 7320 626f 6f74 626c 6f63 6b20 %s %s bootblock |
-000039e0: 7374 6172 7469 6e67 2e2e 2e0a 0030 3132 starting.....012 |
-000039f0: 3334 3536 3738 3961 6263 6465 6667 6869 3456789abcdefghi |
-00003a00: 6a6b 6c6d 6e6f 7071 7273 7475 7677 7879 jklmnopqrstuvwxy |
-00003a10: 7a00 3031 3233 3435 3637 3839 4142 4344 z.0123456789ABCD |
-00003a20: 4546 4748 494a 4b4c 4d4e 4f50 5152 5354 EFGHIJKLMNOPQRST |
-00003a30: 5556 5758 595a 003c 4e55 4c4c 3e00 0000 UVWXYZ.<NULL>... |
-00003a40: dfbb 0002 1dbc 0002 21c2 0002 fdc1 0002 ........!....... |
-00003a50: e1c1 0002 0000 1302 0000 0000 9dc2 0002 ................ |
-00003a60: 0001 0001 1000 0000 0ae0 0002 0000 1402 ................ |
-00003a70: 0000 0000 9dc2 0002 0001 0001 2000 0000 ............ ... |
-00003a80: 14e0 0002 0000 1502 0000 0000 9dc2 0002 ................ |
-00003a90: 0001 0001 4000 0000 1ee0 0002 0000 1602 ....@........... |
-00003aa0: 0000 0000 9dc2 0002 0001 0001 8000 0000 ................ |
-00003ab0: 28e0 0002 0000 1820 0103 0000 9dc2 0002 (...... ........ |
-00003ac0: 0001 0001 0001 0000 32e0 0002 0000 1820 ........2...... |
-00003ad0: 0003 0000 9dc2 0002 0001 0004 4000 0000 ............@... |
-00003ae0: 40e0 0002 0000 1902 014d 0000 9dc2 0002 @........M...... |
-00003af0: 0001 0001 0002 0000 4fe0 0002 0000 1502 ........O....... |
-00003b00: 004d 0000 9dc2 0002 0001 0001 4000 0000 .M..........@... |
-00003b10: 5ee0 0002 0000 1820 014d 0000 9dc2 0002 ^...... .M...... |
-00003b20: 0001 0001 0001 0000 68e0 0002 0100 1540 ........h......@ |
-00003b30: 0000 0000 c3c2 0002 0001 0001 2000 0000 ............ ... |
-00003b40: 71e0 0002 5346 3a20 456e 6162 6c69 6e67 q...SF: Enabling |
-00003b50: 2057 7269 7465 2066 6169 6c65 640a 0053 Write failed..S |
-00003b60: 463a 2053 5041 4e53 494f 4e20 5061 6765 F: SPANSION Page |
-00003b70: 2050 726f 6772 616d 2066 6169 6c65 640a Program failed. |
-00003b80: 0000 0000 f5c6 0002 e1c2 0002 b9c7 0002 ................ |
-00003b90: 5dc8 0002 5346 3a20 556e 7375 7070 6f72 ]...SF: Unsuppor |
-00003ba0: 7465 6420 5350 414e 5349 4f4e 2049 4420 ted SPANSION ID |
-00003bb0: 2530 3278 2025 3032 7820 2530 3278 2025 %02x %02x %02x % |
-00003bc0: 3032 7820 2530 3278 0a00 5332 3546 4c30 02x %02x..S25FL0 |
-00003bd0: 3038 4100 5332 3546 4c30 3136 4100 5332 08A.S25FL016A.S2 |
-00003be0: 3546 4c30 3332 4100 5332 3546 4c30 3634 5FL032A.S25FL064 |
-00003bf0: 4100 5332 3546 4c31 3238 505f 3634 4b00 A.S25FL128P_64K. |
-00003c00: 5332 3546 4c31 3238 505f 3235 364b 0053 S25FL128P_256K.S |
-00003c10: 3235 464c 3132 3853 5f32 3536 4b00 5332 25FL128S_256K.S2 |
-00003c20: 3546 4c30 3332 5000 3235 4653 3132 3853 5FL032P.25FS128S |
-00003c30: 0053 3235 464c 3131 364b 5f31 364d 0073 .S25FL116K_16M.s |
-00003c40: 7263 2f64 7269 7665 7273 2f73 7069 2f73 rc/drivers/spi/s |
-00003c50: 7069 2d67 656e 6572 6963 2e63 0000 0000 pi-generic.c.... |
-00003c60: 0001 0000 91c3 0002 0020 0000 f9c9 0002 ......... ...... |
-00003c70: 00ff 0000 f9c9 0002 5346 3a20 4661 696c ........SF: Fail |
-00003c80: 6564 2074 6f20 7365 6e64 2063 6f6d 6d61 ed to send comma |
-00003c90: 6e64 2025 3032 783a 2025 640a 0053 463a nd %02x: %d..SF: |
-00003ca0: 2045 7261 7365 206f 6666 7365 742f 6c65 Erase offset/le |
-00003cb0: 6e67 7468 206e 6f74 206d 756c 7469 706c ngth not multipl |
-00003cc0: 6520 6f66 2065 7261 7365 2073 697a 650a e of erase size. |
-00003cd0: 0053 463a 2053 7563 6365 7373 6675 6c6c .SF: Successfull |
-00003ce0: 7920 6572 6173 6564 2025 7a75 2062 7974 y erased %zu byt |
-00003cf0: 6573 2040 2025 2378 0a00 5346 3a20 7469 es @ %#x..SF: ti |
-00003d00: 6d65 6f75 7420 6174 2025 6c64 206d 7365 meout at %ld mse |
-00003d10: 630a 0053 463a 2046 6169 6c65 6420 746f c..SF: Failed to |
-00003d20: 2073 656e 6420 7265 6164 2063 6f6d 6d61 send read comma |
-00003d30: 6e64 2028 257a 7520 6279 7465 7329 3a20 nd (%zu bytes): |
-00003d40: 2564 0a00 5346 3a20 4661 696c 6564 2074 %d..SF: Failed t |
-00003d50: 6f20 7365 6e64 2077 7269 7465 2063 6f6d o send write com |
-00003d60: 6d61 6e64 2028 257a 7520 6279 7465 7329 mand (%zu bytes) |
-00003d70: 3a20 2564 0a00 4d61 6e75 6661 6374 7572 : %d..Manufactur |
-00003d80: 6572 3a20 2530 3278 0a00 5346 3a20 4661 er: %02x..SF: Fa |
-00003d90: 696c 6564 2074 6f20 7365 7420 7570 2073 iled to set up s |
-00003da0: 6c61 7665 0a00 5346 3a20 556e 7375 7070 lave..SF: Unsupp |
-00003db0: 6f72 7465 6420 6d61 6e75 6661 6374 7572 orted manufactur |
-00003dc0: 6572 210a 0053 463a 2044 6574 6563 7465 er!..SF: Detecte |
-00003dd0: 6420 2573 2077 6974 6820 7365 6374 6f72 d %s with sector |
-00003de0: 2073 697a 6520 3078 2578 2c20 746f 7461 size 0x%x, tota |
-00003df0: 6c20 3078 2578 0a00 adc6 0002 49c9 0002 l 0x%x......I... |
-00003e00: b9c7 0002 0000 0000 5346 3a20 556e 7375 ........SF: Unsu |
-00003e10: 7070 6f72 7465 6420 5354 4d69 6372 6f20 pported STMicro |
-00003e20: 4944 2025 3032 7825 3032 780a 0000 0000 ID %02x%02x..... |
-00003e30: 1120 d800 0001 8000 0400 0000 51e3 0002 . ..........Q... |
-00003e40: 1520 d800 0001 0001 2000 0000 58e3 0002 . ...... ...X... |
-00003e50: 1220 d800 0001 0001 0400 0000 5fe3 0002 . .........._... |
-00003e60: 1620 d800 0001 0001 4000 0000 66e3 0002 . ......@...f... |
-00003e70: 1320 d800 0001 0001 0800 0000 6de3 0002 . ..........m... |
-00003e80: 1720 d800 0001 0001 8000 0000 74e3 0002 . ..........t... |
-00003e90: 1420 d800 0001 0001 1000 0000 7be3 0002 . ..........{... |
-00003ea0: 1820 d800 0001 0004 4000 0000 82e3 0002 . ......@....... |
-00003eb0: 17bb 2000 0001 1000 0008 0000 8ae3 0002 .. ............. |
-00003ec0: 18bb 2000 0001 1000 0010 0000 92e3 0002 .. ............. |
-00003ed0: 18ba 2000 0001 1000 0010 0000 9ae3 0002 .. ............. |
-00003ee0: 19ba 2000 0001 1000 0020 0000 a3e3 0002 .. ...... ...... |
-00003ef0: 5346 3a20 5354 4d69 6372 6f20 5061 6765 SF: STMicro Page |
-00003f00: 2050 726f 6772 616d 2066 6169 6c65 640a Program failed. |
-00003f10: 004d 3235 5031 3000 4d32 3550 3136 004d .M25P10.M25P16.M |
-00003f20: 3235 5032 3000 4d32 3550 3332 004d 3235 25P20.M25P32.M25 |
-00003f30: 5034 3000 4d32 3550 3634 004d 3235 5038 P40.M25P64.M25P8 |
-00003f40: 3000 4d32 3550 3132 3800 4e32 3551 3036 0.M25P128.N25Q06 |
-00003f50: 3400 4e32 3551 3132 3800 4e32 3551 3132 4.N25Q128.N25Q12 |
-00003f60: 3841 004e 3235 5132 3536 0043 4246 533a 8A.N25Q256.CBFS: |
-00003f70: 2027 2573 2720 6c6f 6361 7465 6420 4342 '%s' located CB |
-00003f80: 4653 2061 7420 5b25 7a78 3a25 7a78 290a FS at [%zx:%zx). |
-00003f90: 0000 0000 04e4 0002 0000 0000 c1ca 0002 ................ |
-00003fa0: 4342 4653 2040 2025 7a78 2073 697a 6520 CBFS @ %zx size |
-00003fb0: 257a 780a 0073 7263 2f6c 6962 2f63 6266 %zx..src/lib/cbf |
-00003fc0: 732e 6300 4d61 7374 6572 2048 6561 6465 s.c.Master Heade |
-00003fd0: 7220 4c6f 6361 746f 7200 0000 0000 0000 r Locator....... |
-00003fe0: 0000 0000 ecdd 0002 0000 0000 ffff ffff ................ |
-00003ff0: 6661 6c6c 6261 636b 2f72 6f6d 7374 6167 fallback/romstag |
-00004000: 6500 436f 756c 646e 2774 206c 6f61 6420 e.Couldn't load |
-00004010: 726f 6d73 7461 6765 2e0a 0057 6564 204a romstage...Wed J |
-00004020: 616e 2020 3320 3036 3a32 393a 3532 2055 an 3 06:29:52 U |
-00004030: 5443 2032 3031 3800 0034 2e36 2d32 3438 TC 2018..4.6-248 |
-00004040: 302d 6764 3037 3835 3039 3866 3239 312d 0-gd0785098f291- |
-00004050: 6469 7274 7900 0000 0000 0019 0800 0019 dirty........... |
-00004060: 0c00 0019 1000 0019 1400 0019 1800 0019 ................ |
-00004070: 1c00 0019 2000 0019 2400 0019 3400 0019 .... ...$...4... |
-00004080: 3800 0019 3c00 0019 4000 0019 4400 0019 8...<...@...D... |
-00004090: 0001 0019 0002 0019 0402 0019 1002 0019 ................ |
-000040a0: 0003 0019 0004 0019 000a 0019 040a 0019 ................ |
-000040b0: 080a 0019 0c0a 0019 100a 0019 140a 0019 ................ |
-000040c0: 000c 0019 040c 0019 080c 0019 0c0c 0019 ................ |
-000040d0: 100c 0019 140c 0019 180c 0019 1c0c 0019 ................ |
-000040e0: 200c 0019 240c 0019 000e 0019 040e 0019 ...$........... |
-000040f0: 080e 0019 100e 0019 200e 0019 240e 0019 ........ ...$... |
-00004100: 400e 0019 480e 0019 640e 0019 c00e 0019 @...H...d....... |
-00004110: c40e 0019 000f 0019 040f 0019 080f 0019 ................ |
-00004120: 7472 7573 747a 6f6e 6520 696e 6974 6961 trustzone initia |
-00004130: 6c69 7a65 640a 0046 6169 6c65 6420 746f lized..Failed to |
-00004140: 2062 7269 6e67 2050 4c33 3330 2044 4d41 bring PL330 DMA |
-00004150: 4320 6f75 7420 6f66 2072 6573 6574 0a00 C out of reset.. |
-00004160: 504c 3333 3020 444d 4143 2069 6e69 7469 PL330 DMAC initi |
-00004170: 616c 697a 6564 0a00 4c43 4420 696e 6974 alized..LCD init |
-00004180: 6961 6c69 7a65 640a 0056 3344 2069 6e69 ialized..V3D ini |
-00004190: 7469 616c 697a 6564 0a00 6175 6469 6f20 tialized..audio |
-000041a0: 696e 6974 6961 6c69 7a65 640a 0046 6169 initialized..Fai |
-000041b0: 6c65 6420 746f 2061 636b 204e 454f 4e20 led to ack NEON |
-000041c0: 706f 7765 7220 6f6e 0a00 4661 696c 6564 power on..Failed |
-000041d0: 2074 6f20 6163 6b20 4e45 4f4e 2070 6f77 to ack NEON pow |
-000041e0: 6572 206f 6b0a 006e 656f 6e20 696e 6974 er ok..neon init |
-000041f0: 6961 6c69 7a65 640a 0050 4349 6520 696e ialized..PCIe in |
-00004200: 6974 6961 6c69 7a65 640a 004d 3020 696e itialized..M0 in |
-00004210: 6974 6961 6c69 7a65 640a 0043 4355 2069 itialized..CCU i |
-00004220: 6e69 7469 616c 697a 6564 0a00 5344 494f nitialized..SDIO |
-00004230: 2069 6e69 7469 616c 697a 6564 0a00 4661 initialized..Fa |
-00004240: 696c 6564 2074 6f20 6272 696e 6720 5344 iled to bring SD |
-00004250: 494f 206f 7574 206f 6620 7265 7365 740a IO out of reset. |
-00004260: 0000 0000 51d7 0002 e5d4 0002 35d4 0002 ....Q.......5... |
-00004270: 01d5 0002 39c5 0002 ffff 0000 0000 0000 ....9........... |
-00004280: 0000 0000 0000 0000 a4e6 0002 0000 0000 ................ |
-00004290: 0000 0000 0100 0000 0800 001a 1000 001a ................ |
-000042a0: 1400 001a 3800 001a 3c00 001a 7400 001a ....8...<...t... |
-000042b0: 7800 001a 7c00 001a 8000 001a 8400 001a x...|........... |
-000042c0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000042d0: 0000 0000 80de 0002 0000 0000 0000 2000 .............. . |
-000042e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000042f0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004300: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004310: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004320: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004330: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004340: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004350: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004360: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004370: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004380: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004390: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043a0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043b0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043c0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043d0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043e0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-000043f0: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004400: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004410: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
-00004420: 0000 0000 0000 0000 0000 0000 0000 0000 ................ |
diff --git a/util/broadcom/secimage/test/data/input/configfile.xxdump b/util/broadcom/secimage/test/data/input/configfile.xxdump
deleted file mode 100644
index 97e0167..0000000
--- a/util/broadcom/secimage/test/data/input/configfile.xxdump
+++ /dev/null
@@ -1,41 +0,0 @@
-00000000: 2f2f 2055 6e61 7574 6820 4865 6164 6572 // Unauth Header |
-00000010: 0a2f 2f0a 2f2f 2073 7472 7563 7420 556e .//.// struct Un |
-00000020: 4175 7468 656e 7469 6361 7465 6448 6561 AuthenticatedHea |
-00000030: 6465 725f 7420 7b0a 2f2f 0975 696e 7433 der_t {.//.uint3 |
-00000040: 325f 7420 5461 673b 0909 2f2a 2054 6167 2_t Tag;../* Tag |
-00000050: 2075 7365 6420 746f 206c 6f63 6174 6520 used to locate |
-00000060: 626f 6f74 2062 696e 6172 7920 696e 206d boot binary in m |
-00000070: 656d 6f72 7920 2a2f 0a2f 2f09 7569 6e74 emory */.//.uint |
-00000080: 3332 5f74 204c 656e 6774 683b 092f 2a20 32_t Length;./* |
-00000090: 4c65 6e67 7468 206f 6620 7468 6520 626f Length of the bo |
-000000a0: 6f74 2062 696e 6172 7920 2a2f 0a2f 2f09 ot binary */.//. |
-000000b0: 7569 6e74 3332 5f74 2052 6573 6572 7665 uint32_t Reserve |
-000000c0: 643b 092f 2a20 4164 6472 6573 7320 666f d;./* Address fo |
-000000d0: 7220 7468 6520 6e6f 6e2d 6175 7468 656e r the non-authen |
-000000e0: 7469 6361 7465 6420 626f 6f74 2e0a 2f2f ticated boot..// |
-000000f0: 0909 0909 2020 2054 6865 2061 6464 7265 .... The addre |
-00000100: 7373 2069 7320 616c 6967 6e65 6420 746f ss is aligned to |
-00000110: 2031 3620 6279 7465 7320 626f 756e 6461 16 bytes bounda |
-00000120: 7279 2e0a 2f2f 0909 0909 2020 2054 6865 ry..//.... The |
-00000130: 206c 6f77 6572 2034 2062 6974 7320 6172 lower 4 bits ar |
-00000140: 6520 7573 6564 2066 6f72 2043 6c6b 436f e used for ClkCo |
-00000150: 6e66 6967 3a0a 2f2f 0909 0909 2020 2056 nfig:.//.... V |
-00000160: 616c 7565 2020 2046 7265 710a 2f2f 0909 alue Freq.//.. |
-00000170: 0909 2020 2031 2020 2020 2020 2034 3030 .. 1 400 |
-00000180: 0a2f 2f09 0909 0920 2020 3220 2020 2020 .//.... 2 |
-00000190: 2020 3147 487a 0a2f 2f09 0909 0920 2020 1GHz.//.... |
-000001a0: 3320 2020 2020 2020 4d61 7820 2831 2e32 3 Max (1.2 |
-000001b0: 4748 7a29 0a2f 2f09 0909 0920 2020 3420 GHz).//.... 4 |
-000001c0: 2020 2020 2020 6e6f 2050 4c4c 206c 6f63 no PLL loc |
-000001d0: 6b3a 2032 3030 4d48 7a0a 2f2f 0909 0909 k: 200MHz.//.... |
-000001e0: 202a 2f0a 2f2f 0975 696e 7433 325f 7420 */.//.uint32_t |
-000001f0: 6372 633b 0909 2f2a 2043 5243 2063 6f6d crc;../* CRC com |
-00000200: 7075 7465 6420 6f6e 2061 6c6c 206f 7468 puted on all oth |
-00000210: 6572 2066 6965 6c64 7320 696e 2074 6869 er fields in thi |
-00000220: 730a 2f2f 0909 0909 2020 2073 7472 7563 s.//.... struc |
-00000230: 7475 7265 2065 7863 6c75 6469 6e67 2063 ture excluding c |
-00000240: 7263 2066 6965 6c64 202a 2f0a 2f2f 207d rc field */.// } |
-00000250: 3b0a 5461 673d 0909 3078 4135 4135 4135 ;.Tag=..0xA5A5A5 |
-00000260: 4135 0a4c 656e 6774 683d 0909 3078 3030 A5.Length=..0x00 |
-00000270: 3030 3030 3030 0a52 6573 6572 7665 643d 000000.Reserved= |
-00000280: 2020 0930 7830 3030 3030 3030 320a .0x00000002. |
diff --git a/util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump b/util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump
deleted file mode 100644
index 9c0a23c..0000000
--- a/util/broadcom/secimage/test/data/input/hmac_binary_key.xxdump
+++ /dev/null
@@ -1,2 +0,0 @@
-00000000: d1ef bcba d798 d871 003d ee3b f7b8 461c .......q.=.;..F. |
-00000010: 53a8 b9c5 b6dc 57dc 1280 631d aea3 e003 S.....W...c..... |
diff --git a/util/broadcom/secimage/test/hmac.sh b/util/broadcom/secimage/test/hmac.sh
deleted file mode 100755
index ded0eb7..0000000
--- a/util/broadcom/secimage/test/hmac.sh
+++ /dev/null
@@ -1,78 +0,0 @@
-#!/usr/bin/env bash
-
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2003-2018 Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 3 or later of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## SPDX-License-Identifier: GPL-3.0-or-later
-## <https://spdx.org/licenses/GPL-3.0-or-later.html>
-##
-
-set -o errexit
-set -o nounset
-set -o pipefail
-
-# static analysis
-if command -v shellcheck 1>/dev/null; then
- shellcheck "${BASH_SOURCE[0]}"
-else
- echo "shellcheck not found, running unchecked" >&2
-fi
-
-# dependency check
-dependencies=(basename diff dirname head mkdir mktemp openssl rm tail xxd)
-for dependency in "${dependencies[@]}"; do
- if ! command -v "${dependency}" 1>/dev/null; then
- echo "missing ${dependency}, test skipped" >&2
- exit 0
- fi
-done
-
-# parameters
-if [ ${#} -ne 1 ]; then
- echo "usage: '${0}' <testee>"
- exit 1
-fi
-
-# setup
-testee="${1}"
-declare -i header_len=16 signature_len=32
-tmp_dir="$(mktemp --directory --tmpdir secimage-test-XXXXXXXX)"
-shopt -s globstar nullglob
-for dump_file in test/data/**/*.xxdump; do
- bin_file_dir="${tmp_dir}/$(dirname "${dump_file#test/data/}")"
- mkdir --parents "${bin_file_dir}"
- xxd -r "${dump_file}" \
- "${bin_file_dir}/$(basename "${dump_file}" .xxdump)"
-done
-tail --bytes=+$((header_len + 1)) "${tmp_dir}/expected/binary" \
- | head --bytes=-${signature_len} \
- | openssl dgst -sha256 -mac hmac \
- -macopt hexkey:"$(xxd -c$((signature_len * 2)) -ps \
- "${tmp_dir}/input/hmac_binary_key")" \
- -binary \
- > "${tmp_dir}/expected/signature"
-mkdir "${tmp_dir}/actual"
-
-# test
-"${testee}" \
- -out "${tmp_dir}/actual/binary" \
- -config "${tmp_dir}/input/configfile" \
- -hmac "${tmp_dir}/input/hmac_binary_key" \
- -bl "${tmp_dir}/input/binary"
-tail --bytes=${signature_len} "${tmp_dir}/actual/binary" \
- > "${tmp_dir}/actual/signature"
-diff --recursive "${tmp_dir}/actual" "${tmp_dir}/expected" 1>/dev/null
-
-# teardown
-rm --force --recursive "${tmp_dir}"
diff --git a/util/broadcom/unauth.cfg b/util/broadcom/unauth.cfg
deleted file mode 100644
index fd81a9c..0000000
--- a/util/broadcom/unauth.cfg
+++ /dev/null
@@ -1,20 +0,0 @@
-// Unauth Header
-//
-// struct UnAuthenticatedHeader_t {
-// uint32_t Tag; /* Tag used to locate boot binary in memory */
-// uint32_t Length; /* Length of the boot binary */
-// uint32_t Reserved; /* Address for the non-authenticated boot.
-// The address is aligned to 16 bytes boundary.
-// The lower 4 bits are used for ClkConfig:
-// Value Freq
-// 1 400
-// 2 1GHz
-// 3 Max (1.2GHz)
-// 4 no PLL lock: 200MHz
-// */
-// uint32_t crc; /* CRC computed on all other fields in this
-// structure excluding crc field */
-// };
-Tag= 0xA5A5A5A5
-Length= 0x00000000
-Reserved= 0x00000002
diff --git a/util/testing/Makefile.inc b/util/testing/Makefile.inc
index dddb765..2b98730 100644
--- a/util/testing/Makefile.inc
+++ b/util/testing/Makefile.inc
@@ -60,7 +60,6 @@
echo
TOOLLIST= \
-broadcom/secimage \
cbmem \
ectool \
futility \