broadcom: Remove SoC and board support

The reason for this code cleanup is the legacy
Google Purin board which isn't available anymore
and AFAIK never made it into the stores.

* Remove broadcom cygnus SoC support
* Remove /util/broadcom tool
* Remove Google Purin mainboard
* Remove MAINTAINERS entries

Change-Id: I148dd7eb0192d396cb69bc26c4062f88a764771a
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29905
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/Documentation/util.md b/Documentation/util.md
index 59f2c3b..d76c294 100644
--- a/Documentation/util.md
+++ b/Documentation/util.md
@@ -18,7 +18,6 @@
 `Yacc`
 * __board_status__ - Tools to collect logs and upload them to the board
 status repository `Bash` `Go`
-* __broadcom__ - Generate Broadcom secure boot image. `C`
 * __cavium__ - Devicetree_convert Tool to convert a DTB to a static C
 file `Python`
 * __cbfstool__
diff --git a/MAINTAINERS b/MAINTAINERS
index 8ff21a8..810bb35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -404,12 +404,10 @@
 F:	src/cpu/allwinner/
 F:	src/cpu/armltd/
 F:	src/cpu/ti/
-F:	src/soc/broadcom/
 F:	src/soc/marvell/
 F:	src/soc/qualcomm/
 F:	src/soc/samsung/
 F:	util/arm_boot_tools/
-F:	util/broadcom/
 F:	util/exynos/
 F:	util/ipqheader/
 
diff --git a/Makefile.inc b/Makefile.inc
index aaae7bc..1d6a671 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -93,7 +93,7 @@
 subdirs-y += src/superio
 subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*)
 subdirs-y += src/cpu src/vendorcode
-subdirs-y += util/cbfstool util/sconfig util/nvramtool util/broadcom
+subdirs-y += util/cbfstool util/sconfig util/nvramtool
 subdirs-y += util/futility util/marvell util/bincfg
 subdirs-y += $(wildcard src/arch/*)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
diff --git a/src/mainboard/google/purin/Kconfig b/src/mainboard/google/purin/Kconfig
deleted file mode 100644
index 0453b5e..0000000
--- a/src/mainboard/google/purin/Kconfig
+++ /dev/null
@@ -1,53 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_GOOGLE_PURIN
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_2048
-	select COMMON_CBFS_SPI_WRAPPER
-	select MAINBOARD_HAS_CHROMEOS
-	select SOC_BROADCOM_CYGNUS
-	select SPI_FLASH
-	select SPI_FLASH_SPANSION
-	select SPI_FLASH_STMICRO # required for the reference board BCM958305K
-	select MAINBOARD_HAS_I2C_TPM_GENERIC
-	select MAINBOARD_HAS_TPM1
-
-config VBOOT
-	select VBOOT_VBNV_FLASH
-
-config MAINBOARD_DIR
-	string
-	default google/purin
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Purin"
-
-config MAINBOARD_VENDOR
-	string
-	default "Google"
-
-config DRAM_SIZE_MB
-	int
-	default 256
-
-config GBB_HWID
-	string
-	depends on CHROMEOS
-	default "Purin TEST 1"
-endif #  BOARD_GOOGLE_PURIN
diff --git a/src/mainboard/google/purin/Kconfig.name b/src/mainboard/google/purin/Kconfig.name
deleted file mode 100644
index db960087..0000000
--- a/src/mainboard/google/purin/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_GOOGLE_PURIN
-	bool "Purin"
diff --git a/src/mainboard/google/purin/Makefile.inc b/src/mainboard/google/purin/Makefile.inc
deleted file mode 100644
index 5f13a8b..0000000
--- a/src/mainboard/google/purin/Makefile.inc
+++ /dev/null
@@ -1,36 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-bootblock-y += bootblock.c
-bootblock-y += boardid.c
-bootblock-y += chromeos.c
-bootblock-y += reset.c
-
-verstage-y += boardid.c
-verstage-y += chromeos.c
-verstage-y += reset.c
-
-romstage-y += boardid.c
-romstage-y += chromeos.c
-romstage-y += reset.c
-
-ramstage-y += boardid.c
-ramstage-y += chromeos.c
-ramstage-y += mainboard.c
-ramstage-y += reset.c
-
-bootblock-y += memlayout.ld
-verstage-y += memlayout.ld
-romstage-y += memlayout.ld
-ramstage-y += memlayout.ld
diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt
deleted file mode 100644
index 878db18..0000000
--- a/src/mainboard/google/purin/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Vendor name: Google
-Board name: Purin Broadcom Cygnus reference board
-Category: eval
-ROM protocol: SPI
-ROM socketed: n
-Flashrom support: y
diff --git a/src/mainboard/google/purin/boardid.c b/src/mainboard/google/purin/boardid.c
deleted file mode 100644
index 901d837..0000000
--- a/src/mainboard/google/purin/boardid.c
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <boardid.h>
-
-uint32_t board_id(void)
-{
-	return -1;
-}
diff --git a/src/mainboard/google/purin/bootblock.c b/src/mainboard/google/purin/bootblock.c
deleted file mode 100644
index 18c1f5f..0000000
--- a/src/mainboard/google/purin/bootblock.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 20145Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <bootblock_common.h>
-
-void bootblock_mainboard_init(void)
-{
-}
diff --git a/src/mainboard/google/purin/chromeos.c b/src/mainboard/google/purin/chromeos.c
deleted file mode 100644
index 5e7cdfe..0000000
--- a/src/mainboard/google/purin/chromeos.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <boot/coreboot_tables.h>
-#include <vendorcode/google/chromeos/chromeos.h>
-
-void fill_lb_gpios(struct lb_gpios *gpios)
-{
-}
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}
-
-int get_write_protect_state(void)
-{
-	return 0;
-}
diff --git a/src/mainboard/google/purin/chromeos.fmd b/src/mainboard/google/purin/chromeos.fmd
deleted file mode 100644
index 3f4ca84..0000000
--- a/src/mainboard/google/purin/chromeos.fmd
+++ /dev/null
@@ -1,32 +0,0 @@
-FLASH@0x0 0x200000 {
-	WP_RO@0x0 0x100000 {
-		RO_SECTION@0x0 0xf0000 {
-			BOOTBLOCK@0 128K
-			COREBOOT(CBFS)@0x20000 0x60000
-			FMAP@0x80000 0x1000
-			GBB@0x81000 0x6ef00
-			RO_FRID@0xeff00 0x100
-		}
-		RO_VPD@0xf0000 0x10000
-	}
-	RW_SECTION_A@0x100000 0x58000 {
-		VBLOCK_A@0x0 0x2000
-		FW_MAIN_A(CBFS)@0x2000 0x55f00
-		RW_FWID_A@0x57f00 0x100
-	}
-	RW_SHARED@0x158000 0x4000 {
-		SHARED_DATA@0x0 0x4000
-	}
-	RW_ELOG@0x15c000 0x4000
-	RW_GPT@0x160000 0x20000 {
-		RW_GPT_PRIMARY@0x0 0x10000
-		RW_GPT_SECONDARY@0x10000 0x10000
-	}
-	RW_SECTION_B@0x180000 0x58000 {
-		VBLOCK_B@0x0 0x2000
-		FW_MAIN_B(CBFS)@0x2000 0x55f00
-		RW_FWID_B@0x57f00 0x100
-	}
-	RW_VPD@0x1d8000 0x8000
-	RW_NVRAM@0x1e0000 0x10000
-}
diff --git a/src/mainboard/google/purin/devicetree.cb b/src/mainboard/google/purin/devicetree.cb
deleted file mode 100644
index 6ef5c3b..0000000
--- a/src/mainboard/google/purin/devicetree.cb
+++ /dev/null
@@ -1,19 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# TODO fill with Versatile Express board data in QEMU.
-chip soc/broadcom/cygnus
-	device cpu_cluster 0 on end
-end
diff --git a/src/mainboard/google/purin/mainboard.c b/src/mainboard/google/purin/mainboard.c
deleted file mode 100644
index bc7b545..0000000
--- a/src/mainboard/google/purin/mainboard.c
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <boot/coreboot_tables.h>
-#include <symbols.h>
-
-static void mainboard_init(struct device *dev)
-{
-}
-
-static void mainboard_enable(struct device *dev)
-{
-	dev->ops->init = &mainboard_init;
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-};
-
-void lb_board(struct lb_header *header)
-{
-	struct lb_range *dma;
-
-	dma = (struct lb_range *)lb_new_record(header);
-	dma->tag = LB_TAB_DMA;
-	dma->size = sizeof(*dma);
-	dma->range_start = (uintptr_t)_dma_coherent;
-	dma->range_size = _dma_coherent_size;
-}
diff --git a/src/mainboard/google/purin/memlayout.ld b/src/mainboard/google/purin/memlayout.ld
deleted file mode 100644
index 2c33306..0000000
--- a/src/mainboard/google/purin/memlayout.ld
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/memlayout.ld>
diff --git a/src/mainboard/google/purin/reset.c b/src/mainboard/google/purin/reset.c
deleted file mode 100644
index 51a2187..0000000
--- a/src/mainboard/google/purin/reset.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <reset.h>
-
-void do_board_reset(void)
-{
-}
diff --git a/src/soc/broadcom/Kconfig b/src/soc/broadcom/Kconfig
deleted file mode 100644
index 18c46c1..0000000
--- a/src/soc/broadcom/Kconfig
+++ /dev/null
@@ -1,2 +0,0 @@
-# Load all chipsets
-source "src/soc/broadcom/*/Kconfig"
diff --git a/src/soc/broadcom/cygnus/Kconfig b/src/soc/broadcom/cygnus/Kconfig
deleted file mode 100644
index e2f97e4..0000000
--- a/src/soc/broadcom/cygnus/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2014 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-config SOC_BROADCOM_CYGNUS
-	bool
-	default n
-	select ARCH_BOOTBLOCK_ARMV7
-	select ARCH_RAMSTAGE_ARMV7
-	select ARCH_ROMSTAGE_ARMV7
-	select ARCH_VERSTAGE_ARMV7
-	select BOOTBLOCK_CONSOLE
-	select GENERIC_UDELAY
-	select HAVE_MONOTONIC_TIMER
-	select HAVE_UART_SPECIAL
-	select GENERIC_GPIO_LIB
-
-if SOC_BROADCOM_CYGNUS
-
-config VBOOT
-	select VBOOT_STARTS_IN_BOOTBLOCK
-	select VBOOT_SEPARATE_VERSTAGE
-	select VBOOT_RETURN_FROM_VERSTAGE
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on DRIVERS_UART
-	default 0x18023000
-
-config CYGNUS_DDR333
-	def_bool n
-
-config CYGNUS_DDR400
-	def_bool n
-
-config CYGNUS_DDR533
-	def_bool n
-
-config CYGNUS_DDR667
-	def_bool n
-
-config CYGNUS_DDR800
-	bool "DDR Speed at 800MHz"
-	default y
-
-config CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE
-	bool "Enable DDR auto self-refresh"
-	default y
-	help
-	  Warning: M0 expects that auto self-refresh is enabled. Modify
-	  with caution.
-
-
-config CYGNUS_SHMOO_REUSE_DDR_32BIT
-	bool "Indicate if DDR width is 32-bit"
-	default n
-
-config CYGNUS_SDRAM_TEST_DDR
-	bool "Run a write-read test on DDR after initialization"
-	default n
-
-config CYGNUS_PRINT_SHMOO_DEBUG
-	bool "Print debug info for shmoo"
-	default n
-
-config CYGNUS_GPIO_TEST
-	bool "Run a test on gpio"
-	default n
-
-endif
diff --git a/src/soc/broadcom/cygnus/Makefile.inc b/src/soc/broadcom/cygnus/Makefile.inc
deleted file mode 100644
index 21c5806..0000000
--- a/src/soc/broadcom/cygnus/Makefile.inc
+++ /dev/null
@@ -1,100 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright 2015 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ifeq ($(CONFIG_SOC_BROADCOM_CYGNUS),y)
-
-bootblock-y += bootblock.c
-bootblock-y += cbmem.c
-bootblock-y += i2c.c
-bootblock-y += timer.c
-bootblock-y += tz.c
-bootblock-y += hw_init.c
-bootblock-$(CONFIG_SPI_FLASH) += spi.c
-ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
-bootblock-y += ns16550.c
-endif
-
-verstage-y += i2c.c
-verstage-y += timer.c
-verstage-$(CONFIG_SPI_FLASH) += spi.c
-verstage-y += ns16550.c
-
-romstage-y += cbmem.c
-romstage-y += i2c.c
-romstage-y += timer.c
-romstage-y += romstage.c
-romstage-y += sdram.c
-romstage-$(CONFIG_SPI_FLASH) += spi.c
-romstage-y += ns16550.c
-romstage-y += ddr_init.c
-romstage-y += ddr_init_table.c
-romstage-y += shmoo_and28.c
-romstage-y += phy_reg_access.c
-romstage-y += ydc_ddr_bist.c
-romstage-y += timer.c
-romstage-y += gpio.c
-romstage-y += iomux.c
-
-ramstage-y += cbmem.c
-ramstage-y += i2c.c
-ramstage-y += sdram.c
-ramstage-y += soc.c
-ramstage-y += timer.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
-ramstage-y += ns16550.c
-ramstage-y += usb.c
-
-CPPFLAGS_common += -Isrc/soc/broadcom/cygnus/include/
-
-ifneq ($(V),1)
-redirect := > /dev/null
-endif
-
-# Options used in the command line:
-# -out: path of the output file
-# -config: path to the file containing unauth header
-# -hmac: path to the file containing hmac for sha256
-# -bl: boot image file, ie. input file
-#
-# Authenticated header parameters:
-#
-# SBIConfiguration				/* Indicates SBI config */
-#   SYMMETRIC				0x0040
-#
-# CustomerID;			/* Customer ID */
-#   TYPE				bits [31-28]
-#     PRODUCTION			0x6
-#     DEVELOPMENT			0x9
-#   CUSTOMER_ID				bits [27-0]
-#
-# ProductID;			/* Product ID */
-#
-# CustomerRevisionID;		/* Customer Revision ID */
-#
-# SBIUsage			/* Boot Image Usage */
-#   NONE		0	/* All purposes */
-#   SLEEP		1
-#   DEEP_SLEEP		2
-#   EXCEPTION		4
-$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin \
-		$(objutil)/broadcom/secimage/secimage \
-		util/broadcom/unauth.cfg \
-		util/broadcom/khmacsha256
-	@printf "    SIGN       $(subst $(obj)/,,$(@))\n"
-	$(objutil)/broadcom/secimage/secimage -out $@ \
-		-config util/broadcom/unauth.cfg \
-		-hmac util/broadcom/khmacsha256 -bl $<
-
-endif
diff --git a/src/soc/broadcom/cygnus/bootblock.c b/src/soc/broadcom/cygnus/bootblock.c
deleted file mode 100644
index d24895e..0000000
--- a/src/soc/broadcom/cygnus/bootblock.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/cache.h>
-#include <bootblock_common.h>
-#include <stddef.h>
-#include <symbols.h>
-#include <soc/hw_init.h>
-
-void bootblock_soc_init(void)
-{
-	/*
-	 * not only for speed but for preventing the CPU from crashing.
-	 * the CPU is not happy when cache is cleaned without mmu turned on.
-	 */
-	mmu_init();
-	mmu_config_range(0, 4096, DCACHE_OFF);
-	mmu_config_range_kb((uintptr_t)_sram/KiB, _sram_size/KiB,
-			    DCACHE_WRITETHROUGH);
-	dcache_mmu_enable();
-
-	hw_init();
-}
diff --git a/src/soc/broadcom/cygnus/cbmem.c b/src/soc/broadcom/cygnus/cbmem.c
deleted file mode 100644
index 544303b..0000000
--- a/src/soc/broadcom/cygnus/cbmem.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <cbmem.h>
-#include <stddef.h>
-#include <symbols.h>
-#include <soc/sdram.h>
-
-void *cbmem_top(void)
-{
-	return _dram + sdram_size_mb()*MiB;
-}
diff --git a/src/soc/broadcom/cygnus/ddr_init.c b/src/soc/broadcom/cygnus/ddr_init.c
deleted file mode 100644
index e00ae91..0000000
--- a/src/soc/broadcom/cygnus/ddr_init.c
+++ /dev/null
@@ -1,1672 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#include <delay.h>
-#include <console/console.h>
-#include <soc/config.h>
-#include <soc/reg_utils.h>
-
-#define DDR_CTL_TYPE_1 1
-#define DDR_DRAM_TYPE_DDR3L 31
-
-extern unsigned int ddr_init_tab[];
-#ifdef DDR2_SUPPORT
-extern unsigned int ddr2_init_tab[];
-extern unsigned int ddr2_init_tab_400[];
-extern unsigned int ddr2_init_tab_667[];
-extern unsigned int ddr2_init_tab_800[];
-extern unsigned int ddr2_init_tab_1066[];
-extern unsigned int ddr2_mode_reg_tab[];
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
-#define CYGNUS_DRAM_FREQ 333
-extern unsigned int ddr3_init_tab_667[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
-#define CYGNUS_DRAM_FREQ 400
-extern unsigned int ddr3_init_tab_800[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
-#define CYGNUS_DRAM_FREQ 533
-extern unsigned int ddr3_init_tab_1066[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
-#define CYGNUS_DRAM_FREQ 667
-extern unsigned int ddr3_init_tab_1333[];
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-#define CYGNUS_DRAM_FREQ 800
-extern unsigned int ddr3_init_tab_1600[];
-#endif
-
-#define __udelay udelay
-
-/* Local function prototype */
-uint32_t change_ddr_clock(uint32_t clk);
-void dump_phy_regs(void);
-void ddr_init_regs(unsigned int * tblptr);
-void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr);
-void ddr_phy_wl_regs_ovrd(unsigned int * tblptr);
-int is_ddr_32bit(void);
-uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit);
-int cygnus_phy_powerup(void);
-void ddr_init2(void);
-void PRE_SRX(void);
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-void PRE_SRX(void)
-{
-	uint32_t readvalue = 0;
-
-	// Disable low power receivers:  bit 0 of the byte lane STATIC_PAD_CTL register
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL);
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL,
-		    (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R)));
-
-	// Turn off ZQ_CAL drivers: bits 0,1, and 17 of the ZQ_CAL register (other bits 0 & 1 are set to 1)
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL);
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_ZQ_CAL,
-		    (readvalue & ~(1 << DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ)));
-
-	// Byte lane 0 power up
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
-		    (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE)));
-
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
-		    (readvalue & 0xffff800f));
-
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL,
-		    (readvalue & ~(1 << DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ)));
-
-	// Byte lane 1 power up
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
-		    (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE)));
-
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
-		    (readvalue & 0xffff800f));
-
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL,
-		    (readvalue & ~(1 << DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ)));
-
-	// Turn on PHY_CONTROL AUTO_OEB C not required
-	// Enable byte lane AUTO_DQ_RXENB_MODE: bits 18 and 19 of the byte lane IDLE_PAD_CONTROL C already set 180114c8: 000f000a
-
-	printk(BIOS_INFO, "\n....PLL power up.\n");
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
-		    ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN)));
-
-	// PLL out of reset
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
-		    ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET)));
-	printk(BIOS_INFO, "\n....poll lock..\n");
-	// Poll lock
-	readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
-	while ((readvalue & 0x1) == 0x0)
-	{
-		printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_PLL_STATUS = %8x..\n",readvalue);
-		readvalue = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_STATUS);
-	}
-	printk(BIOS_INFO, "\n....after while..\n");
-
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
-		    ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV)));
-
-	printk(BIOS_INFO, "\n....remove hold..\n");
-	// Remove hold
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_CONFIG) &
-		    ~(1<<DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD)));
-	printk(BIOS_INFO, "\n....restore dac..\n");
-
-	// Restore DAC
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL) & 0xffff0fff));
-	printk(BIOS_INFO, "\n....set iddq bit..\n");
-
-	// Set the iddq bit in the idle control register and select all outputs except cke and rst in the idee select registers.
-	//	Do NOT assert any other bits in the idle control register.	(This step can be done during init on power up.)
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
-		    ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ)));
-	printk(BIOS_INFO, "\n....idle pad enable 0..\n");
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0, 0x0);
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1, 0x0);
-	printk(BIOS_INFO, "\n....DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL..\n");
-	reg32_write((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL,
-		    (reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL) &
-		    ~(1 << DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE)));
-}
-
-#endif
-
-#if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7)
-void iproc_ddr_ovrd_ecc_lane(void)
-{
-	uint32_t val;
-
-#define SET_OVR_STEP(v) (0x30000 | ((v) & 0x3F))    /* OVR_FORCE = OVR_EN = 1, OVR_STEP = v */
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_P);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_R_N);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_DM_W);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_P);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT0_R_N);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_P);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT1_R_N);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_P);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT2_R_N);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_P);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT3_R_N);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE0_BIT_RD_EN);
-	val = SET_OVR_STEP(val & 0xff);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_DATA_DLY);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_DATA_DLY, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_READ_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_CONTROL, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_IDLE_PAD_CONTROL);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_DRIVE_PAD_CTL);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_DRIVE_PAD_CTL, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	val = reg32_read((volatile uint32_t *)DDR_PHY_WORD_LANE_0_WR_PREAMBLE_MODE);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE, val);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-
-	__udelay(200);
-	reg32_write((volatile uint32_t *)DDR_PHY_ECC_LANE_READ_FIFO_CLEAR, 0x1);
-	val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-	__udelay(200);
-}
-
-uint32_t iproc_read_ecc_syndrome(void)
-{
-	volatile uint32_t syndrome = 0;
-	/* Place uncorrectible as bits 7:0, and correctible as 15:8 */
-	syndrome = ((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 3) & 0x1) |
-				(((reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) >> 5) & 0x1));
-	return(syndrome);
-}
-
-void iproc_clear_ecc_syndrome(void)
-{
-	uint32_t val;
-
-	/* Clear the interrupts, bits 6:3 */
-	reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, (1 << 5) | (1<< 3));
-	__udelay(1000);
-}
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-uint32_t iproc_get_ddr3_clock_mhz(uint32_t unit)
-{
-	uint32_t ndiv, mdiv, pdiv, ddrclk, data;
-
-	data = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_PLL_DIVIDERS);
-
-	ndiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R;
-	ndiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH) - 1;
-
-	pdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R;
-	pdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH) - 1;
-
-	mdiv = data >> DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R;
-	mdiv &= (2^DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH) - 1;
-
-	/* read ndiv pdiv and mdiv */
-	ddrclk = (25 * ndiv * 2 * pdiv) / mdiv;
-	printk(BIOS_INFO, "%s DDR PHY PLL divisor: ndiv(0x%x) mdiv(0x%x) ddrclk(0x%x)\n", __FUNCTION__, ndiv, mdiv, ddrclk);
-
-	return(ddrclk);
-}
-
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-
-int cygnus_phy_powerup(void)
-{
-	int data;
-	int count = 15;
-
-	data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
-
-	if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
-	{
-		/* Step 1: POWER ON */
-		data = reg32_read((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL);
-		data |= 0x8;// assert power ON
-		reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-		__udelay(2);
-
-		/* Step 2: POWER OK */
-		data |= 0x10;// assert power OK
-		reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-		while (count--)
-			__udelay(2);
-
-	}
-	else
-	{
-		printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 1\n");
-	}
-
-	/* Step 3: DFI normal mode */
-	data &= ~(0x04);// remove DFI isolation
-	reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-
-	/* Step 4: Enable register access */
-	data &= ~(0x02);// remove PHY register isolation
-	reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-	data &= ~(0x01);// remove PLL isolation
-	reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-
-	count = 20;
-	while (count--)
-		__udelay(2);
-
-	if (reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG)==0)
-	{
-		/* Step 5: release reset */
-		data |= 0x20;// de-assert reset
-		reg32_write((volatile uint32_t *)CRMU_DDR_PHY_AON_CTRL, data);
-	}
-	else
-	{
-		printk(BIOS_INFO, "DeepSleep wakeup: ddr phy init bypassed 2\n");
-	}
-	while ((reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x08) != 0x08) {
-		//poll DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb
-	}
-
-	return 0;
-}
-
-#endif
-
-uint32_t change_ddr_clock(uint32_t clk)
-{
-	return(0);
-}
-
-void dump_phy_regs(void)
-{
-	int i;
-	printk(BIOS_DEBUG, "\n PHY register dump: Control registers\n");
-	for (i = 0; i <= 0x94; i+=4)
-	{
-		printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
-			*(volatile uint32_t *)(DDR_PHY_CONTROL_REGS_REVISION + i));
-	}
-
-	printk(BIOS_DEBUG, "\n PHY register dump: Wordlane0 registers\n");
-	for (i = 0; i <= 0xc5; i+=4)
-	{
-		printk(BIOS_DEBUG, "0x%03x,\t0x%08x,\n", i,
-			*(volatile uint32_t *)(DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P + i));
-	}
-
-	return;
-}
-
-void ddr_init_regs(unsigned int * tblptr)
-{
-	unsigned int offset = *tblptr;
-	unsigned int *addr = (unsigned int *)DDR_DENALI_CTL_00;
-
-	while (offset != 0xffffffff) {
-		++tblptr;
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-		addr[offset] = *tblptr;
-#else
-		addr[offset] = swap_u32(*tblptr);
-#endif
-		++tblptr;
-		offset = *tblptr;
-	}
-}
-
-void ddr_phy_ctl_regs_ovrd(unsigned int * tblptr)
-{
-	unsigned int offset = *tblptr;
-	unsigned int *addr = (unsigned int *)DDR_PHY_CONTROL_REGS_REVISION;
-	unsigned int val;
-
-	while (offset != 0xffffffff) {
-		++tblptr;
-#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
-		addr[offset/4] = *tblptr;
-#else
-		addr[offset/4] = swap_u32(*tblptr);
-#endif
-		val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-		if (val) ;
-		++tblptr;
-		offset = *tblptr;
-	}
-}
-
-void ddr_phy_wl_regs_ovrd(unsigned int * tblptr)
-{
-}
-
-/*DDR_SHMOO_RELATED_CHANGE*/
-
-#ifdef CONFIG_RUN_DDR_SHMOO
-int ReWriteModeRegisters(void)
-{
-	int nRet = 0;
-	int j = 100;
-
-	reg32_clear_bits((volatile uint32_t *)DDR_DENALI_CTL_89, 1 << 18);
-
-	/* Set mode register for MR0, MR1, MR2 and MR3 write for all chip selects */
-	reg32_write((volatile uint32_t *)DDR_DENALI_CTL_43, (1 << 17) | (1 << 24) | (1 << 25));
-
-	/* Trigger Mode Register Write(MRW) sequence */
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_43, 1 << 25);
-
-	do {
-		if (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) {
-			break;
-		}
-		--j;
-	} while (j);
-
-	if (j == 0 && (reg32_read((volatile uint32_t *)DDR_DENALI_CTL_89) & (1 << 18)) == 0) {
-		printk(BIOS_ERR, "Error: DRAM mode registers write failed\n");
-		nRet = 1;
-	};
-
-	return nRet;
-}
-#endif /* CONFIG_RUN_DDR_SHMOO */
-
-
-int is_ddr_32bit(void)
-{
-	int ddr32 = 0;
-
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT)
-	ddr32=1;
-#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) */
-
-	return ddr32;
-}
-
-
-static uint32_t get_ddr_clock(uint32_t sku_id, int ddr_type)
-{
-#ifdef CYGNUS_DRAM_FREQ
-	return  CYGNUS_DRAM_FREQ;
-#else
-	#error Please set DDR frequency (CYGNUS_DRAM_FREQ must be set)
-#endif
-}
-
-#if defined(CONFIG_SHMOO_REUSE) || defined(CONFIG_SHMOO_AND28_REUSE)
-
-#define RAND_MAGIC_1    0x0000444BUL
-#define RAND_MAGIC_2    0x88740000UL
-#define RAND_MAGIC_3    69069UL
-#define RAND_SEED       0x5301beef
-#define RAND_SEED_2     ((RAND_SEED << 21) + (RAND_SEED << 14) + (RAND_SEED << 7))
-#define RAND_C_INIT     (((RAND_SEED_2 + RAND_MAGIC_1) << 1) + 1)
-#define RAND_T_INIT     ((RAND_SEED_2 << (RAND_SEED_2 & 0xF)) + RAND_MAGIC_2)
-
-static int simple_memory_test(void *start, uint32_t len)
-{
-	register uint32_t rand_c_value, rand_t_value, rand_value;
-	register uint32_t i;
-	register volatile uint32_t *paddr;
-
-	len /= 4;
-	paddr = (volatile uint32_t *)start;
-	rand_c_value = RAND_C_INIT;
-	rand_t_value = RAND_T_INIT;
-	for (i=0; i<len; i++, paddr++) {
-		rand_c_value *= RAND_MAGIC_3;
-		rand_t_value ^= rand_t_value >> 15;
-		rand_t_value ^= rand_t_value << 17;
-		rand_value = rand_t_value ^ rand_c_value;
-		*paddr = rand_value;
-	}
-
-	paddr = (volatile uint32_t *)start;
-	rand_c_value = RAND_C_INIT;
-	rand_t_value = RAND_T_INIT;
-	for (i=0; i<len; i++, paddr++) {
-		rand_c_value *= RAND_MAGIC_3;
-		rand_t_value ^= rand_t_value >> 15;
-		rand_t_value ^= rand_t_value << 17;
-		rand_value = rand_t_value ^ rand_c_value;
-		if (*paddr != rand_value) {
-			return -1;
-		}
-	}
-
-	return 0;
-}
-
-#endif /* CONFIG_SHMOO_REUSE || CONFIG_SHMOO_AND28_REUSE */
-
-#if defined(CONFIG_RUN_DDR_SHMOO2) && defined(CONFIG_SHMOO_REUSE)
-
-#define SHMOO_HEADER_MAGIC      "SHMO"
-#define SHMOO_MIN_BLOCK_SIZE    0x10000
-
-static const uint16_t ddr_phy_ctl_regs[] = {
-	0x030,
-	0x034,
-	0x06c
-};
-
-static const uint16_t ddr_phy_wl_regs[] = {
-	0x000,
-	0x004,
-	0x008,
-	0x00c,
-	0x010,
-	0x014,
-	0x018,
-	0x01c,
-	0x020,
-	0x024,
-	0x028,
-	0x02c,
-	0x030,
-	0x034,
-	0x038,
-	0x03c,
-	0x040,
-	0x044,
-	0x048,
-	0x04c,
-	0x050,
-	0x054,
-	0x058,
-	0x05c,
-	0x060,
-	0x064,
-	0x068,
-	0x06c,
-	0x070,
-	0x074,
-	0x0a4,
-	0x0a8,
-	0x0ac,
-	0x0b0,
-	0x0b4,
-	0x0b8,
-	0x0bc,
-	0x0c0,
-	0x0c4,
-	0x0c8,
-	0x0cc,
-	0x0d0,
-	0x0d4,
-	0x0d8,
-	0x0dc,
-	0x0e0,
-	0x0e4,
-	0x0e8,
-	0x0ec,
-	0x0f0,
-	0x0f4,
-	0x0f8,
-	0x0fc,
-	0x100,
-	0x104,
-	0x108,
-	0x10c,
-	0x110,
-	0x114,
-	0x118,
-	0x11c,
-	0x120,
-	0x124,
-	0x128,
-	0x12c,
-	0x130,
-	0x134,
-	0x138,
-	0x13c,
-	0x140,
-	0x144,
-	0x148,
-	0x14c,
-	0x150,
-	0x154,
-	0x158,
-	0x15c,
-	0x160,
-	0x164,
-	0x168,
-	0x16c,
-	0x1a0,
-	0x1a4,
-	0x1a8,
-	0x1ac,
-	0x1b0
-};
-#if defined(CONFIG_IPROC_DDR_ECC) && !defined(CONFIG_IPROC_P7)
-static const uint16_t ddr_phy_eccl_regs[] = {
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_P_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_R_N_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_DM_W_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_P_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT0_R_N_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_P_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT1_R_N_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_P_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT2_R_N_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_P_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT3_R_N_BASE,
-	DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE,
-	DDR_PHY_ECC_LANE_READ_DATA_DLY_BASE,
-	DDR_PHY_ECC_LANE_READ_CONTROL_BASE,
-	DDR_PHY_ECC_LANE_IDLE_PAD_CONTROL_BASE,
-	DDR_PHY_ECC_LANE_DRIVE_PAD_CTL_BASE,
-	DDR_PHY_ECC_LANE_WR_PREAMBLE_MODE_BASE,
-};
-#endif
-#if defined(CONFIG_IPROC_NAND) && defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
-	nand_info_t *nand;
-	int ret = 0;
-	uint32_t offset = CONFIG_SHMOO_REUSE_NAND_OFFSET;
-	uint32_t end = offset + CONFIG_SHMOO_REUSE_NAND_RANGE;
-	uint32_t blksize;
-
-	/* Get flash handle */
-	nand = &nand_info[0];
-	if (nand->size < offset || nand->writesize == 0 || nand->erasesize == 0) {
-		printk(BIOS_ERR, "Failed to initialize NAND flash for saving Shmoo values!\n");
-		return -1;
-	}
-
-	/* For NAND with bad blocks, we always erase all blocks in the range */
-	{
-		nand_erase_options_t opts;
-		memset(&opts, 0, sizeof(opts));
-		opts.offset = offset / nand->erasesize * nand->erasesize;
-		opts.length = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / nand->erasesize * nand->erasesize + 1;
-		opts.quiet  = 1;
-		ret = nand_erase_opts(nand, &opts);
-		if (ret) {
-			printk(BIOS_ERR, "NAND flash erase failed, error=%d\n", ret);
-			return ret;
-		}
-	}
-
-	/* Write data */
-	blksize = nand->erasesize > SHMOO_MIN_BLOCK_SIZE?
-	nand->erasesize : SHMOO_MIN_BLOCK_SIZE;
-	while (offset < end) {
-		if (nand_block_isbad(nand, offset)) {
-			offset += blksize;
-			continue;
-		}
-		ret = nand_write(nand, offset, (size_t *)&length, (u_char *)buf);
-		if (ret) {
-			printk(BIOS_ERR, "NAND flash write failed, error=%d\n", ret);
-		}
-		break;
-	}
-
-	return ret;
-}
-
-#elif defined(CONFIG_SPI_FLASH) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) && CONFIG_ENV_IS_IN_SPI_FLASH
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
-	struct spi_flash flash;
-	int erase = 0;
-	volatile uint32_t *flptr;
-	int i, j, ret = 0;
-	uint32_t offset = CONFIG_SHMOO_REUSE_QSPI_OFFSET;
-
-	/* Check if erasing is required */
-	flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + offset / 4 * 4);
-	j = (length - 1) / 4 + 1;
-	for (i=0; i<j; i++, flptr++) {
-		if (*flptr != 0xFFFFFFFF) {
-		erase = 1;
-		break;
-		}
-	}
-
-	/* Probe flash */
-	if (spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, &flash)) {
-		printk(BIOS_ERR, "Failed to initialize SPI flash for saving Shmoo values!\n");
-		return -1;
-	}
-
-	/* Erase if necessary */
-	if (erase) {
-		ret = spi_flash_erase(
-			&flash,
-			offset / flash->sector_size * flash->sector_size,
-			flash->sector_size
-			);
-		if (ret) {
-			printk(BIOS_ERR, "SPI flash erase failed, error=%d\n", ret);
-			return ret;
-		}
-	}
-
-	/* Write data */
-	ret = spi_flash_write(&flash, offset, length, buf);
-	if (ret) {
-		printk(BIOS_ERR, "SPI flash write failed, error=%d\n", ret);
-	}
-
-	return ret;
-}
-
-#elif defined(CONFIG_ENV_IS_IN_FLASH)
-
-static int write_shmoo_to_flash(void *buf, int length)
-{
-	int erase = 0;
-	volatile uint32_t *flptr, shmoo_start;
-	int i, j, ret = 0;
-	uint32_t offset = CONFIG_SHMOO_REUSE_NOR_OFFSET;
-	int sect_len;
-
-	/* Check if erasing is required */
-	flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + offset / 4 * 4);
-	shmoo_start = flptr;
-	j = (length - 1) / 4 + 1;
-	for (i=0; i<j; i++, flptr++) {
-		if (*flptr != 0xFFFFFFFF) {
-			erase = 1;
-			break;
-		}
-	}
-
-	sect_len = (((length / 0x20000) + 1)*0x20000 - 1);
-	/* Erase if necessary */
-	if (erase) {
-		ret = flash_sect_erase((ulong)shmoo_start, (ulong)shmoo_start + sect_len);
-		if (ret) {
-			printk(BIOS_ERR, "NOR flash erase failed, error=%d, start addr: 0x%x, end addr: 0x%x\n",
-		                ret, (ulong)shmoo_start, (ulong)shmoo_start + sect_len);
-			return ret;
-		}
-	}
-
-	/* Write data */
-	ret = flash_write((char *)buf, (ulong)shmoo_start, length);
-
-	if (ret) {
-		printk(BIOS_ERR, "NOR flash write failed, error=%d\n", ret);
-	}
-
-
-	return ret;
-
-}
-#else
- #error Flash (SPI or NAND) must be enabled
-#endif
-
-/* Return flash pointer; or NULL if validation failed */
-static volatile uint32_t *validate_flash_shmoo_values(struct shmoo_signature *psig, int *ppairs)
-{
-	uint32_t dev_id, sku_id, ddr_type, ddr_clk;
-	volatile uint32_t *ptr;
-	volatile uint32_t *flptr;
-	struct shmoo_signature sig;
-	uint32_t checksum, pairs, length;
-	uint32_t chksum;
-	int offset;
-	int i;
-	int numpairs = 1;
-
-	if (is_ddr_32bit()) {
-		numpairs = 2;
-	}
-
-    /* Calculate required length (register/value pair) */
-	pairs =
-	sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]) +
-	sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]) * numpairs;
-#ifdef CONFIG_IPROC_DDR_ECC
-	pairs += sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]);
-#endif
-
-	if (ppairs != NULL) {
-		*ppairs = pairs;
-	}
-
-#if defined(CONFIG_ENV_IS_IN_NAND) && CONFIG_ENV_IS_IN_NAND
-	/* Read SHMOO data from NAND */
-	flptr = (volatile uint32_t *)(IPROC_NAND_MEM_BASE + CONFIG_SHMOO_REUSE_NAND_OFFSET);
-	offset = (CONFIG_SHMOO_REUSE_NAND_RANGE - 1) / SHMOO_MIN_BLOCK_SIZE * SHMOO_MIN_BLOCK_SIZE;
-#elif defined(CONFIG_ENV_IS_IN_FLASH)
-	/* Read SHMOO data from NOR */
-	flptr = (volatile uint32_t *)(IPROC_NOR_MEM_BASE + CONFIG_SHMOO_REUSE_NOR_OFFSET);
-	offset = 0;
-#else
-	/* Read SHMOO data from SPI */
-	flptr = (volatile uint32_t *)(IPROC_QSPI_MEM_BASE + CONFIG_SHMOO_REUSE_QSPI_OFFSET);
-	offset = 0;
-#endif
-
-	/* Get chip type and DDR type/clock */
-	dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff;
-	sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
-	ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1;
-	ddr_clk = get_ddr_clock(sku_id, ddr_type);
-
-	/* Construct signature */
-	memcpy(sig.magic, SHMOO_HEADER_MAGIC, 4);
-	sig.dev_id = dev_id;
-	sig.sku_id = sku_id;
-	sig.ddr_type = ddr_type;
-	sig.ddr_clock = ddr_clk;
-
-	/* Provide signature data to caller */
-	if (psig) {
-		memcpy(psig, &sig, sizeof(sig));
-	}
-
-	/* Check signature (in min-blocks from bottom) */
-	while (offset >= 0) {
-		ptr = flptr + offset;
-		if (!shmoo_sigmemcmp(&sig,(void *)ptr)) {
-			break;
-		}
-		offset -= SHMOO_MIN_BLOCK_SIZE;
-	}
-	if (offset < 0) {
-		printk(BIOS_ERR, " Signature mismatch ");
-		return NULL;
-	}
-	ptr += 3;
-
-	/* Verify checksum */
-	checksum = *ptr++;
-	length = *ptr++;
-	if (pairs != length) {
-		/* Pair count unmatched */
-		printk(BIOS_ERR, " Pair count mismatch pairs %x length %x",pairs, length);
-		return NULL;
-	}
-	chksum = 0;
-	for (i=0; i<length * 2; i++, ptr++) {
-		chksum += *ptr;
-	}
-	if (chksum != checksum) {
-		printk(BIOS_ERR, " Checksum mismatch cksum: %x checksum:%x",chksum,checksum);
-		return NULL;
-	}
-
-	return flptr + offset;
-}
-
-static int try_restore_shmoo(void)
-{
-    int invalid = 0;
-    struct shmoo_signature sig;
-    volatile uint32_t *flptr;
-    volatile uint32_t *reg;
-    uint32_t val;
-    int pairs, i;
-
-    /* Validate values in flash */
-    printk(BIOS_INFO, "Validate Shmoo parameters stored in flash ..... ");
-    flptr = validate_flash_shmoo_values(&sig, &pairs);
-    if (flptr == NULL) {
-        printk(BIOS_ERR, "failed\n");
-        return 1;
-    }
-    printk(BIOS_INFO, "OK\n");
-
-    /* Check if user wants to skip restoring and run Shmoo */
-    if (CONFIG_SHMOO_REUSE_DELAY_MSECS > 0) {
-        char c = 0;
-        unsigned long start;
-        printk(BIOS_INFO, "Press Ctrl-C to run Shmoo ..... ");
-        start = get_timer(0);
-        while (get_timer(start) <= CONFIG_SHMOO_REUSE_DELAY_MSECS) {
-            if (tstc()) {
-                c = getc();
-                if (c == 0x03) {
-                    printk(BIOS_INFO, "Pressed.\n");
-                    printk(BIOS_INFO, "Do you want to run the Shmoo? [y/N] ");
-                    for (;;) {
-                        c = getc();
-                        if (c == 'y' || c == 'Y') {
-                            printk(BIOS_INFO, "Y\n");
-                            invalid = 1;
-                            break;
-                        } else if (c == '\r' || c == 'n' || c == 'N') {
-                            if (c != '\r')
-                                printk(BIOS_INFO, "N\n");
-                            break;
-                        }
-                    }
-                    break;
-                } else {
-                    c = 0;
-                }
-            }
-        }
-        if (c == 0)
-            printk(BIOS_INFO, "skipped\n");
-    }
-
-    if (invalid) {
-        return 1;
-    }
-
-    /* Restore values from flash */
-    printk(BIOS_INFO, "Restoring Shmoo parameters from flash ..... ");
-    flptr += 5;
-    for (i=0; i<pairs; i++) {
-        reg = (uint32_t *)(*flptr++);
-        val = (uint32_t *)(*flptr++);
-	if ( (((uint32_t)reg >= DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
-		|| (((uint32_t)reg >= DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN) && ((uint32_t)reg <= (DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + 0x114)))
-#endif
-#ifdef CONFIG_IPROC_DDR_ECC
-		|| (((uint32_t)reg >= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_RD_EN_BASE)) && ((uint32_t)reg <= (DDR_DENALI_CTL_00 + DDR_PHY_ECC_LANE_VDL_OVRIDE_BYTE_BIT_RD_EN_BASE)))
-#endif
-	) {
-		val |= (1 << 17); /* Force Override */
-	}
-	// printk(BIOS_INFO, "Writing 0x%x to 0x%x\n",val,reg);
-	reg32_write(reg, val);
-
-	reg32_read(reg); /* Dummy read back */
-	}
-	printk(BIOS_INFO, "done\n");
-
-	/* Perform memory test to see if the parameters work */
-	if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
-		printk(BIOS_INFO, "Running simple memory test ..... ");
-		i = simple_memory_test((void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
-		    CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
-		if (i) {
-			printk(BIOS_ERR, "failed!\n");
-			return 1;
-		}
-		printk(BIOS_INFO, "OK\n");
-	}
-
-    return 0;
-}
-
-#define SHMOO_REG_BUFFER_SIZE 100;
-static uint32_t shmoo_reg_buffer[SHMOO_REG_BUFFER_SIZE];
-
-void iproc_save_shmoo_values(void)
-{
-    uint32_t *buffer, *ptr;
-    volatile uint32_t *flptr;
-    uint32_t reg, val;
-    struct shmoo_signature sig;
-    int pairs, length;
-    uint32_t chksum;
-    int i;
-
-    /* Check if flash already contains valid data  */
-    flptr = validate_flash_shmoo_values(&sig, &pairs);
-    if (flptr != NULL) {
-        /* Check if the flash data are the same as current DDR PHY values */
-        flptr += 5;
-	for (i=0; i<pairs; i++) {
-	    reg = *flptr++;
-	    val = *flptr++;
-            if (val != reg32_read(reg)) {
-                break;
-            }
-
-	}
-	if (i == pairs) {
-		/* No difference found; Saving skipped */
-	    return;
-	}
-    }
-
-    /* Calculate size of buffer */
-    length = 12 +
-        sizeof(uint32_t) * 2 +
-        sizeof(uint32_t) * pairs * 2;
-
-    /* Allocate buffer */
-	if (length > size(uint32_t) * SHMOO_REG_BUFFER_SIZE) {
-        printk(BIOS_INFO, "Error pre-allocated shmoo register buffer is not large enough!\n");
-        return;
-	}
-
-    buffer = shmoo_reg_buffer;
-    ptr = buffer;
-
-    /* Fill signature */
-    shmoo_sig2mem(&sig,ptr);
-    ptr += 5;
-
-    /* Copy registers and values to buffer */
-    chksum = 0;
-    for (i=0; i<sizeof(ddr_phy_ctl_regs) / sizeof(ddr_phy_ctl_regs[0]); i++) {
-        reg = (uint32_t)DDR_PHY_CONTROL_REGS_REVISION + ddr_phy_ctl_regs[i];
-        *ptr++ = reg;
-        chksum += reg;
-        // val = *(volatile uint32_t *)reg;
-        val = reg32_read((volatile uint32_t *)reg);
-        *ptr++ = val;
-        chksum += val;
-    }
-    for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
-        reg = (uint32_t)DDR_PHY_WORD_LANE_0_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
-        *ptr++ = reg;
-        chksum += reg;
-        // val = *(volatile uint32_t *)reg;
-        val = reg32_read((volatile uint32_t *)reg);
-	*ptr++ = val;
-        chksum += val;
-    }
-#if IS_ENABLED(CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT) || defined(CONFIG_NS_PLUS)
-	if (is_ddr_32bit()) {
-	    for (i=0; i<sizeof(ddr_phy_wl_regs) / sizeof(ddr_phy_wl_regs[0]); i++) {
-	        reg = (uint32_t)DDR_PHY_WORD_LANE_1_VDL_OVRIDE_BYTE_RD_EN + ddr_phy_wl_regs[i];
-	        *ptr++ = reg;
-	        chksum += reg;
-	        // val = *(volatile uint32_t *)reg;
-		val = reg32_read((volatile uint32_t *)reg);
-		*ptr++ = val;
-	        chksum += val;
-	    }
-	}
-#endif /* (CONFIG_CYGNUS_SHMOO_REUSE_DDR_32BIT || defined(CONFIG_NS_PLUS)) */
-#ifdef CONFIG_IPROC_DDR_ECC
-    for (i=0; i<sizeof(ddr_phy_eccl_regs) / sizeof(ddr_phy_eccl_regs[0]); i++) {
-        reg = (uint32_t)DDR_DENALI_CTL_00 + ddr_phy_eccl_regs[i];
-        *ptr++ = reg;
-        chksum += reg;
-        // val = *(volatile uint32_t *)reg;
-        val = reg32_read((volatile uint32_t *)reg);
-	*ptr++ = val;
-        chksum += val;
-    }
-#endif
-
-    /* Fill checksum and length */
-    buffer[3] = chksum;
-    buffer[4] = pairs;
-
-    /* Write to flash */
-    printk(BIOS_INFO, "Writing Shmoo values into flash .....\n");
-    i = write_shmoo_to_flash(buffer, length);
-
-    /* Free buffer */
-//    free(buffer);
-}
-
-#endif /* CONFIG_RUN_DDR_SHMOO2 && CONFIG_SHMOO_REUSE */
-
-#include "soc/ddr_bist.h"
-#include "soc/shmoo_and28/shmoo_and28.h"
-
-#ifdef CONFIG_IPROC_DDR_ECC
-static int clear_ddr(uint32_t offset, uint32_t size)
-{
-	unsigned long start;
-	unsigned int i, val;
-
-	reg32_write((uint32_t *)DDR_BistConfig,
-		    reg32_read((uint32_t *)DDR_BistConfig) & ~0x1);
-
-	for (i = 0; i < 1000; i++)
-		;
-
-#if !defined(CONFIG_IPROC_P7)
-	reg32_write((volatile uint32_t *)DDR_DENALI_CTL_213, 0x00FFFFFF);
-#endif
-
-	reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000002);
-	reg32_write((volatile uint32_t *)DDR_BistConfig, 0x00000003);
-	reg32_write((volatile uint32_t *)DDR_BistConfig, 0x0000C003);
-	reg32_write((volatile uint32_t *)DDR_BistGeneralConfigurations, 0x00000020);
-
-	val =  255 << DDR_BistConfigurations__WriteWeight_R |
-		  0 << DDR_BistConfigurations__ReadWeight_R |
-		  1 << DDR_BistConfigurations__ConsAddr8Banks;
-
-	reg32_write((volatile uint32_t *)DDR_BistConfigurations, val);
-
-
-	reg32_write((volatile uint32_t *)DDR_BistStartAddress, offset);
-	reg32_write((volatile uint32_t *)DDR_BistEndAddress, (1 << DDR_BistEndAddress__BistEndAddress_WIDTH) - 1);
-	reg32_write((volatile uint32_t *)DDR_BistNumberOfActions, (size + 31) / 32);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord0, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord1, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord2, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord3, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord4, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord5, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord6, 0);
-	reg32_write((volatile uint32_t *)DDR_BistPatternWord7, 0);
-
-	reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__IndWrRdAddrMode);
-
-	reg32_set_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
-
-	start = get_timer(0);
-	while (get_timer(start) <= 10000) {
-		if (reg32_read((volatile uint32_t *)DDR_BistStatuses) & (1 << DDR_BistStatuses__BistFinished))
-			break;
-	}
-	/* Clear BIST_EN bit */
-	reg32_clear_bits((volatile uint32_t *)DDR_BistConfigurations, 1 << DDR_BistConfigurations__BistEn);
-
-	if ((get_timer(start) <= 10000)  &&
-	   (!reg32_read((volatile uint32_t *)DDR_BistErrorOccurred)))
-	{
-		printk(BIOS_INFO, "clear_ddr: OK\n");
-		return(0);
-	}
-	printk(BIOS_INFO, "clear_ddr: Failed: 0x%lx\n", get_timer(start));
-	if (reg32_read((volatile uint32_t *)DDR_BistErrorOccurred))
-		printk(BIOS_ERR, "clear_ddr: Error occurred\n");
-	return(1);
-}
-#endif /* CONFIG_IPROC_DDR_ECC */
-
-#if defined(CONFIG_SHMOO_AND28_REUSE)
-extern void restore_shmoo_config(and28_shmoo_config_param_t *shmoo_control_para);
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-static int simple_ddr_crc32_check(void)
-{
-	return 0;
-	register uint32_t crc_mcu = 0;
-	register uint32_t crc = 0, offset = 0;
-	register volatile uint32_t *buf = (uint32_t *)0x60000000;
-	register uint32_t len = 0x00100000;//in word
-
-	printk(BIOS_INFO, "Checking simple DDR CRC, word start 0x%p, len 0x%08x...\n", buf, len);
-
-	for (offset=0; offset<len; offset++)
-	{
-		crc ^= *buf++;
-	}
-
-	crc_mcu = reg32_read((volatile uint32_t *)0x03012A00);
-
-	if (crc != crc_mcu)
-	{
-		printk(BIOS_ERR, "DDR CRC NOT match, old=0x%08x, new=0x%08x!\n", crc_mcu, crc);
-		return -1;
-	}
-	else
-	{
-		printk(BIOS_INFO, "DDR CRC 0x%08x, match!\n", crc);
-		return 0;
-	}
-}
-#endif
-
-void ddr_init2(void)
-{
-	int i;
-	volatile unsigned int val;
-	int ddr_type;
-	uint32_t status, sku_id, ddr_clk, dev_id = 0;
-	uint32_t unit = 0;
-	uint32_t skip_shmoo = 0;
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	uint32_t pwrctli0 = reg32_read((volatile uint32_t *)IHOST_SCU_POWER_STATUS)  & 0x3;
-	skip_shmoo = reg32_read((volatile uint32_t *)CRMU_IHOST_POR_WAKEUP_FLAG) & 0x1;
-
-	if (pwrctli0==2)
-	{
-		goto wakeup;
-	}
-	else if (pwrctli0==3)
-	{
-		skip_shmoo = 1;
-		reg32_write((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL, reg32_read((volatile uint32_t *)IHOST_GTIM_GLOB_CTRL)| 0x1);
-	}
-#endif	/* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
-
-	dev_id = dev_id;
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	and28_shmoo_dram_info_t sdi;
-	and28_shmoo_config_param_t config_param;
-#endif
-
-#if !IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	dev_id = (reg32_read((volatile uint32_t *)ChipcommonA_ChipID)) & 0x0000ffff;
-#else
-    dev_id = 0x5800;
-    cygnus_phy_powerup();
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 8) & 0x0f;
-#else
-	sku_id = (reg32_read((volatile uint32_t *)ROM_S0_IDM_IO_STATUS) >> 2) & 0x03;
-#endif
-	/* See if it is KATANA2, KATANA2 doesn't have right chip ID in ChipcommonA_ChipID */
-	if (((sku_id & 0xfff0) == 0xa450) || ((sku_id & 0xfff0) == 0xb450) || sku_id == 0xb248) {
-		dev_id = 56450; /* KATANA2 */
-	}
-
-	printk(BIOS_INFO, "DEV ID = 0x%x\n", dev_id);
-
-	printk(BIOS_INFO, "SKU ID = 0x%x\n", sku_id);
-
-#if defined(CONFIG_IPROC_P7)
-	val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x3;
-	if (val == 0) {
-		ddr_type = 1;
-	} else if (val == 1) {
-		ddr_type = 2;
-	} else {
-		printk(BIOS_ERR, "Unsupported DDR type: %d\n", val);
-		goto done;
-	}
-    printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type == 1)? 3 : 4);
-#elif IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-    ddr_type = 1;
-#else
-	ddr_type = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS) & 0x1;
-	printk(BIOS_INFO, "DDR type: DDR%d\n", (ddr_type) ? 3 : 2);
-#endif /* defined(CONFIG_IPROC_P7) */
-
-	ddr_clk = get_ddr_clock(sku_id, ddr_type);
-	printk(BIOS_INFO, "MEMC 0 DDR speed = %dMHz\n", ddr_clk);
-
-	status = change_ddr_clock(ddr_clk);
-	if (status) {
-		printk(BIOS_INFO, "CRU LCPLL configuratioin failed\n");
-		goto done;
-	}
-
-#if defined(CONFIG_IPROC_P7)
-	val = reg32_read((volatile uint32_t *)CRU_ddrphy_pwr_ctrl);
-
-	/* assert power ON */
-	val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwronin_phy;
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* assert power OK */
-	__udelay(10);
-	val |= 1 << CRU_ddrphy_pwr_ctrl__i_pwrokin_phy;
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* remove DFI isolation */
-	__udelay(150);
-	val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_dfi);
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* remove PHY register isolation */
-	val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_regs);
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* remove PLL isolation */
-	val &= ~(1 << CRU_ddrphy_pwr_ctrl__i_iso_phy_pll);
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* de-assert reset */
-	__udelay(200);
-	val |= 1 << CRU_ddrphy_pwr_ctrl__i_hw_reset_n;
-	reg32_write((volatile uint32_t *)CRU_ddrphy_pwr_ctrl, val);
-
-	/* Wait for PHY power up */
-	for (i=0; i < 0x19000; i++) {
-		val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
-		if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb)))
-			break;
-	}
-	if (i == 0x19000) {
-		printk(BIOS_ERR, "DDR PHY not power up\n");
-		goto done;
-	}
-#endif /* defined(CONFIG_IPROC_P7) */
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7)
-	/* Get the DDR S1 and S2 out of reset */
-	reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0);
-	reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
-
-	__udelay(1000);
-	reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0);
-	/* Set the ddr_ck to 400 MHz, 2x memc clock */
-	reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
-
-	if (pwrctli0==3)
-	{
-		printk(BIOS_INFO, "\n PRE_SRX call\n");
-		PRE_SRX();
-	}
-#else
-    reg32_write((volatile uint32_t *)DDR_S1_IDM_RESET_CONTROL, 0);
-    reg32_write((volatile uint32_t *)DDR_S2_IDM_RESET_CONTROL, 0);
-    /* Set the ddr_ck to 400 MHz, 2x memc clock */
-    reg32_write_masked((volatile uint32_t *)DDR_S1_IDM_IO_CONTROL_DIRECT, 0xfff << 16, /*ddr_clk*/ 0x190 << 16);
-#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) || defined(CONFIG_IPROC_P7) */
-
-#if defined(CONFIG_IPROC_P7)
-	if (is_ddr_32bit()) {
-		reg32_write_masked(
-			(volatile uint32_t *)DDR_S2_IDM_IO_CONTROL_DIRECT,
-				1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b,
-				1 << DDR_S2_IDM_IO_CONTROL_DIRECT__mode_32b
-				);
-	}
-
-	/* Wait for PHY ready */
-	for (i=0; i < 0x19000; i++) {
-		val = reg32_read((volatile uint32_t *)DDR_S1_IDM_IO_STATUS);
-		if ((val & (1 << DDR_S1_IDM_IO_STATUS__o_phy_ready)))
-			break; /* DDR PHY is up */
-	}
-
-	if (i == 0x19000) {
-		printk(BIOS_ERR, "DDR PLL not locked\n");
-		goto done;
-	}
-
-	/* Get the DDR S0 out of reset */
-	reg32_write((volatile uint32_t *)DDR_S0_IDM_RESET_CONTROL, 0);
-#endif /* defined(CONFIG_IPROC_P7) */
-
-	/* Wait for DDR PHY up */
-	for (i=0; i < 0x19000; i++) {
-		val = reg32_read((volatile uint32_t *)DDR_PHY_CONTROL_REGS_REVISION);
-		if (val != 0) {
-			printk(BIOS_INFO, "PHY revision version: 0x%08x\n", val);
-			break; /* DDR PHY is up */
-		}
-	}
-
-	if (i == 0x19000) {
-		printk(BIOS_ERR, "DDR PHY is not up\n");
-		return;
-	}
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	if (!skip_shmoo)
-	{
-		printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
-		/* Cygnus clock speed:
-		*
-		*    clock       rate
-		*    400         800
-		*    533         1066
-		*    667         1333
-		*    800         1600
-		*/
-		sdi.data_rate_mbps = (ddr_clk == 667) ? 1333 : ((ddr_clk == 333) ? 667 : (ddr_clk << 1));
-		sdi.ref_clk_mhz = 50;
-		sdi.ctl_type = DDR_CTL_TYPE_1;
-		sdi.dram_type = DDR_DRAM_TYPE_DDR3L;
-		sdi.dram_bitmap = 0x00000001;
-		sdi.interface_bitwidth = SDI_INTERFACE_BITWIDTH;
-		sdi.num_columns = SDI_NUM_COLUMNS;
-		sdi.num_rows = SDI_NUM_ROWS;
-		sdi.num_banks = SDI_NUM_BANKS;
-		sdi.refi = 7800;
-		sdi.command_parity_latency = 0;
-		sdi.sim_system_mode = 0;
-		printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_dram_info_set\n");
-		soc_and28_shmoo_dram_info_set(unit, &sdi);
-	}
-	else
-	{
-		printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 1\n");
-	}
-#else
-#error "DRAM config is not set"
-#endif
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	if (!skip_shmoo)
-	{
-		printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_phy_init\n");
-		if (soc_and28_shmoo_phy_init(unit, 0) != SOC_E_NONE) {
-
-			printk(BIOS_ERR, "DDR PHY initialization failed\n");
-			goto done;
-		}
-	}
-	else
-	{
-		printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 2\n");
-	}
-#endif
-
-#ifdef CONFIG_RUN_DDR_SHMOO
-	printk(BIOS_DEBUG, "PHY register dump after DDR PHY init\n");
-	dump_phy_regs();
-#endif
-
-	printk(BIOS_INFO, "Programming controller register\n");
-	ddr_init_regs(ddr_init_tab);
-
-    ddr_type = 1;
-	if (ddr_type) {
-		/* DDR3 */
-		switch(ddr_clk) {
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
-			case 333:
-				ddr_init_regs(ddr3_init_tab_667);
-				break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
-			case 400:
-				ddr_init_regs(ddr3_init_tab_800);
-				break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
-			case 533:
-				ddr_init_regs(ddr3_init_tab_1066);
-				break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
-			case 667:
-				ddr_init_regs(ddr3_init_tab_1333);
-				break;
-#endif
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-			case 800:
-				ddr_init_regs(ddr3_init_tab_1600);
-				break;
-#endif
-		}
-	}
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR_AUTO_SELF_REFRESH_ENABLE)
-#if (DDR_AUTO_SELF_REFRESH_IDLE_COUNT > 0) & (DDR_AUTO_SELF_REFRESH_IDLE_COUNT <= 0xff)
-	/* Enable auto self-refresh */
-	reg32_set_bits((unsigned int *)DDR_DENALI_CTL_57,
-		0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
-		0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
-
-	reg32_set_bits((unsigned int *)DDR_DENALI_CTL_58,
-		DDR_AUTO_SELF_REFRESH_IDLE_COUNT << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
-#else
-	#error DDR_AUTO_SELF_REFRESH_IDLE_COUNT out of range
-#endif
-#else
-	/* Disable auto-self refresh */
-	reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_57,
-		0x2 << DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R |
-		0x2 << DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R);
-	reg32_clear_bits((unsigned int *)DDR_DENALI_CTL_58,
-		0xff << DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R);
-#endif
-
-	/* Start the DDR */
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_00, 0x01);
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	if (!skip_shmoo)
-	{
-		while (!(reg32_read((volatile uint32_t *)DDR_DENALI_CTL_175) & 0x100));
-		printk(BIOS_INFO, "ddr_init2: MemC initialization complete\n");
-
-		reg32_set_bits((unsigned int *)DDR_DENALI_CTL_177, 0x00100);
-		reg32_write((unsigned int *)DDR_BistConfig, 0x00000002);
-		reg32_write((unsigned int *)DDR_BistConfig, 0x00000003);
-		reg32_write((unsigned int *)DDR_BistConfig, 0x0000C003);
-		reg32_write((unsigned int *)DDR_BistGeneralConfigurations, 0x00000020);
-
-		printk(BIOS_INFO, "ddr_init2: Calling soc_and28_shmoo_ctl\n");
-  #if defined(CONFIG_SHMOO_AND28_REUSE)
-		if (is_shmoo_data_valid()) {
-			restore_shmoo_config(&config_param);
-			soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RESTORE, &config_param);
-
-    #if defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH)
-			/* Perform memory test to see if the stored SHMMO values work */
-			if (CONFIG_SHMOO_REUSE_MEMTEST_LENGTH > 0) {
-				/* Release DDR to AXI for memory testing */
-				reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
-
-				printk(BIOS_INFO, "Running simple memory test ..... ");
-				i = simple_memory_test(
-					(void *)CONFIG_SHMOO_REUSE_MEMTEST_START,
-					CONFIG_SHMOO_REUSE_MEMTEST_LENGTH);
-				if (i) {
-					printk(BIOS_ERR, "failed!\n");
-
-					/* Connect DDR controller to BIST for SHMOO */
-					reg32_set_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
-
-					/* Perform full SHMOO since stored values don't work */
-					soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
-				} else {
-					printk(BIOS_INFO, "OK\n");
-				}
-			}
-    #endif /* defined(CONFIG_SHMOO_REUSE_MEMTEST_LENGTH) */
-
-		} else {
-			soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
-		}
-  #else
-		soc_and28_shmoo_ctl(unit, 0, SHMOO_AND28_SHMOO_RSVP, 0, 1, SHMOO_AND28_ACTION_RUN, &config_param);
-  #endif /* CONFIG_SHMOO_AND28_REUSE */
-	}
-#endif
-	else
-	{
-		printk(BIOS_INFO, "DeepSleep wakeup: ddr init bypassed 3\n");
-	}
-
-#if defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC)
-	printk(BIOS_INFO, "Enabling DDR ECC correcting and reporting\n");
-
-	/* Clear DDR ECC interrupts if any */
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_177,
-		DDR_DENALI_CTL_177_ECC_MASK);
-
-	/* Disable auto corruption */
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_148,
-		1 << DDR_DENALI_CTL_148__ECC_DISABLE_W_UC_ERR);
-
-	/* Enable ECC correction and reporting */
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_146,
-		1 << DDR_DENALI_CTL_146__ECC_EN);
-
-	/* Initialize DDR so that uninitialized reads won't report ecc error */
-	clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE);
-#elif defined(CONFIG_IPROC_DDR_ECC)
-	printk(BIOS_INFO, "Enabling DDR ECC reporting\n");
-	/* Clear DDR interrupts if any */
-	*(unsigned int *)(DDR_DENALI_CTL_213) = 0x00FFFFFF;
-	__udelay(1000);
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_67, 0x01); //Disable auto correction
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 0x01); //Enable ECC
-
-	clear_ddr(0, CONFIG_PHYS_SDRAM_1_SIZE);
-	printk(BIOS_INFO, "Enabling DDR ECC correction\n");
-	reg32_set_bits((volatile uint32_t *)DDR_DENALI_CTL_66, 1 << 1); //Enable ECC correction
-#endif /* defined(CONFIG_IPROC_P7) && defined(CONFIG_IPROC_DDR_ECC) */
-
-	/* Release DDR slave port to AXI */
-	reg32_clear_bits((volatile uint32_t *)DDR_BistConfig, 1 << DDR_BistConfig__axi_port_sel);
-	printk(BIOS_INFO, "DDR Interface Ready\n");
-
-	//dump_phy_regs();
-
-#if IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS)
-	/* SRX */
-	if (skip_shmoo)
-	{
-		// Enter Self refresh (dummy), to keep Denali happy
-		reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x0a050505);
-
-		__udelay(200);
-		printk(BIOS_INFO, "\nDDR self refresh exit\n");
-
-		// Assert DFI request from PHY to mask any interaction with MEMC
-		reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0xe0);
-		reg32_write((unsigned int *)DDR_PHY_CONTROL_REGS_DFI_CNTRL, 0);
-
-		// Exit Self refresh
-		reg32_write((unsigned int *)DDR_DENALI_CTL_56, 0x09050505);
-	}
-
-	/* Clear iHOST flag */
-	reg32_write((unsigned int *)CRMU_IHOST_POR_WAKEUP_FLAG, 0x0);
-	printk(BIOS_INFO, "IHOST POR WAKEUP FLAG cleared\n");
-
-//	iproc_dump_ddr_regs();
-
-	if (pwrctli0==0)
-		goto done;
-
-wakeup:
-	printk(BIOS_INFO, "Wakeup from %s\n", pwrctli0==2 ? "SLEEP":"DEEPSLEEP");
-
-	if (pwrctli0==3)
-	{
-		__udelay(10000);
-		if (simple_ddr_crc32_check()<0)
-		{
-			printk(BIOS_INFO, "Die...\n");
-			while (1);
-		}
-	}
-
-	/* CRMU_IHOST_SW_PERSISTENT_REG4 = 0x03024c64 */
-	asm(
-		"movw	r3, #0x4c64\n"
-		"movt	r3, #0x0302\n"
-		"ldr	r5, [r3]\n"
-		"mov	lr, #0\n"
-		"mov	pc, r5\n");
-#endif /* IS_ENABLED(CONFIG_SOC_BROADCOM_CYGNUS) */
-
-done:
-	/* Reclaim everything we have previously allocated for temporary usage. */
-//	free_heap();
-	return;
-}
diff --git a/src/soc/broadcom/cygnus/ddr_init_table.c b/src/soc/broadcom/cygnus/ddr_init_table.c
deleted file mode 100644
index 20eb5e6..0000000
--- a/src/soc/broadcom/cygnus/ddr_init_table.c
+++ /dev/null
@@ -1,1810 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-const unsigned int ddr_init_tab[] = {
-        0xffffffff
-	};
-
-#ifdef DDR2_SUPPORT
-const unsigned int ddr2_init_tab[] = {
-		0,	0x00000400,
-		3,	0x00000043,
-		4,	0x000000a7,
-		5,	0x0a040a02,
-		6,	0x04020404,
-		7,	0x05030e14,
-		8,	0x030e1404,
-		9,	0x04020305,
-		10,	0x03005b26,
-		11,	0x04020303,
-		12,	0x03005b26,
-		13,	0x01000003,
-		16,	0x030000c8,
-		17,	0x00860000,
-		18,	0x05050086,
-		20,	0x00002301,
-		21,	0x00230a24,
-		22,	0x00050a24,
-		23,	0x00000200,
-		24,	0x000a0002,
-		25,	0x0002000a,
-		26,	0x00020008,
-		27,	0x00c80008,
-		28,	0x00c80027,
-		29,	0x00000027,
-		30,	0x03000001,
-		31,	0x00030303,
-		44,	0x00085300,
-		45,	0x00000004,
-		46,	0x00040853,
-		48,	0x08530000,
-		49,	0x00000004,
-		50,	0x00040853,
-		52,	0x08530000,
-		53,	0x00000004,
-		54,	0x00040853,
-		56,	0x08530000,
-		57,	0x00000004,
-		58,	0x00040853,
-		82,	0x01030101,
-		108,	0x02020101,
-		109,	0x08080404,
-		110,	0x03020200,
-		111,	0x01000202,
-		128,	0x001d1d00,
-		129,	0x1d1d0001,
-		133,	0x00011d1d,
-		134,	0x00011d1d,
-		137,	0x001d1d00,
-		138,	0x1d1d0001,
-		142,	0x00011d1d,
-		143,	0x00011d1d,
-		146,	0x001d1d00,
-		147,	0x1d1d0001,
-		169,	0x0a240000,
-		172,	0x00000a24,
-		173,	0x000032b4,
-		174,	0x0a240404,
-		177,	0x00000a24,
-		178,	0x000032b4,
-		179,	0x02020404,
-		186,	0x15070303,
-		202,	0x0001046b,
-		203,	0x0001046b,
-		206,	0x01030301,
-		207,	0x00000001,
-		0xffffffff
-};
-
-const unsigned int ddr2_init_tab_400[] = {
-    0,    0x00000400,
-    1,    0x00000000,
-    3,    0x00000050,
-    4,    0x000000c8,
-    5,    0x0c050c02,
-    6,    0x04020405,
-    7,    0x05031015,
-    8,    0x03101504,
-    9,    0x05020305,
-    10,   0x03006d60,
-    11,   0x05020303,
-    12,   0x03006d60,
-    13,   0x01000003,
-    14,   0x05061001,
-    15,   0x000b0b06,
-    16,   0x030000c8,
-    17,   0x00a01212,
-    18,   0x060600a0,
-    19,   0x00000000,
-    20,   0x00003001,
-    21,   0x00300c2d,
-    22,   0x00050c2d,
-    23,   0x00000200,
-    24,   0x000a0002,
-    25,   0x0002000a,
-    26,   0x00020008,
-    27,   0x00c80008,
-    28,   0x00c80037,
-    29,   0x00000037,
-    30,   0x03000001,
-    31,   0x00030303,
-    32,   0x00000000,
-    35,   0x00000000,
-    36,   0x01000000,
-    37,   0x10000000,
-    38,   0x00100400,
-    39,   0x00000400,
-    40,   0x00000100,
-    41,   0x00000000,
-    42,   0x00000001,
-    43,   0x00000000,
-    44,   0x000a6300,
-    45,   0x00000004,
-    46,   0x00040a63,
-    47,   0x00000000,
-    48,   0x0a630000,
-    49,   0x00000004,
-    50,   0x00040a63,
-    51,   0x00000000,
-    52,   0x0a630000,
-    53,   0x00000004,
-    54,   0x00040a63,
-    55,   0x00000000,
-    56,   0x0a630000,
-    57,   0x00000004,
-    58,   0x00040a63,
-    59,   0x00000000,
-    60,   0x00000000,
-    61,   0x00010100,
-    62,   0x00000000,
-    63,   0x00000000,
-    64,   0x00000000,
-    65,   0x00000000,
-    66,   0x00000000,
-    67,   0x00000000,
-    68,   0x00000000,
-    69,   0x00000000,
-    70,   0x00000000,
-    71,   0x00000000,
-    72,   0x00000000,
-    73,   0x00000000,
-    74,   0x00000000,
-    75,   0x00000000,
-    76,   0x00000000,
-    77,   0x00000000,
-    78,   0x01000200,
-    79,   0x02000040,
-    80,   0x00400100,
-    81,   0x00000200,
-    82,   0x01030001,
-    83,   0x01ffff0a,
-    84,   0x01010101,
-    85,   0x03010101,
-    86,   0x01000003,
-    87,   0x0000010c,
-    88,   0x00010000,
-    89,   0x00000000,
-    90,   0x00000000,
-    91,   0x00000000,
-    92,   0x00000000,
-    93,   0x00000000,
-    94,   0x00000000,
-    95,   0x00000000,
-    96,   0x00000000,
-    97,   0x00000000,
-    98,   0x00000000,
-    99,   0x00000000,
-    100,  0x00000000,
-    101,  0x00000000,
-    102,  0x00000000,
-    103,  0x00000000,
-    104,  0x00000000,
-    105,  0x00000000,
-    106,  0x00000000,
-    107,  0x00000000,
-    108,  0x02020101,
-    109,  0x08080404,
-    110,  0x03020200,
-    111,  0x01000202,
-    112,  0x00000200,
-    113,  0x00000000,
-    114,  0x00000000,
-    115,  0x00000000,
-    116,  0x19000000,
-    117,  0x00000028,
-    118,  0x00000000,
-    119,  0x00010001,
-    120,  0x00010001,
-    121,  0x00010001,
-    122,  0x00010001,
-    123,  0x00010001,
-    124,  0x00000000,
-    125,  0x00000000,
-    126,  0x00000000,
-    127,  0x00000000,
-    128,  0x001c1c00,
-    129,  0x1c1c0001,
-    130,  0x00000001,
-    131,  0x00000000,
-    132,  0x00000000,
-    133,  0x00011c1c,
-    134,  0x00011c1c,
-    135,  0x00000000,
-    136,  0x00000000,
-    137,  0x001c1c00,
-    138,  0x1c1c0001,
-    139,  0x00000001,
-    140,  0x00000000,
-    141,  0x00000000,
-    142,  0x00011c1c,
-    143,  0x00011c1c,
-    144,  0x00000000,
-    145,  0x00000000,
-    146,  0x001c1c00,
-    147,  0x1c1c0001,
-    148,  0xffff0001,
-    149,  0x00ffff00,
-    150,  0x0000ffff,
-    151,  0x00000000,
-    152,  0x03030303,
-    153,  0x03030303,
-    156,  0x02006400,
-    157,  0x02020202,
-    158,  0x02020202,
-    160,  0x01020202,
-    161,  0x01010064,
-    162,  0x01010101,
-    163,  0x01010101,
-    165,  0x00020101,
-    166,  0x00000064,
-    167,  0x00000000,
-    168,  0x000a0a00,
-    169,  0x0c2d0000,
-    170,  0x02000200,
-    171,  0x02000200,
-    172,  0x00000c2d,
-    173,  0x00003ce1,
-    174,  0x0c2d0505,
-    175,  0x02000200,
-    176,  0x02000200,
-    177,  0x00000c2d,
-    178,  0x00003ce1,
-    179,  0x02020505,
-    180,  0x80000100,
-    181,  0x04070303,
-    182,  0x0000000a,
-    183,  0x00000000,
-    184,  0x00000000,
-    185,  0x0010ffff,
-    186,  0x16070303,
-    187,  0x0000000f,
-    188,  0x00000000,
-    189,  0x00000000,
-    190,  0x00000000,
-    191,  0x00000000,
-    192,  0x00000000,
-    193,  0x00000000,
-    194,  0x00000204,
-    195,  0x00000000,
-    196,  0x00000000,
-    197,  0x00000000,
-    198,  0x00000000,
-    199,  0x00000000,
-    200,  0x00000000,
-    201,  0x00000000,
-    202,  0x00000050,
-    203,  0x00000050,
-    204,  0x00000000,
-    205,  0x00000040,
-    206,  0x01030301,
-    207,  0x00000001,
-    0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR333)
-const unsigned int ddr3_init_tab_667[] = {
-        0, 0x00000600,
-        1, 0x00000000,
-        2, 0x00000000,
-        3, 0x00000000,
-        4, 0x00000000,
-        5, 0x00000000,
-        6, 0x00000000,
-        7, 0x00000400,
-        8, 0x00000000,
-        9, 0x00000000,
-        10, 0x00000000,
-        11, 0x00000004,
-        12, 0x00000000,
-        13, 0x00000000,
-        15, 0x0001046b,
-        16, 0x00028b0b,
-        17, 0x00000000,
-        18, 0x02000000,
-        19, 0x00050a00,
-        20, 0x00000000,
-        21, 0x00050a00,
-        22, 0x00000000,
-        23, 0x05040400,
-        24, 0x0c110004,
-        25, 0x0a050404,
-        26, 0x11000405,
-        27, 0x0504040c,
-        28, 0x0404040a,
-        29, 0x005b680c,
-        30, 0x040c0303,
-        31, 0x000c0404,
-        32, 0x03005b68,
-        33, 0x05000c03,
-        34, 0x00050505,
-        35, 0x010c0032,
-        41, 0x00000000,
-        43, 0x00570100,
-        44, 0x00000a20,
-        45, 0x00000057,
-        46, 0x00000a20,
-        47, 0x00000005,
-        48, 0x00030003,
-        49, 0x000a000a,
-        50, 0x00000000,
-        51, 0x00000000,
-        52, 0x02000000,
-        53, 0x0200005a,
-        54, 0x0000005a,
-        55, 0x05000001,
-        56, 0x00050505,
-        57, 0x00000000,
-        58, 0x00000000,
-        59, 0x00010000,
-        60, 0x10040010,
-        62, 0x00000200,
-        63, 0x00000000,
-        64, 0x00000001,
-        65, 0x00000000,
-        66, 0x00000000,
-        67, 0x00000000,
-        68, 0x00000000,
-        69, 0x00000000,
-        70, 0x00000000,
-        71, 0x00000000,
-        72, 0x00000000,
-        73, 0x00000000,
-        74, 0x00000000,
-        75, 0x00000000,
-        76, 0x00000000,
-        77, 0x00000000,
-        82, 0x00000000,
-        85, 0x00000046,
-        86, 0x00000000,
-        89, 0x00000000,
-        90, 0x00000000,
-        91, 0x00000000,
-        92, 0x00000000,
-        93, 0x00000000,
-        94, 0x00000000,
-        95, 0x00000000,
-        96, 0x00000000,
-        97, 0x00000000,
-        98, 0x00000210,
-        99, 0x00000046,
-        100, 0x00000000,
-        101, 0x00000210,
-        102, 0x00000046,
-        103, 0x00000000,
-        104, 0x00000000,
-        105, 0x00000000,
-        106, 0x00000000,
-        107, 0x00000000,
-        108, 0x00000000,
-        109, 0x00000000,
-        110, 0x00000000,
-        111, 0x00000000,
-        113, 0x00000000,
-        114, 0x00000000,
-        115, 0x00000000,
-        118, 0x00000000,
-        124, 0x00000000,
-        125, 0x00000000,
-        126, 0x00000000,
-        127, 0x00000000,
-        128, 0x00000000,
-        129, 0x00000000,
-        131, 0x00000000,
-        132, 0x00000000,
-        133, 0x00000000,
-        134, 0x00000000,
-        135, 0x00000000,
-        136, 0x00000000,
-        137, 0x00000000,
-        138, 0x00000000,
-        140, 0x01000000,
-        141, 0x00000001,
-        142, 0x00000000,
-        143, 0x00000000,
-        144, 0x00000000,
-        145, 0x00000000,
-        146, 0x00000000,
-        147, 0x00000000,
-        151, 0x00000000,
-        154, 0x00000000,
-        155, 0x00000000,
-        159, 0x00400100,
-        164, 0x0a020001,
-        167, 0x01010101,
-        169, 0x00000c03,
-        172, 0x01000000,
-        173, 0x00000100,
-        174, 0x00000000,
-        177, 0x00000000,
-        178, 0x00000000,
-        179, 0x00000000,
-        183, 0x00000000,
-        184, 0x00000000,
-        186, 0x00000000,
-        188, 0x00000000,
-        189, 0x00000000,
-        190, 0x00000000,
-        191, 0x00000000,
-        192, 0x00000000,
-        193, 0x00000000,
-        195, 0x00000000,
-        196, 0x01010200,
-        197, 0x00000002,
-        198, 0x06040400,
-        199, 0x00000106,
-        200, 0x00000000,
-        201, 0x02020002,
-        202, 0x02020101,
-        203, 0x02000102,
-        204, 0x00000000,
-        206, 0x00000000,
-        207, 0x00000000,
-        208, 0x00000000,
-        209, 0x0000280d,
-        210, 0x00010000,
-        211, 0x00010000,
-        212, 0x00000003,
-        213, 0x00000000,
-        214, 0x00000000,
-        215, 0x00000000,
-        216, 0x00000000,
-        217, 0x00000000,
-        218, 0x00000000,
-        219, 0x00000000,
-        220, 0x00000000,
-        221, 0x01000000,
-        222, 0x00000001,
-        223, 0x00000100,
-        224, 0x00030300,
-        225, 0x0556AA00,
-        226, 0x000aa955,
-        227, 0x000aa955,
-        228, 0x000556aa,
-        229, 0x000556aa,
-        230, 0x000aa955,
-        231, 0x000aa955,
-        232, 0x030556aa,
-        233, 0x01000001,
-        234, 0x00010300,
-        235, 0x00676700,
-        236, 0x00676700,
-        237, 0x00676700,
-        238, 0x00676700,
-        239, 0x00676700,
-        240, 0x00676700,
-        241, 0x00676700,
-        242, 0x00676700,
-        243, 0x00676700,
-        244, 0x00000000,
-        245, 0x01000000,
-        246, 0x00000001,
-        247, 0x00000101,
-        248, 0x00010100,
-        249, 0x03000000,
-        250, 0x03030303,
-        251, 0x00030303,
-        252, 0x02020064,
-        253, 0x02020202,
-        254, 0x00010202,
-        255, 0x01010064,
-        256, 0x01010101,
-        257, 0x00020101,
-        258, 0x00000064,
-        259, 0x00000000,
-        260, 0x000d0d00,
-        261, 0x00000000,
-        262, 0x00001440,
-        263, 0x02000200,
-        264, 0x02000200,
-        265, 0x00001440,
-        266, 0x00006540,
-        267, 0x00000505,
-        268, 0x00001440,
-        269, 0x02000200,
-        270, 0x02000200,
-        271, 0x00001440,
-        272, 0x00006540,
-        273, 0x02020505,
-        274, 0x000a0100,
-        275, 0x0000000a,
-        276, 0x00000000,
-        277, 0x00000000,
-        278, 0x00000f0a,
-        279, 0x00000000,
-        280, 0x00000000,
-        281, 0x00000000,
-        282, 0x00000000,
-        283, 0x00000000,
-        284, 0x00000103,
-        285, 0x00010003,
-        286, 0x00000003,
-        287, 0x00000000,
-        288, 0x00000000,
-        289, 0x00000000,
-        290, 0x04010000,
-        291, 0x00040404,
-        292, 0x00000000,
-        293, 0x00000000,
-        294, 0x00000000,
-        295, 0x00000000,
-        296, 0x00000000,
-        297, 0x00000000,
-        298, 0x00000000,
-        299, 0x00000000,
-        300, 0x00000000,
-        301, 0x00000000,
-        302, 0x00000000,
-        303, 0x00000000,
-        304, 0x00000000,
-        305, 0x00000000,
-        0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR400)
-const unsigned int ddr3_init_tab_800[] = {
-        14, 0x01000000,
-        36, 0x0a140a0a,
-        37, 0x0100000a,
-        38, 0x0c0c0101,
-        39, 0x00060603,
-        40, 0x00010100,
-        42, 0x00000000,
-        61, 0x00000400,
-        78, 0x00000000,
-        79, 0x00000000,
-        80, 0x00000000,
-        81, 0x00000000,
-        83, 0x00000000,
-        84, 0x00000420,
-        87, 0x00000420,
-        88, 0x00000046,
-        112, 0x00000000,
-        116, 0x00000000,
-        117, 0x00000000,
-        119, 0x00000000,
-        120, 0x00000000,
-        121, 0x00000000,
-        122, 0x00000000,
-        123, 0x00000000,
-        130, 0x00000000,
-        139, 0x00000000,
-        148, 0x00000000,
-        149, 0x00000000,
-        150, 0x00000000,
-        152, 0x00000000,
-        153, 0x00000000,
-        156, 0x00000000,
-        157, 0x01000200,
-        158, 0x02000040,
-        160, 0x00000200,
-        161, 0x00000040,
-        162, 0x00000000,
-        163, 0x01000000,
-        165, 0x0101ffff,
-        166, 0x01010101,
-        168, 0x00000103,
-        170, 0x00000001,
-        171, 0x00000000,
-        175, 0x00000000,
-        176, 0x00000000,
-        180, 0x00000000,
-        181, 0x00000000,
-        182, 0x00000000,
-        185, 0x00000000,
-        187, 0x00000000,
-        194, 0x00000000,
-        205, 0x00000000,
-        0, 0x00000600,
-        1, 0x00000000,
-        2, 0x00000000,
-        3, 0x00000000,
-        4, 0x00000000,
-        5, 0x00000000,
-        6, 0x00000000,
-        7, 0x00000400,
-        8, 0x00000000,
-        9, 0x00000000,
-        10, 0x00000000,
-        11, 0x00000004,
-        12, 0x00000000,
-        13, 0x00000000,
-        15, 0x00013880,
-        16, 0x00030d40,
-        17, 0x00000000,
-        18, 0x02000000,
-        19, 0x00050c00,
-        20, 0x00000000,
-        21, 0x00050c00,
-        22, 0x00000000,
-        23, 0x05040400,
-        24, 0x0e140004,
-        25, 0x0c060404,
-        26, 0x14000405,
-        27, 0x0604040e,
-        28, 0x0404040c,
-        29, 0x006db00c,
-        30, 0x040c0303,
-        31, 0x000c0404,
-        32, 0x03006db0,
-        33, 0x06000c03,
-        34, 0x00060606,
-        35, 0x010c003c,
-        41, 0x00000000,
-        43, 0x00680100,
-        44, 0x00000c28,
-        45, 0x00000068,
-        46, 0x00000c28,
-        47, 0x00000005,
-        48, 0x00030003,
-        49, 0x000a000a,
-        50, 0x00000000,
-        51, 0x00000000,
-        52, 0x02000000,
-        53, 0x0200006c,
-        54, 0x0000006c,
-        55, 0x05000001,
-        56, 0x00050505,
-        57, 0x00000000,
-        58, 0x00000000,
-        59, 0x00010000,
-        60, 0x10040010,
-        62, 0x00000200,
-        63, 0x00000000,
-        64, 0x00000001,
-        65, 0x00000000,
-        66, 0x00000000,
-        67, 0x00000000,
-        68, 0x00000000,
-        69, 0x00000000,
-        70, 0x00000000,
-        71, 0x00000000,
-        72, 0x00000000,
-        73, 0x00000000,
-        74, 0x00000000,
-        75, 0x00000000,
-        76, 0x00000000,
-        77, 0x00000000,
-        82, 0x00000000,
-        85, 0x00000046,
-        86, 0x00000000,
-        89, 0x00000000,
-        90, 0x00000000,
-        91, 0x00000000,
-        92, 0x00000000,
-        93, 0x00000000,
-        94, 0x00000000,
-        95, 0x00000000,
-        96, 0x00000000,
-        97, 0x00000000,
-        98, 0x00000420,
-        99, 0x00000046,
-        100, 0x00000000,
-        101, 0x00000420,
-        102, 0x00000046,
-        103, 0x00000000,
-        104, 0x00000000,
-        105, 0x00000000,
-        106, 0x00000000,
-        107, 0x00000000,
-        108, 0x00000000,
-        109, 0x00000000,
-        110, 0x00000000,
-        111, 0x00000000,
-        113, 0x00000000,
-        114, 0x00000000,
-        115, 0x00000000,
-        118, 0x00000000,
-        124, 0x00000000,
-        125, 0x00000000,
-        126, 0x00000000,
-        127, 0x00000000,
-        128, 0x00000000,
-        129, 0x00000000,
-        131, 0x00000000,
-        132, 0x00000000,
-        133, 0x00000000,
-        134, 0x00000000,
-        135, 0x00000000,
-        136, 0x00000000,
-        137, 0x00000000,
-        138, 0x00000000,
-        140, 0x01000000,
-        141, 0x00000001,
-        142, 0x00000000,
-        143, 0x00000000,
-        144, 0x00000000,
-        145, 0x00000000,
-        146, 0x00000000, // disable ECC
-        147, 0x00000000,
-        151, 0x00000000,
-        154, 0x00000000,
-        155, 0x00000000,
-        159, 0x00400100,
-        164, 0x0a020001,
-        167, 0x01010101,
-        169, 0x00000c03,
-        172, 0x01000000,
-        173, 0x00000100,
-        174, 0x00000000,
-        177, 0x00000000,
-        178, 0x00000000,
-        179, 0x00000000,
-        183, 0x00000000,
-        184, 0x00000000,
-        186, 0x00000000,
-        188, 0x00000000,
-        189, 0x00000000,
-        190, 0x00000000,
-        191, 0x00000000,
-        192, 0x00000000,
-        193, 0x00000000,
-        195, 0x00000000,
-        196, 0x01010200,
-        197, 0x00000002,
-        198, 0x06040400,
-        199, 0x00000106,
-        200, 0x01010000,
-        201, 0x02020002,
-        202, 0x02020101,
-        203, 0x02000102,
-        204, 0x00000000,
-        206, 0x00000000,
-        207, 0x00000000,
-        208, 0x00000000,
-        209, 0x0000280d,
-        210, 0x00010000,
-        211, 0x00010000,
-        212, 0x00000003,
-        213, 0x00000000,
-        214, 0x00000000,
-        215, 0x00000000,
-        216, 0x00000000,
-        217, 0x00000000,
-        218, 0x00000000,
-        219, 0x00000000,
-        220, 0x00000000,
-        221, 0x01000000,
-        222, 0x00000001,
-        223, 0x00000100,
-        224, 0x00030300,
-        225, 0x0556AA00,
-        226, 0x000aa955,
-        227, 0x000aa955,
-        228, 0x000556aa,
-        229, 0x000556aa,
-        230, 0x000aa955,
-        231, 0x000aa955,
-        232, 0x030556aa,
-        233, 0x01000001,
-        234, 0x00010300,
-        235, 0x00676700,
-        236, 0x00676700,
-        237, 0x00676700,
-        238, 0x00676700,
-        239, 0x00676700,
-        240, 0x00676700,
-        241, 0x00676700,
-        242, 0x00676700,
-        243, 0x00676700,
-        244, 0x00000000,
-        245, 0x01000000,
-        246, 0x00000001,
-        247, 0x00000101,
-        248, 0x00010100,
-        249, 0x03000000,
-        250, 0x03030303,
-        251, 0x00030303,
-        252, 0x02020064,
-        253, 0x02020202,
-        254, 0x00010202,
-        255, 0x01010064,
-        256, 0x01010101,
-        257, 0x00020101,
-        258, 0x00000064,
-        259, 0x00000000,
-        260, 0x000d0d00,
-        261, 0x00000000,
-        262, 0x00001850,
-        263, 0x02000200,
-        264, 0x02000200,
-        265, 0x00001850,
-        266, 0x00007990,
-        267, 0x00000505,
-        268, 0x00001850,
-        269, 0x02000200,
-        270, 0x02000200,
-        271, 0x00001850,
-        272, 0x00007990,
-        273, 0x02020505,
-        274, 0x000a0100,
-        275, 0x0000000a,
-        276, 0x00000000,
-        277, 0x00000000,
-        278, 0x00000f0a,
-        279, 0x00000000,
-        280, 0x00000000,
-        281, 0x00000000,
-        282, 0x00000000,
-        283, 0x00000000,
-        284, 0x00000103,
-        285, 0x00010003,
-        286, 0x00000003,
-        287, 0x00000000,
-        288, 0x00000000,
-        289, 0x00000000,
-        290, 0x05000000,
-        291, 0x00040504,
-        292, 0x00000000,
-        293, 0x00000000,
-        294, 0x00000000,
-        295, 0x00000000,
-        296, 0x00000000,
-        297, 0x00000000,
-        298, 0x00000000,
-        299, 0x00000000,
-        300, 0x00000000,
-        301, 0x00000000,
-        302, 0x00000000,
-        303, 0x00000000,
-        304, 0x00000000,
-        305, 0x00000000,
-        0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR533)
-const unsigned int ddr3_init_tab_1066[] = {
-        14, 0x01000000,
-        36, 0x0a140a0a,
-        37, 0x0100000a,
-        38, 0x10100101,
-        39, 0x00080803,
-        40, 0x00010100,
-        42, 0x00000000,
-        61, 0x00000400,
-        78, 0x00000000,
-        79, 0x00000000,
-        80, 0x00000000,
-        81, 0x00000000,
-        83, 0x00000000,
-        84, 0x00000840,
-        87, 0x00000840,
-        88, 0x00000046,
-        112, 0x00000000,
-        116, 0x00000000,
-        117, 0x00000000,
-        119, 0x00000000,
-        120, 0x00000000,
-        121, 0x00000000,
-        122, 0x00000000,
-        123, 0x00000000,
-        130, 0x00000000,
-        139, 0x00000000,
-        148, 0x00000000,
-        149, 0x00000000,
-        150, 0x00000000,
-        152, 0x00000000,
-        153, 0x00000000,
-        156, 0x00000000,
-        157, 0x01000200,
-        158, 0x02000040,
-        160, 0x00000200,
-        161, 0x00000040,
-        162, 0x00000000,
-        163, 0x01000000,
-        165, 0x0101ffff,
-        166, 0x01010101,
-        168, 0x00000103,
-        170, 0x00000001,
-        171, 0x00000000,
-        175, 0x00000000,
-        176, 0x00000000,
-        180, 0x00000000,
-        181, 0x00000000,
-        182, 0x00000000,
-        185, 0x00000000,
-        187, 0x00000000,
-        194, 0x00000000,
-        205, 0x00000000,
-        0, 0x00000600,
-        1, 0x00000000,
-        2, 0x00000000,
-        3, 0x00000000,
-        4, 0x00000000,
-        5, 0x00000000,
-        6, 0x00000000,
-        7, 0x00000600,
-        8, 0x00000000,
-        9, 0x00000000,
-        10, 0x00000000,
-        11, 0x00000006,
-        12, 0x00000000,
-        13, 0x00000000,
-        15, 0x00019f8f,
-        16, 0x00040ee6,
-        17, 0x00000000,
-        18, 0x02000000,
-        19, 0x00061000,
-        20, 0x00000000,
-        21, 0x00061000,
-        22, 0x00000000,
-        23, 0x05040400,
-        24, 0x131a0004,
-        25, 0x10080404,
-        26, 0x1a000405,
-        27, 0x08040413,
-        28, 0x04040410,
-        29, 0x0091dc0c,
-        30, 0x040c0303,
-        31, 0x000c0404,
-        32, 0x030091dc,
-        33, 0x08000c03,
-        34, 0x00080808,
-        35, 0x010c0050,
-        41, 0x00000000,
-        43, 0x008b0100,
-        44, 0x0000102c,
-        45, 0x0000008b,
-        46, 0x0000102c,
-        47, 0x00000005,
-        48, 0x00040004,
-        49, 0x000d000d,
-        50, 0x00000000,
-        51, 0x00000000,
-        52, 0x02000000,
-        53, 0x02000090,
-        54, 0x00000090,
-        55, 0x06000001,
-        56, 0x00060606,
-        57, 0x00000000,
-        58, 0x00000000,
-        59, 0x00010000,
-        60, 0x10040010,
-        62, 0x00000200,
-        63, 0x00000000,
-        64, 0x00000001,
-        65, 0x00000000,
-        66, 0x00000000,
-        67, 0x00000000,
-        68, 0x00000000,
-        69, 0x00000000,
-        70, 0x00000000,
-        71, 0x00000000,
-        72, 0x00000000,
-        73, 0x00000000,
-        74, 0x00000000,
-        75, 0x00000000,
-        76, 0x00000000,
-        77, 0x00000000,
-        82, 0x00000000,
-        85, 0x00000046,
-        86, 0x00000008,
-        89, 0x00000008,
-        90, 0x00000000,
-        91, 0x00000000,
-        92, 0x00000000,
-        93, 0x00000000,
-        94, 0x00000000,
-        95, 0x00000000,
-        96, 0x00000000,
-        97, 0x00000000,
-        98, 0x00000840,
-        99, 0x00000046,
-        100, 0x00000008,
-        101, 0x00000840,
-        102, 0x00000046,
-        103, 0x00000008,
-        104, 0x00000000,
-        105, 0x00000000,
-        106, 0x00000000,
-        107, 0x00000000,
-        108, 0x00000000,
-        109, 0x00000000,
-        110, 0x00000000,
-        111, 0x00000000,
-        113, 0x00000000,
-        114, 0x00000000,
-        115, 0x00000000,
-        118, 0x00000000,
-        124, 0x00000000,
-        125, 0x00000000,
-        126, 0x00000000,
-        127, 0x00000000,
-        128, 0x00000000,
-        129, 0x00000000,
-        131, 0x00000000,
-        132, 0x00000000,
-        133, 0x00000000,
-        134, 0x00000000,
-        135, 0x00000000,
-        136, 0x00000000,
-        137, 0x00000000,
-        138, 0x00000000,
-        140, 0x01000000,
-        141, 0x00000001,
-        142, 0x00000000,
-        143, 0x00000000,
-        144, 0x00000000,
-        145, 0x00000000,
-        146, 0x00000000, // disable ECC
-        147, 0x00000000,
-        151, 0x00000000,
-        154, 0x00000000,
-        155, 0x00000000,
-        159, 0x00400100,
-        164, 0x0a020001,
-        167, 0x01010101,
-        169, 0x00000c03,
-        172, 0x01000000,
-        173, 0x00000100,
-        174, 0x00000000,
-        177, 0x00000000,
-        178, 0x00000000,
-        179, 0x00000000,
-        183, 0x00000000,
-        184, 0x00000000,
-        186, 0x00000000,
-        188, 0x00000000,
-        189, 0x00000000,
-        190, 0x00000000,
-        191, 0x00000000,
-        192, 0x00000000,
-        193, 0x00000000,
-        195, 0x00000000,
-        196, 0x01010200,
-        197, 0x00000002,
-        198, 0x06050500,
-        199, 0x00000106,
-        200, 0x02020000,
-        201, 0x02020002,
-        202, 0x02020101,
-        203, 0x02000102,
-        204, 0x00000000,
-        206, 0x00000000,
-        207, 0x00000000,
-        208, 0x00000000,
-        209, 0x0000280d,
-        210, 0x00010000,
-        211, 0x00010000,
-        212, 0x00000003,
-        213, 0x00000000,
-        214, 0x00000000,
-        215, 0x00000000,
-        216, 0x00000000,
-        217, 0x00000000,
-        218, 0x00000000,
-        219, 0x00000000,
-        220, 0x00000000,
-        221, 0x01000000,
-        222, 0x00000001,
-        223, 0x00000100,
-        224, 0x00030300,
-        225, 0x0556AA00,
-        226, 0x000aa955,
-        227, 0x000aa955,
-        228, 0x000556aa,
-        229, 0x000556aa,
-        230, 0x000aa955,
-        231, 0x000aa955,
-        232, 0x030556aa,
-        233, 0x01000001,
-        234, 0x00010300,
-        235, 0x00676700,
-        236, 0x00676700,
-        237, 0x00676700,
-        238, 0x00676700,
-        239, 0x00676700,
-        240, 0x00676700,
-        241, 0x00676700,
-        242, 0x00676700,
-        243, 0x00676700,
-        244, 0x00000000,
-        245, 0x01000000,
-        246, 0x00000001,
-        247, 0x00000101,
-        248, 0x00010100,
-        249, 0x03000000,
-        250, 0x03030303,
-        251, 0x00030303,
-        252, 0x02020064,
-        253, 0x02020202,
-        254, 0x00010202,
-        255, 0x01010064,
-        256, 0x01010101,
-        257, 0x00020101,
-        258, 0x00000064,
-        259, 0x00000000,
-        260, 0x000d0d00,
-        261, 0x00000000,
-        262, 0x00002058,
-        263, 0x02000200,
-        264, 0x02000200,
-        265, 0x00002058,
-        266, 0x0000a1b8,
-        267, 0x00000607,
-        268, 0x00002058,
-        269, 0x02000200,
-        270, 0x02000200,
-        271, 0x00002058,
-        272, 0x0000a1b8,
-        273, 0x02020607,
-        274, 0x000a0100,
-        275, 0x0000000a,
-        276, 0x00000000,
-        277, 0x00000000,
-        278, 0x00000f0a,
-        279, 0x00000000,
-        280, 0x00000000,
-        281, 0x00000000,
-        282, 0x00000000,
-        283, 0x00000000,
-        284, 0x00000103,
-        285, 0x00010003,
-        286, 0x00000003,
-        287, 0x00000000,
-        288, 0x00000000,
-        289, 0x00000000,
-        290, 0x07000000,
-        291, 0x00050705,
-        292, 0x00000000,
-        293, 0x00000000,
-        294, 0x00000000,
-        295, 0x00000000,
-        296, 0x00000000,
-        297, 0x00000000,
-        298, 0x00000000,
-        299, 0x00000000,
-        300, 0x00000000,
-        301, 0x00000000,
-        302, 0x00000000,
-        303, 0x00000000,
-        304, 0x00000000,
-        305, 0x00000000,
-        0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR667)
-const unsigned int ddr3_init_tab_1333[] = {
-        14, 0x01000000,
-        36, 0x0a140a0a,
-        37, 0x0100000a,
-        38, 0x14140101,
-        39, 0x000a0a03,
-        40, 0x00010100,
-        42, 0x00000000,
-        61, 0x00000400,
-        78, 0x00000000,
-        79, 0x00000000,
-        80, 0x00000000,
-        81, 0x00000000,
-        83, 0x00000000,
-        84, 0x00000a50,
-        87, 0x00000a50,
-        88, 0x00000046,
-        112, 0x00000000,
-        116, 0x00000000,
-        117, 0x00000000,
-        119, 0x00000000,
-        120, 0x00000000,
-        121, 0x00000000,
-        122, 0x00000000,
-        123, 0x00000000,
-        130, 0x00000000,
-        139, 0x00000000,
-        148, 0x00000000,
-        149, 0x00000000,
-        150, 0x00000000,
-        152, 0x00000000,
-        153, 0x00000000,
-        156, 0x00000000,
-        157, 0x01000200,
-        158, 0x02000040,
-        160, 0x00000200,
-        161, 0x00000040,
-        162, 0x00000000,
-        163, 0x01000000,
-        165, 0x0101ffff,
-        166, 0x01010101,
-        168, 0x00000103,
-        170, 0x00000001,
-        171, 0x00000000,
-        175, 0x00000000,
-        176, 0x00000000,
-        180, 0x00000000,
-        181, 0x00000000,
-        182, 0x00000000,
-        185, 0x00000000,
-        187, 0x00000000,
-        194, 0x00000000,
-        205, 0x00000000,
-        0, 0x00000600,
-        1, 0x00000000,
-        2, 0x00000000,
-        3, 0x00000000,
-        4, 0x00000000,
-        5, 0x00000000,
-        6, 0x00000000,
-        7, 0x00000700,
-        8, 0x00000000,
-        9, 0x00000000,
-        10, 0x00000000,
-        11, 0x00000007,
-        12, 0x00000000,
-        13, 0x00000000,
-        15, 0x000208d6,
-        16, 0x00051616,
-        17, 0x00000000,
-        18, 0x02000000,
-        19, 0x00071200,
-        20, 0x00000000,
-        21, 0x00071200,
-        22, 0x00000000,
-        23, 0x05040400,
-        24, 0x18210004,
-        25, 0x140a0505,
-        26, 0x21000405,
-        27, 0x0a050518,
-        28, 0x04050514,
-        29, 0x00b6d00c,
-        30, 0x050c0404,
-        31, 0x000c0405,
-        32, 0x0400b6d0,
-        33, 0x0a000c04,
-        34, 0x000a0a0a,
-        35, 0x010c0064,
-        41, 0x00000000,
-        43, 0x00ae0100,
-        44, 0x00001448,
-        45, 0x000000ae,
-        46, 0x00001448,
-        47, 0x00000005,
-        48, 0x00040004,
-        49, 0x00100010,
-        50, 0x00000000,
-        51, 0x00000000,
-        52, 0x02000000,
-        53, 0x020000b4,
-        54, 0x000000b4,
-        55, 0x07000001,
-        56, 0x00070707,
-        57, 0x00000000,
-        58, 0x00000000,
-        59, 0x00010000,
-        60, 0x10040010,
-        62, 0x00000200,
-        63, 0x00000000,
-        64, 0x00000001,
-        65, 0x00000000,
-        66, 0x00000000,
-        67, 0x00000000,
-        68, 0x00000000,
-        69, 0x00000000,
-        70, 0x00000000,
-        71, 0x00000000,
-        72, 0x00000000,
-        73, 0x00000000,
-        74, 0x00000000,
-        75, 0x00000000,
-        76, 0x00000000,
-        77, 0x00000000,
-        82, 0x00000000,
-        85, 0x00000046,
-        86, 0x00000010,
-        89, 0x00000010,
-        90, 0x00000000,
-        91, 0x00000000,
-        92, 0x00000000,
-        93, 0x00000000,
-        94, 0x00000000,
-        95, 0x00000000,
-        96, 0x00000000,
-        97, 0x00000000,
-        98, 0x00000a50,
-        99, 0x00000046,
-        100, 0x00000010,
-        101, 0x00000a50,
-        102, 0x00000046,
-        103, 0x00000010,
-        104, 0x00000000,
-        105, 0x00000000,
-        106, 0x00000000,
-        107, 0x00000000,
-        108, 0x00000000,
-        109, 0x00000000,
-        110, 0x00000000,
-        111, 0x00000000,
-        113, 0x00000000,
-        114, 0x00000000,
-        115, 0x00000000,
-        118, 0x00000000,
-        124, 0x00000000,
-        125, 0x00000000,
-        126, 0x00000000,
-        127, 0x00000000,
-        128, 0x00000000,
-        129, 0x00000000,
-        131, 0x00000000,
-        132, 0x00000000,
-        133, 0x00000000,
-        134, 0x00000000,
-        135, 0x00000000,
-        136, 0x00000000,
-        137, 0x00000000,
-        138, 0x00000000,
-        140, 0x01000000,
-        141, 0x00000001,
-        142, 0x00000000,
-        143, 0x00000000,
-        144, 0x00000000,
-        145, 0x00000000,
-        146, 0x00000000, //disable ECC
-        147, 0x00000000,
-        151, 0x00000000,
-        154, 0x00000000,
-        155, 0x00000000,
-        159, 0x00400100,
-        164, 0x0a020001,
-        167, 0x01010101,
-        169, 0x00000c03,
-        172, 0x01000000,
-        173, 0x00000100,
-        174, 0x00000000,
-        177, 0x00000000,
-        178, 0x00000000,
-        179, 0x00000000,
-        183, 0x00000000,
-        184, 0x00000000,
-        186, 0x00000000,
-        188, 0x00000000,
-        189, 0x00000000,
-        190, 0x00000000,
-        191, 0x00000000,
-        192, 0x00000000,
-        193, 0x00000000,
-        195, 0x00000000,
-        196, 0x01010200,
-        197, 0x00000002,
-        198, 0x06060600,
-        199, 0x00000106,
-        200, 0x02020000,
-        201, 0x02020002,
-        202, 0x02020101,
-        203, 0x02000102,
-        204, 0x00000000,
-        206, 0x00000000,
-        207, 0x00000000,
-        208, 0x00000000,
-        209, 0x0000280d,
-        210, 0x00010000,
-        211, 0x00010000,
-        212, 0x00000003,
-        213, 0x00000000,
-        214, 0x00000000,
-        215, 0x00000000,
-        216, 0x00000000,
-        217, 0x00000000,
-        218, 0x00000000,
-        219, 0x00000000,
-        220, 0x00000000,
-        221, 0x01000000,
-        222, 0x00000001,
-        223, 0x00000100,
-        224, 0x00030300,
-        225, 0x0556AA00,
-        226, 0x000aa955,
-        227, 0x000aa955,
-        228, 0x000556aa,
-        229, 0x000556aa,
-        230, 0x000aa955,
-        231, 0x000aa955,
-        232, 0x030556aa,
-        233, 0x01000001,
-        234, 0x00010300,
-        235, 0x00676700,
-        236, 0x00676700,
-        237, 0x00676700,
-        238, 0x00676700,
-        239, 0x00676700,
-        240, 0x00676700,
-        241, 0x00676700,
-        242, 0x00676700,
-        243, 0x00676700,
-        244, 0x00000000,
-        245, 0x01000000,
-        246, 0x00000001,
-        247, 0x00000101,
-        248, 0x00010100,
-        249, 0x03000000,
-        250, 0x03030303,
-        251, 0x00030303,
-        252, 0x02020064,
-        253, 0x02020202,
-        254, 0x00010202,
-        255, 0x01010064,
-        256, 0x01010101,
-        257, 0x00020101,
-        258, 0x00000064,
-        259, 0x00000000,
-        260, 0x000e0e00,
-        261, 0x00000000,
-        262, 0x00002890,
-        263, 0x02000200,
-        264, 0x02000200,
-        265, 0x00002890,
-        266, 0x0000cad0,
-        267, 0x00000708,
-        268, 0x00002890,
-        269, 0x02000200,
-        270, 0x02000200,
-        271, 0x00002890,
-        272, 0x0000cad0,
-        273, 0x02020708,
-        274, 0x000a0100,
-        275, 0x0000000a,
-        276, 0x00000000,
-        277, 0x00000000,
-        278, 0x00000f0a,
-        279, 0x00000000,
-        280, 0x00000000,
-        281, 0x00000000,
-        282, 0x00000000,
-        283, 0x00000000,
-        284, 0x00000103,
-        285, 0x00010003,
-        286, 0x00000003,
-        287, 0x00000000,
-        288, 0x00000000,
-        289, 0x00000000,
-        290, 0x08000000,
-        291, 0x00060806,
-        292, 0x00000000,
-        293, 0x00000000,
-        294, 0x00000000,
-        295, 0x00000000,
-        296, 0x00000000,
-        297, 0x00000000,
-        298, 0x00000000,
-        299, 0x00000000,
-        300, 0x00000000,
-        301, 0x00000000,
-        302, 0x00000000,
-        303, 0x00000000,
-        304, 0x00000000,
-        305, 0x00000000,
-        0xffffffff
-};
-#endif
-
-#if IS_ENABLED(CONFIG_CYGNUS_DDR800)
-const unsigned int ddr3_init_tab_1600[] = {
-        14, 0x01000000,
-        36, 0x0a140a0a,
-        37, 0x0100000a,
-        38, 0x17170101,
-        39, 0x000b0b03,
-        40, 0x00010100,
-        42, 0x00000000,
-        61, 0x00000400,
-        78, 0x00000000,
-        79, 0x00000000,
-        80, 0x00000000,
-        81, 0x00000000,
-        83, 0x00000000,
-        84, 0x00000c70,
-        87, 0x00000c70,
-        88, 0x00000046,
-        112, 0x00000000,
-        116, 0x00000000,
-        117, 0x00000000,
-        119, 0x00000000,
-        120, 0x00000000,
-        121, 0x00000000,
-        122, 0x00000000,
-        123, 0x00000000,
-        130, 0x00000000,
-        139, 0x00000000,
-        148, 0x00000000,
-        149, 0x00000000,
-        150, 0x00000000,
-        152, 0x00000000,
-        153, 0x00000000,
-        156, 0x00000000,
-        157, 0x01000200,
-        158, 0x02000040,
-        160, 0x00000200,
-        161, 0x00000040,
-        162, 0x00000000,
-        163, 0x01000000,
-        165, 0x0101ffff,
-        166, 0x01010101,
-        168, 0x00000103,
-        170, 0x00000001,
-        171, 0x00000000,
-        175, 0x00000000,
-        176, 0x00000000,
-        180, 0x00000000,
-        181, 0x00000000,
-        182, 0x00000000,
-        185, 0x00000000,
-        187, 0x00000000,
-        194, 0x00000000,
-        205, 0x00000000,
-        0, 0x00000600,
-        1, 0x00000000,
-        2, 0x00000000,
-        3, 0x00000000,
-        4, 0x00000000,
-        5, 0x00000000,
-        6, 0x00000000,
-        7, 0x00000800,
-        8, 0x00000000,
-        9, 0x00000000,
-        10, 0x00000000,
-        11, 0x00000008,
-        12, 0x00000000,
-        13, 0x00000000,
-        15, 0x00027100,
-        16, 0x00061a80,
-        17, 0x00000000,
-        18, 0x02000000,
-        19, 0x00081600,
-        20, 0x00000000,
-        21, 0x00081600,
-        22, 0x00000000,
-        23, 0x05040400,
-        24, 0x1c270005,
-        25, 0x180b0606,
-        26, 0x27000505,
-        27, 0x0b06061c,
-        28, 0x04060618,
-        29, 0x00db600c,
-        30, 0x060c0404,
-        31, 0x000c0406,
-        32, 0x0400db60,
-        33, 0x0b000c04,
-        34, 0x000c0b0c,
-        35, 0x010c0078,
-        41, 0x00000000,
-        43, 0x00d00100,
-        44, 0x00001858,
-        45, 0x000000d0,
-        46, 0x00001858,
-        47, 0x00000005,
-        48, 0x00050005,
-        49, 0x00140014,
-        50, 0x00000000,
-        51, 0x00000000,
-        52, 0x02000000,
-        53, 0x020000d8,
-        54, 0x000000d8,
-        55, 0x08000001,
-        56, 0x00080808,
-        57, 0x00000000,
-        58, 0x00000000,
-        59, 0x00010000,
-        60, 0x10040010,
-        62, 0x00000200,
-        63, 0x00000000,
-        64, 0x00000001,
-        65, 0x00000000,
-        66, 0x00000000,
-        67, 0x00000000,
-        68, 0x00000000,
-        69, 0x00000000,
-        70, 0x00000000,
-        71, 0x00000000,
-        72, 0x00000000,
-        73, 0x00000000,
-        74, 0x00000000,
-        75, 0x00000000,
-        76, 0x00000000,
-        77, 0x00000000,
-        82, 0x00000000,
-        85, 0x00000046,
-        86, 0x00000018,
-        89, 0x00000018,
-        90, 0x00000000,
-        91, 0x00000000,
-        92, 0x00000000,
-        93, 0x00000000,
-        94, 0x00000000,
-        95, 0x00000000,
-        96, 0x00000000,
-        97, 0x00000000,
-        98, 0x00000c70,
-        99, 0x00000046,
-        100, 0x00000018,
-        101, 0x00000c70,
-        102, 0x00000046,
-        103, 0x00000018,
-        104, 0x00000000,
-        105, 0x00000000,
-        106, 0x00000000,
-        107, 0x00000000,
-        108, 0x00000000,
-        109, 0x00000000,
-        110, 0x00000000,
-        111, 0x00000000,
-        113, 0x00000000,
-        114, 0x00000000,
-        115, 0x00000000,
-        118, 0x00000000,
-        124, 0x00000000,
-        125, 0x00000000,
-        126, 0x00000000,
-        127, 0x00000000,
-        128, 0x00000000,
-        129, 0x00000000,
-        131, 0x00000000,
-        132, 0x00000000,
-        133, 0x00000000,
-        134, 0x00000000,
-        135, 0x00000000,
-        136, 0x00000000,
-        137, 0x00000000,
-        138, 0x00000000,
-        140, 0x01000000,
-        141, 0x00000001,
-        142, 0x00000000,
-        143, 0x00000000,
-        144, 0x00000000,
-        145, 0x00000000,
-        146, 0x00000000, //disable ECC
-        147, 0x00000000,
-        151, 0x00000000,
-        154, 0x00000000,
-        155, 0x00000000,
-        159, 0x00400100,
-        164, 0x0a020001,
-        167, 0x01010101,
-        169, 0x00000c03,
-        172, 0x01000000,
-        173, 0x00000100,
-        174, 0x00000000,
-        177, 0x00000000,
-        178, 0x00000000,
-        179, 0x00000000,
-        183, 0x00000000,
-        184, 0x00000000,
-        186, 0x00000000,
-        188, 0x00000000,
-        189, 0x00000000,
-        190, 0x00000000,
-        191, 0x00000000,
-        192, 0x00000000,
-        193, 0x00000000,
-        195, 0x00000000,
-        196, 0x01010200,
-        197, 0x00000002,
-        198, 0x06070700,
-        199, 0x00000106,
-        200, 0x03030000,
-        201, 0x02020002,
-        202, 0x02020101,
-        203, 0x02000102,
-        204, 0x00000000,
-        206, 0x00000000,
-        207, 0x00000000,
-        208, 0x00000000,
-        209, 0x0000280d,
-        210, 0x00010000,
-        211, 0x00010000,
-        212, 0x00000003,
-        213, 0x00000000,
-        214, 0x00000000,
-        215, 0x00000000,
-        216, 0x00000000,
-        217, 0x00000000,
-        218, 0x00000000,
-        219, 0x00000000,
-        220, 0x00000000,
-        221, 0x01000000,
-        222, 0x00000001,
-        223, 0x00000100,
-        224, 0x00030300,
-        225, 0x0556AA00,
-        226, 0x000aa955,
-        227, 0x000aa955,
-        228, 0x000556aa,
-        229, 0x000556aa,
-        230, 0x000aa955,
-        231, 0x000aa955,
-        232, 0x030556aa,
-        233, 0x01000001,
-        234, 0x00010300,
-        235, 0x00676700,
-        236, 0x00676700,
-        237, 0x00676700,
-        238, 0x00676700,
-        239, 0x00676700,
-        240, 0x00676700,
-        241, 0x00676700,
-        242, 0x00676700,
-        243, 0x00676700,
-        244, 0x00000000,
-        245, 0x01000000,
-        246, 0x00000001,
-        247, 0x00000101,
-        248, 0x00010100,
-        249, 0x03000000,
-        250, 0x03030303,
-        251, 0x00030303,
-        252, 0x02020064,
-        253, 0x02020202,
-        254, 0x00010202,
-        255, 0x01010064,
-        256, 0x01010101,
-        257, 0x00020101,
-        258, 0x00000064,
-        259, 0x00000000,
-        260, 0x000e0e00,
-        261, 0x00000000,
-        262, 0x000030b0,
-        263, 0x02000200,
-        264, 0x02000200,
-        265, 0x000030b0,
-        266, 0x0000f370,
-        267, 0x0000080a,
-        268, 0x000030b0,
-        269, 0x02000200,
-        270, 0x02000200,
-        271, 0x000030b0,
-        272, 0x0000f370,
-        273, 0x0202080a,
-        274, 0x000a0100,
-        275, 0x0000000a,
-        276, 0x00000000,
-        277, 0x00000000,
-        278, 0x00000f0a,
-        279, 0x00000000,
-        280, 0x00000000,
-        281, 0x00000000,
-        282, 0x00000000,
-        283, 0x00000000,
-        284, 0x00000103,
-        285, 0x00010003,
-        286, 0x00000003,
-        287, 0x00000000,
-        288, 0x00000000,
-        289, 0x00000000,
-        290, 0x0a000000,
-        291, 0x00070a07,
-        292, 0x00000000,
-        293, 0x00000000,
-        294, 0x00000000,
-        295, 0x00000000,
-        296, 0x00000000,
-        297, 0x00000000,
-        298, 0x00000000,
-        299, 0x00000000,
-        300, 0x00000000,
-        301, 0x00000000,
-        302, 0x00000000,
-        303, 0x00000000,
-        304, 0x00000000,
-        305, 0x00000000,
-        0xffffffff
-};
-#endif
-
-#ifdef DDR2_SUPPORT
-const unsigned int ddr2_mode_reg_tab[] = {
-		0x0320,
-		0x0046,
-		0x0000,
-		0x0000
-};
-#endif
diff --git a/src/soc/broadcom/cygnus/gpio.c b/src/soc/broadcom/cygnus/gpio.c
deleted file mode 100644
index 9c4ef24..0000000
--- a/src/soc/broadcom/cygnus/gpio.c
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#include <arch/io.h>
-#include <console/console.h>
-#include <gpio.h>
-#include <stdlib.h>
-#include <delay.h>
-
-#define dev_dbg(chip, fmt, args...) printk(BIOS_DEBUG, "[%s] " fmt, \
-	chip->label, args)
-
-#define CYGNUS_GPIO_DATA_IN_OFFSET   0x00
-#define CYGNUS_GPIO_DATA_OUT_OFFSET  0x04
-#define CYGNUS_GPIO_OUT_EN_OFFSET    0x08
-#define CYGNUS_GPIO_IN_TYPE_OFFSET   0x0c
-#define CYGNUS_GPIO_INT_DE_OFFSET    0x10
-#define CYGNUS_GPIO_INT_EDGE_OFFSET  0x14
-#define CYGNUS_GPIO_INT_MSK_OFFSET   0x18
-#define CYGNUS_GPIO_INT_STAT_OFFSET  0x1c
-#define CYGNUS_GPIO_INT_MSTAT_OFFSET 0x20
-#define CYGNUS_GPIO_INT_CLR_OFFSET   0x24
-#define CYGNUS_GPIO_PAD_RES_OFFSET   0x34
-#define CYGNUS_GPIO_RES_EN_OFFSET    0x38
-
-/* drive strength control for ASIU GPIO */
-#define CYGNUS_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
-
-/* drive strength control for CCM/CRMU (AON) GPIO */
-#define CYGNUS_GPIO_DRV0_CTRL_OFFSET  0x00
-
-#define GPIO_BANK_SIZE 0x200
-#define NGPIOS_PER_BANK 32
-#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
-
-#define CYGNUS_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
-#define CYGNUS_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
-
-#define GPIO_DRV_STRENGTH_BIT_SHIFT  20
-#define GPIO_DRV_STRENGTH_BITS       3
-#define GPIO_DRV_STRENGTH_BIT_MASK   ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
-
-/*
- * Cygnus GPIO core
- *
- * @base: I/O register base for Cygnus GPIO controller
- * @io_ctrl: I/O register base for certain type of Cygnus GPIO controller that
- * has the PINCONF support implemented outside of the GPIO block
- * @num_banks: number of GPIO banks, each bank supports up to 32 GPIOs
- * @pinmux_is_supported: flag to indicate this GPIO controller contains pins
- * that can be individually muxed to GPIO
- * @pctl_priv: pointer to pinctrl handle
- */
-struct cygnus_gpio {
-	void		*base;
-	void		*io_ctrl;
-	const char	*label;
-	int			gpio_base;
-	u16			ngpio;
-	unsigned	num_banks;
-	int			pinmux_is_supported;
-	void		*pctl_priv;
-};
-
-/*
- * GPIO cores table
- *
- * Cygnus has 3 gpio cores. The tables contains descriptors of those cores.
- */
-struct cygnus_gpio cygnus_gpio_table[] = {
-	{
-		.base = (void *)0x03024800,
-		.io_ctrl = (void *)0x03024008,
-		.label = "gpio_crmu",
-		.gpio_base = 170,
-		.ngpio = 6,
-	},
-	{
-		.base = (void *)0x1800a000,
-		.io_ctrl = (void *)0x0301d164,
-		.label = "gpio_ccm",
-		.gpio_base = 0,
-		.ngpio = 24,
-	},
-	{
-		.base = (void *)0x180a5000,
-		.label = "gpio_asiu",
-		.gpio_base = 24,
-		.ngpio = 146,
-		.pinmux_is_supported = 1
-	}
-};
-
-/*
- * Map a GPIO in the local gpio_chip pin space to a pin in the Cygnus IOMUX
- * pinctrl pin space
- */
-struct cygnus_gpio_pin_range {
-	unsigned offset;
-	unsigned pin_base;
-	unsigned num_pins;
-};
-
-#define CYGNUS_PINRANGE(o, p, n) { .offset = o, .pin_base = p, .num_pins = n }
-
-/*
- * Pin mapping table for mapping local GPIO pins to Cygnus IOMUX pinctrl pins.
- * This is for ASIU gpio. The offset is based on ASIU gpios.
- */
-static const struct cygnus_gpio_pin_range cygnus_gpio_pintable[] = {
-	CYGNUS_PINRANGE(0, 42, 1),
-	CYGNUS_PINRANGE(1, 44, 3),
-	CYGNUS_PINRANGE(4, 48, 1),
-	CYGNUS_PINRANGE(5, 50, 3),
-	CYGNUS_PINRANGE(8, 126, 1),
-	CYGNUS_PINRANGE(9, 155, 1),
-	CYGNUS_PINRANGE(10, 152, 1),
-	CYGNUS_PINRANGE(11, 154, 1),
-	CYGNUS_PINRANGE(12, 153, 1),
-	CYGNUS_PINRANGE(13, 127, 3),
-	CYGNUS_PINRANGE(16, 140, 1),
-	CYGNUS_PINRANGE(17, 145, 7),
-	CYGNUS_PINRANGE(24, 130, 10),
-	CYGNUS_PINRANGE(34, 141, 4),
-	CYGNUS_PINRANGE(38, 54, 1),
-	CYGNUS_PINRANGE(39, 56, 3),
-	CYGNUS_PINRANGE(42, 60, 3),
-	CYGNUS_PINRANGE(45, 64, 3),
-	CYGNUS_PINRANGE(48, 68, 2),
-	CYGNUS_PINRANGE(50, 84, 6),
-	CYGNUS_PINRANGE(56, 94, 6),
-	CYGNUS_PINRANGE(62, 72, 1),
-	CYGNUS_PINRANGE(63, 70, 1),
-	CYGNUS_PINRANGE(64, 80, 1),
-	CYGNUS_PINRANGE(65, 74, 3),
-	CYGNUS_PINRANGE(68, 78, 1),
-	CYGNUS_PINRANGE(69, 82, 1),
-	CYGNUS_PINRANGE(70, 156, 17),
-	CYGNUS_PINRANGE(87, 104, 12),
-	CYGNUS_PINRANGE(99, 102, 2),
-	CYGNUS_PINRANGE(101, 90, 4),
-	CYGNUS_PINRANGE(105, 116, 10),
-	CYGNUS_PINRANGE(123, 11, 1),
-	CYGNUS_PINRANGE(124, 38, 4),
-	CYGNUS_PINRANGE(128, 43, 1),
-	CYGNUS_PINRANGE(129, 47, 1),
-	CYGNUS_PINRANGE(130, 49, 1),
-	CYGNUS_PINRANGE(131, 53, 1),
-	CYGNUS_PINRANGE(132, 55, 1),
-	CYGNUS_PINRANGE(133, 59, 1),
-	CYGNUS_PINRANGE(134, 63, 1),
-	CYGNUS_PINRANGE(135, 67, 1),
-	CYGNUS_PINRANGE(136, 71, 1),
-	CYGNUS_PINRANGE(137, 73, 1),
-	CYGNUS_PINRANGE(138, 77, 1),
-	CYGNUS_PINRANGE(139, 79, 1),
-	CYGNUS_PINRANGE(140, 81, 1),
-	CYGNUS_PINRANGE(141, 83, 1),
-	CYGNUS_PINRANGE(142, 10, 1)
-};
-
-static unsigned cygnus_gpio_to_pin(unsigned gpio)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(cygnus_gpio_pintable); i++) {
-		const struct cygnus_gpio_pin_range *range = cygnus_gpio_pintable
-			+ i;
-
-		if ((gpio < range->offset) ||
-			(gpio >= (range->offset + range->num_pins)))
-			continue;
-
-		return range->pin_base + (gpio - range->offset);
-	}
-	return -1;
-}
-
-static struct cygnus_gpio *cygnus_get_gpio_core(unsigned gpio,
-	unsigned *gpio_offset)
-{
-	int i;
-
-	for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
-		struct cygnus_gpio *chip = cygnus_gpio_table + i;
-
-		if ((gpio < chip->gpio_base) ||
-			(gpio >= (chip->gpio_base + chip->ngpio)))
-			continue;
-
-		*gpio_offset = gpio - chip->gpio_base;
-		return chip;
-	}
-
-	return NULL;
-}
-
-static u32 cygnus_readl(struct cygnus_gpio *chip, unsigned int offset)
-{
-	return read32(chip->base + offset);
-}
-
-static void cygnus_writel(struct cygnus_gpio *chip, unsigned int offset,
-			  u32 val)
-{
-	write32(chip->base + offset, val);
-}
-
-/**
- *  cygnus_set_bit - set or clear one bit (corresponding to the GPIO pin) in a
- *  Cygnus GPIO register
- *
- *  @cygnus_gpio: Cygnus GPIO device
- *  @reg: register offset
- *  @gpio: GPIO pin
- *  @set: set or clear. 1 - set; 0 -clear
- */
-static void cygnus_set_bit(struct cygnus_gpio *chip, unsigned int reg,
-			   unsigned gpio, int set)
-{
-	unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
-	unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
-	u32 val;
-
-	val = cygnus_readl(chip, offset);
-	if (set)
-		val |= BIT(shift);
-	else
-		val &= ~BIT(shift);
-	cygnus_writel(chip, offset, val);
-}
-
-static int cygnus_get_bit(struct cygnus_gpio *chip, unsigned int reg,
-			  unsigned gpio)
-{
-	unsigned int offset = CYGNUS_GPIO_REG(gpio, reg);
-	unsigned int shift = CYGNUS_GPIO_SHIFT(gpio);
-	u32 val;
-
-	val = cygnus_readl(chip, offset) & BIT(shift);
-	if (val)
-		return 1;
-	else
-		return 0;
-}
-
-/*
- * Request the Cygnus IOMUX pinmux controller to mux individual pins to GPIO
- */
-static int cygnus_gpio_request(struct cygnus_gpio *chip, unsigned offset)
-{
-	/* not all Cygnus GPIO pins can be muxed individually */
-	if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
-		return 0;
-
-	return cygnus_gpio_request_enable(chip->pctl_priv,
-		cygnus_gpio_to_pin(offset));
-}
-
-static void cygnus_gpio_free(struct cygnus_gpio *chip, unsigned offset)
-{
-	if (!chip->pinmux_is_supported || (chip->pctl_priv == NULL))
-		return;
-
-	cygnus_gpio_disable_free(chip->pctl_priv, cygnus_gpio_to_pin(offset));
-}
-
-static int cygnus_gpio_direction_input(struct cygnus_gpio *chip, unsigned gpio)
-{
-	cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 0);
-
-	dev_dbg(chip, "gpio:%u set input\n", gpio);
-
-	return 0;
-}
-
-static int cygnus_gpio_direction_output(struct cygnus_gpio *chip, unsigned gpio,
-					int value)
-{
-	cygnus_set_bit(chip, CYGNUS_GPIO_OUT_EN_OFFSET, gpio, 1);
-	cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
-
-	dev_dbg(chip, "gpio:%u set output, value:%d\n", gpio, value);
-
-	return 0;
-}
-
-static void cygnus_gpio_set(struct cygnus_gpio *chip, unsigned gpio, int value)
-{
-	cygnus_set_bit(chip, CYGNUS_GPIO_DATA_OUT_OFFSET, gpio, value);
-
-	dev_dbg(chip, "gpio:%u set, value:%d\n", gpio, value);
-}
-
-static int cygnus_gpio_get(struct cygnus_gpio *chip, unsigned gpio)
-{
-	return cygnus_get_bit(chip, CYGNUS_GPIO_DATA_IN_OFFSET, gpio);
-}
-
-static int cygnus_gpio_set_pull(struct cygnus_gpio *chip, unsigned gpio,
-				int disable, int pull_up)
-{
-	if (disable) {
-		cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 0);
-	} else {
-		cygnus_set_bit(chip, CYGNUS_GPIO_PAD_RES_OFFSET, gpio, pull_up);
-		cygnus_set_bit(chip, CYGNUS_GPIO_RES_EN_OFFSET, gpio, 1);
-	}
-
-	dev_dbg(chip, "gpio:%u set pullup:%d\n", gpio, pull_up);
-
-	return 0;
-}
-
-#define CYGNUS_GPIO_TEST_AON_GPIO0	170
-#define CYGNUS_GPIO_TEST_SPI2_MISO	69
-#define CYGNUS_GPIO_TEST_DELAY_S	3
-
-static void cygnus_gpio_test(void)
-{
-	gpio_t gpio_in;
-	gpio_t gpio_out;
-	unsigned val;
-
-	printk(BIOS_INFO, "Start gpio test...\n");
-
-	gpio_in = CYGNUS_GPIO_TEST_AON_GPIO0;  /* AON_GPIO0 */
-	gpio_input(gpio_in);
-	gpio_input_pulldown(gpio_in);
-	printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
-
-	gpio_in = CYGNUS_GPIO_TEST_SPI2_MISO;  /* SPI2_MISO */
-	gpio_input(gpio_in);
-	gpio_input_pullup(gpio_in);
-	printk(BIOS_INFO, "GPIO get %d=%d\n", gpio_in, gpio_get(gpio_in));
-	val = 0;
-	gpio_out = CYGNUS_GPIO_TEST_SPI2_MISO;
-
-	gpio_output(gpio_out, val);
-	printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
-	delay(CYGNUS_GPIO_TEST_DELAY_S);
-
-	val = 1;
-	gpio_set(gpio_out, val);
-	printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
-	delay(CYGNUS_GPIO_TEST_DELAY_S);
-
-	val = 0;
-	gpio_set(gpio_out, val);
-	printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
-	delay(CYGNUS_GPIO_TEST_DELAY_S);
-
-	val = 1;
-	gpio_set(gpio_out, val);
-	printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
-	delay(CYGNUS_GPIO_TEST_DELAY_S);
-
-	val = 0;
-	gpio_set(gpio_out, val);
-	printk(BIOS_INFO, "GPIO set %d=%d\n", gpio_out, val);
-	delay(CYGNUS_GPIO_TEST_DELAY_S);
-
-	gpio_free(CYGNUS_GPIO_TEST_AON_GPIO0);
-	gpio_free(CYGNUS_GPIO_TEST_SPI2_MISO);
-	printk(BIOS_INFO, "Gpio test completed...\n");
-}
-
-void gpio_init(void)
-{
-	int i;
-
-	printk(BIOS_INFO, "Setting up the gpio...\n");
-
-	for (i = 0; i < ARRAY_SIZE(cygnus_gpio_table); i++) {
-		struct cygnus_gpio *chip = cygnus_gpio_table + i;
-
-		chip->num_banks = (chip->ngpio+NGPIOS_PER_BANK - 1)
-			/ NGPIOS_PER_BANK;
-		if (chip->pinmux_is_supported)
-			chip->pctl_priv = cygnus_pinmux_init();
-	}
-
-	if (IS_ENABLED(CONFIG_CYGNUS_GPIO_TEST))
-		cygnus_gpio_test();
-}
-
-void gpio_free(gpio_t gpio)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	cygnus_gpio_free(chip, gpio_num);
-}
-
-void gpio_input(gpio_t gpio)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	if (cygnus_gpio_request(chip, gpio_num) != 0) {
-		printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
-		return;
-	}
-	cygnus_gpio_direction_input(chip, gpio_num);
-}
-
-void gpio_input_pulldown(gpio_t gpio)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	cygnus_gpio_set_pull(chip, gpio_num, 0, 0);
-}
-
-void gpio_input_pullup(gpio_t gpio)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	cygnus_gpio_set_pull(chip, gpio_num, 0, 1);
-}
-
-int gpio_get(gpio_t gpio)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return -1;
-	}
-
-	return cygnus_gpio_get(chip, gpio_num);
-}
-
-void gpio_set(gpio_t gpio, int value)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	cygnus_gpio_set(chip, gpio_num, value);
-}
-
-void gpio_output(gpio_t gpio, int value)
-{
-	struct cygnus_gpio *chip;
-	unsigned gpio_num;
-
-	chip = cygnus_get_gpio_core(gpio, &gpio_num);
-	if (chip == NULL) {
-		dev_dbg(chip, "unable to find chip for gpio %d", gpio);
-		return;
-	}
-
-	if (cygnus_gpio_request(chip, gpio_num) != 0) {
-		printk(BIOS_ERR, "Cannot mux GPIO %d\n", gpio);
-		return;
-	}
-	cygnus_gpio_direction_output(chip, gpio_num, value);
-}
diff --git a/src/soc/broadcom/cygnus/hw_init.c b/src/soc/broadcom/cygnus/hw_init.c
deleted file mode 100644
index ce5592f..0000000
--- a/src/soc/broadcom/cygnus/hw_init.c
+++ /dev/null
@@ -1,759 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <delay.h>
-#include <console/console.h>
-#include <soc/tz.h>
-#include <soc/hw_init.h>
-
-/*****************************************************************************
- * TrustZone
- *****************************************************************************/
-#define IHOST_SCU_SECURE_ACCESS			0x19020054
-
-#define SMAU_NIC_IDM_TZ_BASE			0x180150a0
-#define SMAU_DDR_TZ_BASE			0x18015200
-#define SMAU_FLASH0_TZ_BASE			0x18015300
-#define SMAU_FLASH1_TZ_BASE			0x18015308
-#define SMAU_FLASH2_TZ_BASE			0x18015310
-#define SMAU_FLASH3_TZ_BASE			0x18015318
-#define SMAU_TZ_BASE_ENABLE			0x00000001
-
-#define CRMU_IPROC_ADDR_RANGE0_LOW		0x03024c30
-#define CRMU_IPROC_ADDR_RANGE0_HIGH		0x03024c34
-#define CRMU_ADDR_MASK				0xffffff00
-#define CRMU_ADDR_VALID				0x00000001
-#define CRMU_ADDR_START				0x03010000
-#define CRMU_ADDR_END				0x03100000
-
-static void scu_ns_config(void)
-{
-	/*
-	 * Enable NS SCU access to ARM global timer, private timer, and
-	 * components
-	 */
-	write32((void *)IHOST_SCU_SECURE_ACCESS, 0xFFF);
-}
-
-static void smau_ns_config(void)
-{
-	unsigned int val;
-
-	/* Disable SMAU NIC IDM TZ */
-	val = read32((void *)SMAU_NIC_IDM_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_NIC_IDM_TZ_BASE, val);
-
-	/*
-	 * Disable DDR TZ base
-	 *
-	 * This means the entire DDR is marked as NONSECURE (NS)
-	 *
-	 * NOTE: In the future, multiple regions of DDR may need to be marked
-	 * as SECURE for secure OS and other TZ usages
-	 */
-	val = read32((void *)SMAU_DDR_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_DDR_TZ_BASE, val);
-
-
-	/*
-	 * Disable flash TZ support
-	 *
-	 * The entire flash is currently marked as NS
-	 *
-	 * NOTE: In the future, multiple regions of flash may need to be marked
-	 * as SECURE for secure OS and other TZ firmware/data storage
-	 */
-
-	/* Flash 0: ROM */
-	val = read32((void *)SMAU_FLASH0_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_FLASH0_TZ_BASE, val);
-
-	/* Flash 1: QSPI */
-	val = read32((void *)SMAU_FLASH1_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_FLASH1_TZ_BASE, val);
-
-	/* Flash 2: NAND */
-	val = read32((void *)SMAU_FLASH2_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_FLASH2_TZ_BASE, val);
-
-	/* Flash 3: PNOR */
-	val = read32((void *)SMAU_FLASH3_TZ_BASE);
-	val &= ~SMAU_TZ_BASE_ENABLE;
-	write32((void *)SMAU_FLASH3_TZ_BASE, val);
-}
-
-static void crmu_ns_config(void)
-{
-
-	/*
-	 * Currently opens up the entire CRMU to allow iPROC NS access
-	 *
-	 * NOTE: In the future, we might want to protect particular CRMU
-	 * sub-blocks to allow SECURE access only. That can be done by
-	 * programming the CRMU IPROC address range registers. Up to 4 access
-	 * windows can be created
-	 */
-	write32((void *)CRMU_IPROC_ADDR_RANGE0_LOW,
-		(CRMU_ADDR_START & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
-	write32((void *)CRMU_IPROC_ADDR_RANGE0_HIGH,
-		(CRMU_ADDR_END & CRMU_ADDR_MASK) | CRMU_ADDR_VALID);
-}
-
-static void tz_init(void)
-{
-	/* Configure the Cygnus for non-secure access */
-	/* ARM Cortex A9 SCU NS access configuration */
-	scu_ns_config();
-
-	/* SMAU NS related configurations */
-	smau_ns_config();
-
-	/* CRMU NS related configurations */
-	crmu_ns_config();
-
-	/*
-	 * Configure multiple masters and slaves to run in NS
-	 */
-	tz_set_non_virtual_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-	tz_set_periph_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-	tz_set_masters_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-	tz_set_wrapper_security(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
-				TZ_STATE_NON_SECURE);
-	tz_set_cfg_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-
-	tz_set_ext_slaves_security(0xFFFFFFFF, TZ_STATE_NON_SECURE);
-
-	/* configure sec peripherals to be accessed from non-secure world */
-	tz_set_sec_periphs_security(0xFFFFFFFF &
-				    ~(CYGNUS_sec_periph_APBz_sotp |
-				      CYGNUS_sec_periph_APBz_tzpc),
-				    TZ_STATE_NON_SECURE);
-
-	/* default sram to non-secure */
-	tz_set_sram_sec_region(0);
-}
-
-/*****************************************************************************
- * DMAC
- *****************************************************************************/
-#define DMAC_M0_IDM_RESET_CONTROL	0x1810f800
-#define DMAC_RESET_MASK			0x00000001
-#define DMAC_RESET_TIMEOUT		1000
-
-static void dmac_init(void)
-{
-	unsigned int val, timeout;
-
-	/* bring the DMAC block out of reset */
-	val = read32((void *)DMAC_M0_IDM_RESET_CONTROL);
-	val |= DMAC_RESET_MASK;
-	write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
-	udelay(10);
-	val &= ~DMAC_RESET_MASK;
-	write32((void *)DMAC_M0_IDM_RESET_CONTROL, val);
-
-	timeout = 0;
-	while (read32((void *)DMAC_M0_IDM_RESET_CONTROL) & DMAC_RESET_MASK) {
-		udelay(1);
-		if (timeout++ > DMAC_RESET_TIMEOUT)
-			die("Failed to bring PL330 DMAC out of reset\n");
-	}
-}
-
-/*****************************************************************************
- * Neon
- *****************************************************************************/
-#define CRU_CONTROL				0x1800e000
-#define CRU_CONTROL_NEON_RESET_N		0x00000040
-
-#define CRU_IHOST_PWRDWN_EN			0x1800e004
-#define CRU_IHOST_PWRDWN_EN_CLAMPON_NEON	0x00100000
-#define CRU_IHOST_PWRDWN_EN_PWRON_NEON		0x00200000
-#define CRU_IHOST_PWRDWN_EN_PWROK_NEON		0x00400000
-
-#define CRU_IHOST_PWRDWN_STATUS			0x1800e008
-#define CRU_IHOST_PWRDWN_STATUS_PWRON_NEON	0x00200000
-#define CRU_IHOST_PWRDWN_STATUS_PWROK_NEON	0x00400000
-
-#define CRU_STATUS_DELAY_US			1
-#define CRU_MAX_RETRY_COUNT			10
-#define CRU_RETRY_INTVL_US			1
-
-static void neon_init(void)
-{
-	unsigned int i, val;
-
-	/* put Neon into reset */
-	val = read32((void *)CRU_CONTROL);
-	val &= ~CRU_CONTROL_NEON_RESET_N;
-	write32((void *)CRU_CONTROL, val);
-
-	/* assert the power on register bit */
-	val = read32((void *)CRU_IHOST_PWRDWN_EN);
-	val |= CRU_IHOST_PWRDWN_EN_PWRON_NEON;
-	write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
-	/* wait for power on */
-	i = 0;
-	while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
-		 CRU_IHOST_PWRDWN_STATUS_PWRON_NEON)) {
-		udelay(CRU_RETRY_INTVL_US);
-		if (i++ >= CRU_MAX_RETRY_COUNT)
-			die("Failed to ack NEON power on\n");
-	}
-
-	udelay(CRU_STATUS_DELAY_US);
-
-	/* assert the power ok register bit */
-	val = read32((void *)CRU_IHOST_PWRDWN_EN);
-	val |= CRU_IHOST_PWRDWN_EN_PWROK_NEON;
-	write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
-	/* wait for power ok */
-	i = 0;
-	while (!(read32((void *)CRU_IHOST_PWRDWN_STATUS) &
-		 CRU_IHOST_PWRDWN_STATUS_PWROK_NEON)) {
-		udelay(CRU_RETRY_INTVL_US);
-		if (i++ >= CRU_MAX_RETRY_COUNT)
-			die("Failed to ack NEON power ok\n");
-	}
-
-	udelay(CRU_STATUS_DELAY_US);
-
-	/* clamp off for the NEON block */
-	val = read32((void *)CRU_IHOST_PWRDWN_EN);
-	val &= ~CRU_IHOST_PWRDWN_EN_CLAMPON_NEON;
-	write32((void *)CRU_IHOST_PWRDWN_EN, val);
-
-	udelay(CRU_STATUS_DELAY_US);
-
-	/* bring NEON out of reset */
-	val = read32((void *)CRU_CONTROL);
-	val |= CRU_CONTROL_NEON_RESET_N;
-	write32((void *)CRU_CONTROL, val);
-}
-
-/*****************************************************************************
- * PCIe
- *****************************************************************************/
-#define CRMU_PCIE_CFG			0x0301d0a0
-#define PCIE0_LNK_PHY_IDDQ		0x00000004
-#define PCIE1_LNK_PHY_IDDQ		0x00000400
-
-static void pcie_init(void)
-{
-	unsigned int val;
-
-	/*
-	 * Force all AFEs of both PCIe0 and PCIe1 to be powered down, including
-	 * pad biasing
-	 *
-	 * This brings down the PCIe interfaces to the lowest possible power
-	 * mode
-	 */
-	val = read32((void *)CRMU_PCIE_CFG);
-	val |= PCIE1_LNK_PHY_IDDQ | PCIE0_LNK_PHY_IDDQ;
-	write32((void *)CRMU_PCIE_CFG, val);
-}
-
-/*****************************************************************************
- * M0
- *****************************************************************************/
-#define CRMU_MCU_ACCESS_CONTROL			0x03024c00
-#define CRMU_MCU_ACCESS_MODE_SECURE		0x2
-
-static void M0_init(void)
-{
-	/* Set M0 as a secure master */
-	write32((void *)CRMU_MCU_ACCESS_CONTROL, CRMU_MCU_ACCESS_MODE_SECURE);
-}
-
-/*****************************************************************************
- * CCU
- *****************************************************************************/
-#define IHOST_PROC_CLK_WR_ACCESS		0x19000000
-#define IHOST_PROC_CLK_POLICY_FREQ		0x19000008
-#define IHOST_PROC_CLK_POLICY_CTL		0x1900000c
-#define IHOST_PROC_CLK_POLICY0_MASK		0x19000010
-#define IHOST_PROC_CLK_POLICY1_MASK		0x19000014
-#define IHOST_PROC_CLK_POLICY2_MASK		0x19000018
-#define IHOST_PROC_CLK_POLICY3_MASK		0x1900001c
-#define IHOST_PROC_CLK_INTEN			0x19000020
-#define IHOST_PROC_CLK_INTSTAT			0x19000024
-#define IHOST_PROC_CLK_LVM_EN			0x19000034
-#define IHOST_PROC_CLK_LVM0_3			0x19000038
-#define IHOST_PROC_CLK_LVM4_7			0x1900003c
-#define IHOST_PROC_CLK_VLT0_3			0x19000040
-#define IHOST_PROC_CLK_VLT4_7			0x19000044
-#define IHOST_PROC_CLK_BUS_QUIESC		0x19000100
-#define IHOST_PROC_CLK_CORE0_CLKGATE		0x19000200
-#define IHOST_PROC_CLK_CORE1_CLKGATE		0x19000204
-#define IHOST_PROC_CLK_ARM_SWITCH_CLKGATE	0x19000210
-#define IHOST_PROC_CLK_ARM_PERIPH_CLKGATE	0x19000300
-#define IHOST_PROC_CLK_APB0_CLKGATE		0x19000400
-#define IHOST_PROC_CLK_PL310_DIV		0x19000a00
-#define IHOST_PROC_CLK_PL310_TRIGGER		0x19000a04
-#define IHOST_PROC_CLK_ARM_SWITCH_DIV		0x19000a08
-#define IHOST_PROC_CLK_ARM_SWITCH_TRIGGER	0x19000a0c
-#define IHOST_PROC_CLK_APB_DIV			0x19000a10
-#define IHOST_PROC_CLK_APB_DIV_TRIGGER		0x19000a14
-#define IHOST_PROC_CLK_PLLARMA			0x19000c00
-#define IHOST_PROC_CLK_PLLARMB			0x19000c04
-#define IHOST_PROC_CLK_PLLARMC			0x19000c08
-#define IHOST_PROC_CLK_PLLARMCTRL0		0x19000c0c
-#define IHOST_PROC_CLK_PLLARMCTRL1		0x19000c10
-#define IHOST_PROC_CLK_PLLARMCTRL2		0x19000c14
-#define IHOST_PROC_CLK_PLLARMCTRL3		0x19000c18
-#define IHOST_PROC_CLK_PLLARMCTRL4		0x19000c1c
-#define IHOST_PROC_CLK_PLLARMCTRL5		0x19000c20
-#define IHOST_PROC_CLK_PLLARM_OFFSET		0x19000c24
-#define IHOST_PROC_CLK_ARM_DIV			0x19000e00
-#define IHOST_PROC_CLK_ARM_SEG_TRG		0x19000e04
-#define IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE	0x19000e08
-#define IHOST_PROC_CLK_PLL_DEBUG		0x19000e10
-#define IHOST_PROC_CLK_ACTIVITY_MON1		0x19000e20
-#define IHOST_PROC_CLK_ACTIVITY_MON2		0x19000e24
-#define IHOST_PROC_CLK_CLKGATE_DBG		0x19000e40
-#define IHOST_PROC_CLK_APB_CLKGATE_DBG1		0x19000e48
-#define IHOST_PROC_CLK_CLKMON			0x19000e64
-#define IHOST_PROC_CLK_POLICY_DBG		0x19000ec0
-#define IHOST_PROC_CLK_TGTMASK_DBG1		0x19000ec4
-#define IHOST_PROC_RST_WR_ACCESS		0x19000f00
-#define IHOST_PROC_RST_SOFT_RSTN		0x19000f04
-#define IHOST_PROC_RST_A9_CORE_SOFT_RSTN	0x19000f08
-
-#define WR_ACCESS_PRIVATE_ACCESS_MODE		0x80000000
-
-static uint32_t ccu_reg[] = {
-	IHOST_PROC_CLK_WR_ACCESS,
-	IHOST_PROC_CLK_POLICY_FREQ,
-	IHOST_PROC_CLK_POLICY_CTL,
-	IHOST_PROC_CLK_POLICY0_MASK,
-	IHOST_PROC_CLK_POLICY1_MASK,
-	IHOST_PROC_CLK_POLICY2_MASK,
-	IHOST_PROC_CLK_POLICY3_MASK,
-	IHOST_PROC_CLK_INTEN,
-	IHOST_PROC_CLK_INTSTAT,
-	IHOST_PROC_CLK_LVM_EN,
-	IHOST_PROC_CLK_LVM0_3,
-	IHOST_PROC_CLK_LVM4_7,
-	IHOST_PROC_CLK_VLT0_3,
-	IHOST_PROC_CLK_VLT4_7,
-	IHOST_PROC_CLK_BUS_QUIESC,
-	IHOST_PROC_CLK_CORE0_CLKGATE,
-	IHOST_PROC_CLK_CORE1_CLKGATE,
-	IHOST_PROC_CLK_ARM_SWITCH_CLKGATE,
-	IHOST_PROC_CLK_ARM_PERIPH_CLKGATE,
-	IHOST_PROC_CLK_APB0_CLKGATE,
-	IHOST_PROC_CLK_PL310_DIV,
-	IHOST_PROC_CLK_PL310_TRIGGER,
-	IHOST_PROC_CLK_ARM_SWITCH_DIV,
-	IHOST_PROC_CLK_ARM_SWITCH_TRIGGER,
-	IHOST_PROC_CLK_APB_DIV,
-	IHOST_PROC_CLK_APB_DIV_TRIGGER,
-	IHOST_PROC_CLK_PLLARMA,
-	IHOST_PROC_CLK_PLLARMB,
-	IHOST_PROC_CLK_PLLARMC,
-	IHOST_PROC_CLK_PLLARMCTRL0,
-	IHOST_PROC_CLK_PLLARMCTRL1,
-	IHOST_PROC_CLK_PLLARMCTRL2,
-	IHOST_PROC_CLK_PLLARMCTRL3,
-	IHOST_PROC_CLK_PLLARMCTRL4,
-	IHOST_PROC_CLK_PLLARMCTRL5,
-	IHOST_PROC_CLK_PLLARM_OFFSET,
-	IHOST_PROC_CLK_ARM_DIV,
-	IHOST_PROC_CLK_ARM_SEG_TRG,
-	IHOST_PROC_CLK_ARM_SEG_TRG_OVERRIDE,
-	IHOST_PROC_CLK_PLL_DEBUG,
-	IHOST_PROC_CLK_ACTIVITY_MON1,
-	IHOST_PROC_CLK_ACTIVITY_MON2,
-	IHOST_PROC_CLK_CLKGATE_DBG,
-	IHOST_PROC_CLK_APB_CLKGATE_DBG1,
-	IHOST_PROC_CLK_CLKMON,
-	IHOST_PROC_CLK_POLICY_DBG,
-	IHOST_PROC_CLK_TGTMASK_DBG1,
-	IHOST_PROC_RST_WR_ACCESS,
-	IHOST_PROC_RST_SOFT_RSTN,
-	IHOST_PROC_RST_A9_CORE_SOFT_RSTN
-};
-
-#define CCU_REG_TABLE_SIZE (sizeof(ccu_reg)/sizeof(ccu_reg[0]))
-
-/* Set priv_access_mode field to unrestricted (0) */
-static void ccu_init(void)
-{
-	uint32_t val;
-	uint32_t i;
-	for (i = 0; i < CCU_REG_TABLE_SIZE; i++) {
-		val = read32((void *)(ccu_reg[i]));
-		val &= ~WR_ACCESS_PRIVATE_ACCESS_MODE;
-		write32((void *)(ccu_reg[i]), val);
-	}
-}
-
-/*****************************************************************************
- * LCD
- *****************************************************************************/
-#define ASIU_TOP_CLK_GATING_CTRL			0x180aa024
-#define ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN	0x00000010
-#define ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN	0x00000008
-#define ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN	0x00000001
-#define ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN	0x00000002
-
-static void lcd_init(void)
-{
-	unsigned int val;
-
-	/* make sure the LCD clock is ungated */
-	val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
-	val |= ASIU_TOP_CLK_GATING_CTRL_LCD_CLK_GATE_EN;
-	write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-}
-
-/*******************************************************************
- * Default priority settings in Cygnus
- *
- *   Master Name                Default Priority
- *   ====================       =================
- *   ihost_m0                   12
- *   mhost0_m0                  12
- *   mhost1_m0              `   12
- *   pcie0_m0                   9
- *   pcie0_m1                   9
- *   cmicd_m0                   7
- *   amac_m0                    7
- *   amac_m1                    7
- *   ext_m0 (LCD)               5
- *   ext_m1 (V3D)               5
- *   sdio_m0                    3
- *   sdio_m1                    3
- *   usb2h_m0                   3
- *   usb2d_m0                   3
- *   dmu_m0                     3
- *   a9jtag_m0                  0
- *
- *****************************************************************************/
-
-#define AXIIC_EXT_M0_READ_QOS			0x1a057100
-#define AXIIC_EXT_M0_READ_MASK			0x0000000f
-#define AXIIC_EXT_M0_WRITE_QOS			0x1a057104
-#define AXIIC_EXT_M0_WRITE_MASK			0x0000000f
-
-static void lcd_qos_init(unsigned int qos)
-{
-	unsigned int val;
-
-	val = read32((void *)AXIIC_EXT_M0_READ_QOS);
-	val &= ~AXIIC_EXT_M0_READ_MASK;
-	val |= (qos & AXIIC_EXT_M0_READ_MASK);
-	write32((void *)AXIIC_EXT_M0_READ_QOS, val);
-
-	val = read32((void *)AXIIC_EXT_M0_WRITE_QOS);
-	val &= ~AXIIC_EXT_M0_WRITE_MASK;
-	val |= (qos & AXIIC_EXT_M0_WRITE_MASK);
-	write32((void *)AXIIC_EXT_M0_WRITE_QOS, val);
-}
-
-/*****************************************************************************
- * V3D
- *****************************************************************************/
-static void v3d_init(void)
-{
-	unsigned int val;
-
-	/* make sure the V3D clock is ungated */
-	val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
-	val |= ASIU_TOP_CLK_GATING_CTRL_MIPI_DSI_CLK_GATE_EN |
-	       ASIU_TOP_CLK_GATING_CTRL_GFX_CLK_GATE_EN;
-	write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-}
-
-/*****************************************************************************
- * Audio
- *****************************************************************************/
-#define CRMU_PLL_AON_CTRL				0x0301c020
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL	0x00000800
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG	0x00000400
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO	0x00000200
-#define CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN	0x00000100
-
-static void audio_init(void)
-{
-	unsigned int val;
-
-	/* Ungate (enable) audio clock. */
-	val = read32((void *)ASIU_TOP_CLK_GATING_CTRL);
-	val |= ASIU_TOP_CLK_GATING_CTRL_AUD_CLK_GATE_EN;
-	write32((void *)ASIU_TOP_CLK_GATING_CTRL, val);
-
-	/* Power on audio GEN PLL, LDO, and BG. Input isolation = normal. */
-	val = read32((void *)CRMU_PLL_AON_CTRL);
-	val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_BG;
-	val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_LDO;
-	val |= CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_PWRON_PLL;
-	val &= ~CRMU_PLL_AON_CTRL_ASIU_AUDIO_GENPLL_ISO_IN;
-	write32((void *)CRMU_PLL_AON_CTRL, val);
-}
-
-/*****************************************************************************
- * SDIO
- *****************************************************************************/
-#define CRMU_SDIO_1P8_FAIL_CONTROL	0x0301c0a0
-#define UHS1_18V_VREG_FAIL		0x00000001
-
-#define SDIO_IDM0_IO_CONTROL_DIRECT	0x18116408
-#define SDIO_IDM1_IO_CONTROL_DIRECT	0x18117408
-#define SDIO_CMD_COMFLICT_DISABLE	0x00400000
-#define SDIO_FEEDBACK_CLK_EN		0x00200000
-#define SDIO_CLK_ENABLE			0x00000001
-
-#define CDRU_SDIO0_IO_CONTROL		0x0301d144
-#define CDRU_SDIO1_IO_CONTROL		0x0301d140
-#define INPUT_DISABLE			0x00000080
-#define SLEW_RATE_ENABLE		0x00000040
-#define PULL_UP_ENABLE			0x00000020
-#define PULL_DOWN_ENABLE		0x00000010
-#define HYSTERESIS_ENABLE		0x00000008
-#define SDIO_DEFAULT_DRIVE_STRENGTH	0x4		/* 8 mA */
-
-#define SDIO_IDM0_IDM_RESET_CONTROL	0x18116800
-#define SDIO_IDM1_IDM_RESET_CONTROL	0x18117800
-#define SDIO_RESET_MASK			0x00000001
-#define SDIO_RESET_TIMEOUT		1000
-
-#define CRMU_SDIO_CONTROL0		0x0301d088
-#define CRMU_SDIO_CONTROL1		0x0301d08c
-#define CRMU_SDIO_CONTROL2		0x0301d090
-#define CRMU_SDIO_CONTROL3		0x0301d094
-#define CRMU_SDIO_CONTROL4		0x0301d098
-#define CRMU_SDIO_CONTROL5		0x0301d09c
-
-/*
- * SDIO_CAPS_L
- *
- * Field		Bit(s)
- * ===========================
- * DDR50		31
- * SDR104		30
- * SDR50		29
- * SLOTTYPE		28:27
- * ASYNCHIRQ		26
- * SYSBUS64		25
- * V18			24
- * V3			23
- * V33			22
- * SUPRSM		21
- * SDMA			20
- * HSPEED		19
- * ADMA2		18
- * EXTBUSMED		17
- * MAXBLK		16:15
- * BCLK			14:7
- * TOUT			6
- * TOUTFREQ		5:0
- */
-#define SDIO_CAPS_L			0xA17C0000
-
-/*
- * SDIO_CAPS_H
- *
- * Field		Bit(s)
- * ===========================
- * reserved		31:20
- * SPIBLOCKMODE		19
- * SPIMODE_CAP		18
- * CLOCKMULT		17:10
- * RETUNE_MODE		9:8
- * USETUNE_SDR50	7
- * TMRCNT_RETUNE	6:3
- * DRVR_TYPED		2
- * DRVR_TYPEC		1
- * DRVR_TYPEA		0
- */
-#define SDIO_CAPS_H			0x000C0087
-
-/*
- * Preset value
- *
- * Field		Bit(s)
- * ===========================
- * Driver Strength	12:11
- * Clock Generator	10
- * SDCLK Frequeency	9:0
- */
-
-/*
- * SDIO_PRESETVAL1
- *
- * Field		Bit(s)	Description
- * ============================================================
- * DDR50_PRESET		25:13	Preset Value for DDR50
- * DEFAULT_PRESET	12:0	Preset Value for Default Speed
- */
-#define SDIO_PRESETVAL1		0x01004004
-
-/*
- * SDIO_PRESETVAL2
- *
- * Field		Bit(s)	Description
- * ============================================================
- * HIGH_SPEED_PRESET	25:13	Preset Value for High Speed
- * INIT_PRESET		12:0	Preset Value for Initialization
- */
-#define SDIO_PRESETVAL2		0x01004100
-
-/*
- * SDIO_PRESETVAL3
- *
- * Field		Bit(s)	Description
- * ============================================================
- * SDR104_PRESET	25:13	Preset Value for SDR104
- * SDR12_PRESET		12:0	Preset Value for SDR12
- */
-#define SDIO_PRESETVAL3		0x00000004
-
-/*
- * SDIO_PRESETVAL4
- *
- * Field		Bit(s)	Description
- * ============================================================
- * SDR25_PRESET		25:13	Preset Value for SDR25
- * SDR50_PRESET		12:0	Preset Value for SDR50
- */
-#define SDIO_PRESETVAL4		0x01005001
-
-static void sdio_ctrl_init(unsigned int idx)
-{
-	unsigned int sdio_idm_io_control_direct_reg;
-	unsigned int cdru_sdio_io_control_reg;
-	unsigned int sdio_idm_reset_control_reg;
-	unsigned int val, timeout;
-
-	switch (idx) {
-	case 0:
-		sdio_idm_io_control_direct_reg = SDIO_IDM0_IO_CONTROL_DIRECT;
-		cdru_sdio_io_control_reg = CDRU_SDIO0_IO_CONTROL;
-		sdio_idm_reset_control_reg = SDIO_IDM0_IDM_RESET_CONTROL;
-		break;
-	case 1:
-		sdio_idm_io_control_direct_reg = SDIO_IDM1_IO_CONTROL_DIRECT;
-		cdru_sdio_io_control_reg = CDRU_SDIO1_IO_CONTROL;
-		sdio_idm_reset_control_reg = SDIO_IDM1_IDM_RESET_CONTROL;
-		break;
-	default:
-		return;
-	}
-
-	/*
-	 * Disable the cmd conflict error interrupt and enable feedback clock
-	 */
-	val = read32((void *)sdio_idm_io_control_direct_reg);
-	val |= SDIO_CMD_COMFLICT_DISABLE | SDIO_FEEDBACK_CLK_EN |
-	       SDIO_CLK_ENABLE;
-	write32((void *)sdio_idm_io_control_direct_reg, val);
-
-	/*
-	 * Set drive strength, enable hysteresis and slew rate control
-	 */
-	val = SDIO_DEFAULT_DRIVE_STRENGTH |
-		HYSTERESIS_ENABLE | SLEW_RATE_ENABLE;
-	write32((void *)cdru_sdio_io_control_reg, val);
-
-	/* Reset SDIO controller */
-	val = read32((void *)sdio_idm_reset_control_reg);
-	val |= SDIO_RESET_MASK;
-	write32((void *)sdio_idm_reset_control_reg, SDIO_RESET_MASK);
-	udelay(10);
-	val &= ~SDIO_RESET_MASK;
-	write32((void *)sdio_idm_reset_control_reg, val);
-
-	timeout = 0;
-	while (read32((void *)sdio_idm_reset_control_reg) & SDIO_RESET_MASK) {
-		udelay(1);
-		if (timeout++ > SDIO_RESET_TIMEOUT)
-			die("Failed to bring SDIO out of reset\n");
-	}
-}
-
-static void sdio_init(void)
-{
-	unsigned int val;
-
-	/*
-	 * Configure SDIO host controller capabilities
-	 * (common setting for all SDIO controllers)
-	 */
-	write32((void *)CRMU_SDIO_CONTROL0, SDIO_CAPS_H);
-	write32((void *)CRMU_SDIO_CONTROL1, SDIO_CAPS_L);
-	/*
-	 * Configure SDIO host controller preset values
-	 * (common setting for all SDIO controllers)
-	 */
-	write32((void *)CRMU_SDIO_CONTROL2, SDIO_PRESETVAL1);
-	write32((void *)CRMU_SDIO_CONTROL3, SDIO_PRESETVAL2);
-	write32((void *)CRMU_SDIO_CONTROL4, SDIO_PRESETVAL3);
-	write32((void *)CRMU_SDIO_CONTROL5, SDIO_PRESETVAL4);
-
-	/*
-	 * The sdhci driver attempts to change the SDIO IO voltage for UHS-I
-	 * cards by setting the EN1P8V in control2 register then checks the
-	 * outcome by reading it back.
-	 * Cygnus does not have an internal regulator for the SDIO IO voltage
-	 * but can be configured to indicate success (leave EN1P8V set)
-	 * or failure (clear EN1P8V).
-	 *
-	 * Clear CRMU_SDIO_UHS1_18V_VREG_FAIL in CRMU_SDIO_1P8_FAIL_CONTROL
-	 * register to indicate success.
-	 * (common setting for all SDIO controllers)
-	 */
-	val = read32((void *)CRMU_SDIO_1P8_FAIL_CONTROL);
-	val &= ~UHS1_18V_VREG_FAIL;
-	write32((void *)CRMU_SDIO_1P8_FAIL_CONTROL, val);
-
-	/*
-	 * Initialize each SDIO controller
-	 */
-	sdio_ctrl_init(0);
-	sdio_ctrl_init(1);
-}
-
-void hw_init(void)
-{
-	tz_init();
-	printk(BIOS_INFO, "trustzone initialized\n");
-	dmac_init();
-	printk(BIOS_INFO, "PL330 DMAC initialized\n");
-	lcd_init();
-	lcd_qos_init(15);
-	printk(BIOS_INFO, "LCD initialized\n");
-	v3d_init();
-	printk(BIOS_INFO, "V3D initialized\n");
-	audio_init();
-	printk(BIOS_INFO, "audio initialized\n");
-	neon_init();
-	printk(BIOS_INFO, "neon initialized\n");
-	pcie_init();
-	printk(BIOS_INFO, "PCIe initialized\n");
-	M0_init();
-	printk(BIOS_INFO, "M0 initialized\n");
-	ccu_init();
-	printk(BIOS_INFO, "CCU initialized\n");
-	sdio_init();
-	printk(BIOS_INFO, "SDIO initialized\n");
-}
diff --git a/src/soc/broadcom/cygnus/i2c.c b/src/soc/broadcom/cygnus/i2c.c
deleted file mode 100644
index ac431e7..0000000
--- a/src/soc/broadcom/cygnus/i2c.c
+++ /dev/null
@@ -1,266 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <assert.h>
-#include <console/console.h>
-#include <delay.h>
-#include <device/i2c_simple.h>
-#include <soc/i2c.h>
-
-struct cygnus_i2c_regs {
-	u32 i2c_con;
-	u32 i2c_timing_con;
-	u32 i2c_addr;
-	u32 i2c_fifo_master;
-	u32 i2c_fifo_slave;
-	u32 i2c_bit_bang;
-	u32 reserved0[(0x30 - 0x18) / 4];
-	u32 i2c_master_comm;
-	u32 i2c_slave_comm;
-	u32 i2c_int_en;
-	u32 i2c_int_status;
-	u32 i2c_master_data_wr;
-	u32 i2c_master_data_rd;
-	u32 i2c_slave_data_wr;
-	u32 i2c_slave_data_rd;
-	u32 reserved1[(0xb0 - 0x50) / 4];
-	u32 i2c_timing_con2;
-};
-
-static struct cygnus_i2c_regs *i2c_bus[] = {
-	(struct cygnus_i2c_regs *)0x18008000,
-	(struct cygnus_i2c_regs *)0x1800b000,
-};
-
-#define I2C_TIMEOUT_US	100000 /* 100ms */
-#define I2C_FIFO_MAX_SIZE 64
-
-#define ETIMEDOUT 1
-#define EINVAL 2
-#define EBUSY 3
-
-/* Configuration (0x0) */
-#define I2C_SMB_RESET (1 << 31)
-#define I2C_SMB_EN (1 << 30)
-
-/* Timing configuration (0x4) */
-#define I2C_MODE_400 (1 << 31)
-
-/* Master FIFO control (0xc) */
-#define I2C_MASTER_RX_FIFO_FLUSH (1 << 31)
-#define I2C_MASTER_TX_FIFO_FLUSH (1 << 30)
-
-/* Master command (0x30) */
-#define I2C_MASTER_START_BUSY (1 << 31)
-#define I2C_MASTER_STATUS_SFT 25
-#define I2C_MASTER_STATUS_MASK (0x7 << I2C_MASTER_STATUS_SFT)
-#define I2C_MASTER_PROT_SFT   9
-#define I2C_MASTER_PROT_BLK_WR (0x7 << I2C_MASTER_PROT_SFT)
-#define I2C_MASTER_PROT_BLK_RD (0x8 << I2C_MASTER_PROT_SFT)
-
-/* Master data write (0x40) */
-#define I2C_MASTER_WR_STATUS (1 << 31)
-
-/* Master data read (0x44) */
-#define I2C_MASTER_RD_DATA_MASK 0xff
-
-static unsigned int i2c_bus_busy(struct cygnus_i2c_regs *reg_addr)
-{
-	return read32(&reg_addr->i2c_master_comm) & I2C_MASTER_START_BUSY;
-}
-
-static int i2c_wait_bus_busy(struct cygnus_i2c_regs *reg_addr)
-{
-	int timeout = I2C_TIMEOUT_US;
-	while (timeout--) {
-		if (!i2c_bus_busy(reg_addr))
-			break;
-		udelay(1);
-	}
-
-	if (timeout <= 0)
-		return ETIMEDOUT;
-
-	return 0;
-}
-
-static void i2c_flush_fifo(struct cygnus_i2c_regs *reg_addr)
-{
-	write32(&reg_addr->i2c_fifo_master,
-		I2C_MASTER_RX_FIFO_FLUSH | I2C_MASTER_TX_FIFO_FLUSH);
-}
-
-static int i2c_write(struct cygnus_i2c_regs *reg_addr,
-		     struct i2c_msg *segment)
-{
-	uint8_t *data = segment->buf;
-	unsigned int val, status;
-	int i, ret;
-
-	write32(&reg_addr->i2c_master_data_wr, segment->slave << 1);
-
-	for (i = 0; i < segment->len; i++) {
-		val = data[i];
-
-		/* mark the last byte */
-		if (i == segment->len - 1)
-			val |= I2C_MASTER_WR_STATUS;
-
-		write32(&reg_addr->i2c_master_data_wr, val);
-	}
-	if (segment->len == 0)
-		write32(&reg_addr->i2c_master_data_wr, I2C_MASTER_WR_STATUS);
-
-	/*
-	 * Now we can activate the transfer.
-	 */
-	write32(&reg_addr->i2c_master_comm,
-		I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_WR);
-
-	ret = i2c_wait_bus_busy(reg_addr);
-	if (ret) {
-		printk(BIOS_ERR, "I2C bus timeout\n");
-		goto flush_fifo;
-	}
-
-	/* check transaction successful */
-	status = read32(&reg_addr->i2c_master_comm);
-	ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
-	if (ret) {
-		printk(BIOS_ERR, "I2C write error %u\n", status);
-		goto flush_fifo;
-	}
-
-	return 0;
-
-flush_fifo:
-	i2c_flush_fifo(reg_addr);
-	return ret;
-}
-
-static int i2c_read(struct cygnus_i2c_regs *reg_addr, struct i2c_msg *segment)
-{
-	uint8_t *data = segment->buf;
-	int i, ret;
-	unsigned int status;
-
-	write32(&reg_addr->i2c_master_data_wr, segment->slave << 1 | 1);
-
-	/*
-	 * Now we can activate the transfer. Specify the number of bytes to read
-	 */
-	write32(&reg_addr->i2c_master_comm,
-		I2C_MASTER_START_BUSY | I2C_MASTER_PROT_BLK_RD | segment->len);
-
-	ret = i2c_wait_bus_busy(reg_addr);
-	if (ret) {
-		printk(BIOS_ERR, "I2C bus timeout\n");
-		goto flush_fifo;
-	}
-
-	/* check transaction successful */
-	status = read32(&reg_addr->i2c_master_comm);
-	ret = (status & I2C_MASTER_STATUS_MASK) >> I2C_MASTER_STATUS_SFT;
-	if (ret) {
-		printk(BIOS_ERR, "I2C read error %u\n", status);
-		goto flush_fifo;
-	}
-
-	for (i = 0; i < segment->len; i++)
-		data[i] = read32(&reg_addr->i2c_master_data_rd) &
-			I2C_MASTER_RD_DATA_MASK;
-
-	return 0;
-
-flush_fifo:
-	i2c_flush_fifo(reg_addr);
-	return ret;
-}
-
-static int i2c_do_xfer(struct cygnus_i2c_regs *reg_addr,
-	struct i2c_msg *segment)
-{
-	int ret;
-
-	if (segment->len > I2C_FIFO_MAX_SIZE - 1) {
-		printk(BIOS_ERR,
-			"I2C transfer error: segment size (%d) is larger than limit (%d)\n",
-			segment->len, I2C_FIFO_MAX_SIZE);
-		return EINVAL;
-	}
-
-	if (i2c_bus_busy(reg_addr)) {
-		printk(BIOS_WARNING, "I2C transfer error: bus is busy\n");
-		return EBUSY;
-	}
-
-	if (segment->flags & I2C_M_RD)
-		ret = i2c_read(reg_addr, segment);
-	else
-		ret = i2c_write(reg_addr, segment);
-
-	return ret;
-}
-
-int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
-			  int seg_count)
-{
-	int i;
-	int res = 0;
-	struct cygnus_i2c_regs *regs = i2c_bus[bus];
-	struct i2c_msg *seg = segments;
-
-	for (i = 0; i < seg_count; i++, seg++) {
-		res = i2c_do_xfer(regs, seg);
-		if (res)
-			break;
-	}
-	return res;
-}
-
-void i2c_init(unsigned int bus, unsigned int hz)
-{
-	struct cygnus_i2c_regs *regs = i2c_bus[bus];
-
-	assert(bus >= 0 && bus <= 1);
-
-	setbits_le32(&regs->i2c_con, I2C_SMB_RESET);
-	udelay(100); /* wait 100 usec per spec */
-	clrbits_le32(&regs->i2c_con, I2C_SMB_RESET);
-
-	switch (hz) {
-	case 100000:
-		clrbits_le32(&regs->i2c_timing_con, I2C_MODE_400);
-		break;
-	case 400000:
-		setbits_le32(&regs->i2c_timing_con, I2C_MODE_400);
-		break;
-	default:
-		printk(BIOS_ERR, "I2C bus does not support frequency %d Hz\n",
-			hz);
-		break;
-	}
-
-	i2c_flush_fifo(regs);
-
-	/* disable all interrupts */
-	write32(&regs->i2c_int_en, 0);
-
-	/* clear all pending interrupts */
-	write32(&regs->i2c_int_status, 0xffffffff);
-
-	write32(&regs->i2c_con, I2C_SMB_EN);
-}
diff --git a/src/soc/broadcom/cygnus/include/soc/addressmap.h b/src/soc/broadcom/cygnus/include/soc/addressmap.h
deleted file mode 100644
index 9cc3a52..0000000
--- a/src/soc/broadcom/cygnus/include/soc/addressmap.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
-#define __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__
-
-#define IPROC_PERIPH_BASE		0x19020000
-#define IPROC_PERIPH_GLB_TIM_REG_BASE	(IPROC_PERIPH_BASE + 0x200)
-
-#define IPROC_QSPI_BASE			0x18047000
-
-#define IPROC_IOMUX_OVERRIDE_BASE	0x0301D24C
-
-#endif	/* __SOC_BROADCOM_CYGNUS_ADDRESSMAP_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/config.h b/src/soc/broadcom/cygnus/include/soc/config.h
deleted file mode 100644
index 0ba09e3..0000000
--- a/src/soc/broadcom/cygnus/include/soc/config.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-
-#ifndef __SOC_BROADCOM_CYGNUS_CONFIG_H__
-#define __SOC_BROADCOM_CYGNUS_CONFIG_H__
-
-#include <stdint.h>
-#include <string.h>
-#include <soc/halapis/ddr_regs.h>
-
-/* DDR shmoo Parameters */
-#define SDI_INTERFACE_BITWIDTH	16
-#define SDI_NUM_COLUMNS			1024
-#define SDI_NUM_BANKS			8
-
-#ifdef DDR3_SIZE_512MB
-#define SDI_NUM_ROWS			32768
-#else
-#define SDI_NUM_ROWS			65536
-#endif
-
-/* Idle count (in units of 1024 cycles) before auto entering self-refresh  */
-#define DDR_AUTO_SELF_REFRESH_IDLE_COUNT	16
-
-#endif /* __SOC_BROADCOM_CYGNUS_CONFIG_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus.h b/src/soc/broadcom/cygnus/include/soc/cygnus.h
deleted file mode 100644
index dac5d60..0000000
--- a/src/soc/broadcom/cygnus/include/soc/cygnus.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_H__
-#define __SOC_BROADCOM_CYGNUS_H__
-
-void usb_init(void);
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h b/src/soc/broadcom/cygnus/include/soc/cygnus_types.h
deleted file mode 100644
index 7466024..0000000
--- a/src/soc/broadcom/cygnus/include/soc/cygnus_types.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
-#define __SOC_BROADCOM_CYGNUS_CYGNUS_TYPES_H__
-
-#include <stdint.h>
-#include <types.h>
-
-#ifndef TRUE
-#define TRUE (1 == 1)
-#endif
-
-#ifndef FALSE
-#define FALSE (1 == 0)
-#endif
-
-#ifndef NULL
-#define NULL	0
-#endif
-
-/**********************************************************************
- *  Basic types
- **********************************************************************/
-
-typedef uint8_t  uint8;
-typedef int8_t   int8;
-typedef uint16_t uint16;
-typedef int16_t  int16;
-typedef int32_t  int32;
-typedef uint32_t uint32;
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h b/src/soc/broadcom/cygnus/include/soc/ddr_bist.h
deleted file mode 100644
index bce5222..0000000
--- a/src/soc/broadcom/cygnus/include/soc/ddr_bist.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
-#define __SOC_BROADCOM_CYGNUS_DDR_BIST_H__
-
-#include <soc/config.h>
-
-#define SOC_E_NONE (0)
-#define SOC_E_FAIL (-1)
-#define SOC_E_INTERNAL (-2)
-#define SOC_E_TIMEOUT (-3)
-#define SOC_E_PARAM   (-4)
-#define SOC_E_MEMORY  (-5)
-#define SOC_E_UNAVAIL (-6)
-#define SOC_E_CONFIG (-7)
-#define SOC_DDR3_CLOCK_MHZ(unit)	iproc_get_ddr3_clock_mhz(unit)
-
-#define DDR_SHMOO_PARAM_MEM_PTR         (0x1b000000) /*size ~0x300 */
-#define DDR_SHMOO_VREFW_MEM_PTR         (0x50000000) /* size ~0x30000 */
-#define SOC_DDR3_NUM_MEMORIES           (1)
-
-/* Convenience Macros - Arad Memory Controller - Recheck when MemC files change */
-enum drc_reg_set {
-	DRC_BIST_CONFIGr = 0,
-	DRC_BIST_CONFIG2r,
-	DRC_BIST_GENERAL_CONFIGURATIONSr,
-	DRC_BIST_CONFIGURATIONSr,
-	DRC_BIST_NUMBER_OF_ACTIONSr,
-	DRC_BIST_START_ADDRESSr,
-	DRC_BIST_END_ADDRESSr,
-	DRC_BIST_SINGLE_BIT_MASKr,
-	DRC_BIST_PATTERN_WORD_7r,
-	DRC_BIST_PATTERN_WORD_6r,
-	DRC_BIST_PATTERN_WORD_5r,
-	DRC_BIST_PATTERN_WORD_4r,
-	DRC_BIST_PATTERN_WORD_3r,
-	DRC_BIST_PATTERN_WORD_2r,
-	DRC_BIST_PATTERN_WORD_1r,
-	DRC_BIST_PATTERN_WORD_0r,
-	DRC_BIST_FULL_MASK_WORD_7r,
-	DRC_BIST_FULL_MASK_WORD_6r,
-	DRC_BIST_FULL_MASK_WORD_5r,
-	DRC_BIST_FULL_MASK_WORD_4r,
-	DRC_BIST_FULL_MASK_WORD_3r,
-	DRC_BIST_FULL_MASK_WORD_2r,
-	DRC_BIST_FULL_MASK_WORD_1r,
-	DRC_BIST_FULL_MASK_WORD_0r,
-	DRC_BIST_STATUSESr,
-	DRC_BIST_FULL_MASK_ERROR_COUNTERr,
-	DRC_BIST_SINGLE_BIT_MASK_ERROR_COUNTERr,
-	DRC_BIST_ERROR_OCCURREDr,
-	DRC_BIST_GLOBAL_ERROR_COUNTERr,
-	DRC_BIST_LAST_ADDR_ERRr,
-	DRC_BIST_LAST_DATA_ERR_WORD_7r,
-	DRC_BIST_LAST_DATA_ERR_WORD_6r,
-	DRC_BIST_LAST_DATA_ERR_WORD_5r,
-	DRC_BIST_LAST_DATA_ERR_WORD_4r,
-	DRC_BIST_LAST_DATA_ERR_WORD_3r,
-	DRC_BIST_LAST_DATA_ERR_WORD_2r,
-	DRC_BIST_LAST_DATA_ERR_WORD_1r,
-	DRC_BIST_LAST_DATA_ERR_WORD_0r
-};
-
-
-
-#define DRCA     DDR_BistConfig
-#define DRCB     DDR_BistConfig
-#define DRCC     DDR_BistConfig
-#define DRCD     DDR_BistConfig
-#define DRCE     DDR_BistConfig
-#define DRCF     DDR_BistConfig
-#define DRCG     DDR_BistConfig
-#define DRCH     DDR_BistConfig
-#define DRCALL   DDR_BistConfig
-
-#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_SHIFT 26
-#define DRCA_BIST_CONFIGURATIONSr_RESERVEDf_WIDTH 6
-#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_SHIFT 25
-#define DRCA_BIST_CONFIGURATIONSr_BIST_ENf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_SHIFT 24
-#define DRCA_BIST_CONFIGURATIONSr_DATA_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_SHIFT 23
-#define DRCA_BIST_CONFIGURATIONSr_DATA_SHIFT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_SHIFT 22
-#define DRCA_BIST_CONFIGURATIONSr_ADDRESS_SHIFT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_SHIFT 21
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_8_BANKSf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_SHIFT 20
-#define DRCA_BIST_CONFIGURATIONSr_CONS_ADDR_4_BANKSf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_SHIFT 19
-#define DRCA_BIST_CONFIGURATIONSr_IND_WR_RD_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_SHIFT 18
-#define DRCA_BIST_CONFIGURATIONSr_PRBS_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_SHIFT 17
-#define DRCA_BIST_CONFIGURATIONSr_TWO_ADDR_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_SHIFT 16
-#define DRCA_BIST_CONFIGURATIONSr_PATTERN_BIT_MODEf_WIDTH 1
-#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_SHIFT 8
-#define DRCA_BIST_CONFIGURATIONSr_READ_WEIGHTf_WIDTH 8
-#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_SHIFT 0
-#define DRCA_BIST_CONFIGURATIONSr_WRITE_WEIGHTf_WIDTH 8
-
-#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_SHIFT 0
-#define DRCA_BIST_NUMBER_OF_ACTIONSr_BIST_NUM_ACTIONSf_WIDTH 32
-
-
-#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_SHIFT 0
-#define DRCA_BIST_START_ADDRESSr_BIST_START_ADDRESSf_WIDTH 26
-#define DRCA_BIST_START_ADDRESSr_RESERVED_SHIFT 26
-#define DRCA_BIST_START_ADDRESSr_RESERVED_WIDTH 6
-
-#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_SHIFT 0
-#define DRCA_BIST_END_ADDRESSr_BIST_END_ADDRESSf_WIDTH 26
-#define DRCA_BIST_END_ADDRESSr_RESERVED_SHIFT 26
-#define DRCA_BIST_END_ADDRESSr_RESERVED_WIDTH 6
-
-#define DRCA_BIST_STATUSESr_RESERVED_SHIFT 4
-#define DRCA_BIST_STATUSESr_RESERVED_WIDTH 28
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_SHIFT 3
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_RADDRf_WIDTH 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_SHIFT 2
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_CMDf_WIDTH 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_SHIFT 1
-#define DRCA_BIST_STATUSESr_OVERFLOW_FIFO_WDATAf_WIDTH 1
-#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_SHIFT 0
-#define DRCA_BIST_STATUSESr_BIST_FINISHEDf_WIDTH 1
-
-#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_SHIFT 0
-#define DRCA_BIST_ERROR_OCCURREDr_ERR_OCCURREDf_WIDTH 32
-
-
-#define soc_reg_field_set(unit, r, m, f, data) \
-	(*(m) = ((*(m) & ~(((1 << r##_##f##_WIDTH) - 1) << r##_##f##_SHIFT)) | ((data & ((1 << r##_##f##_WIDTH) - 1)) << r##_##f##_SHIFT)))
-
-
-#define soc_reg_field_get(unit, r, m, f) \
-		((m >> r##_##f##_SHIFT) & ((1 << r##_##f##_WIDTH) - 1))
-
-
-#define DRC_REG_READ(unit, channel, reg, rvp) \
-	soc_reg32_get((volatile uint32*)(channel + 4 * reg), rvp)
-
-#define DRC_REG_WRITE(unit, channel, reg, rv) \
-	soc_reg32_set((volatile uint32*)(channel + 4 * reg), rv)
-
-#endif /* __SOC_BROADCOM_CYGNUS_DDR_BIST_H__ */
-
-/* End of File */
diff --git a/src/soc/broadcom/cygnus/include/soc/gpio.h b/src/soc/broadcom/cygnus/include/soc/gpio.h
deleted file mode 100644
index 69f06ce..0000000
--- a/src/soc/broadcom/cygnus/include/soc/gpio.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_GPIO_H__
-#define __SOC_BROADCOM_CYGNUS_GPIO_H__
-
-#include <types.h>
-
-#define ENOTSUPP	524	/* Operation is not supported */
-
-/* Supported GPIO types. Not all of these types are supported on all boards. */
-enum iproc_gpio_types {
-	IPROC_GPIO_CCA_ID,
-	IPROC_GPIO_CMICM_ID,
-	IPROC_GPIO_ASIU_ID
-};
-
-typedef u32 gpio_t;
-
-
-void *cygnus_pinmux_init(void);
-int cygnus_gpio_request_enable(void *priv, unsigned pin);
-void cygnus_gpio_disable_free(void *priv, unsigned pin);
-void gpio_init(void);
-void gpio_free(gpio_t gpio);
-
-#endif	/* __SOC_BROADCOM_CYGNUS_GPIO_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h b/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
deleted file mode 100644
index 32668d1..0000000
--- a/src/soc/broadcom/cygnus/include/soc/halapis/ddr_regs.h
+++ /dev/null
@@ -1,1074 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-#ifndef __SOC_BROADCOM_CYGNUS_DDR_REGS_H__
-#define __SOC_BROADCOM_CYGNUS_DDR_REGS_H__
-
-#define CRMU_DDR_PHY_AON_CTRL 0x0301c024
-#define CRMU_DDR_PHY_AON_CTRL_BASE 0x024
-#define CRMU_DDR_PHY_AON_CTRL_OFFSET 0x0301c024
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN 5
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_HW_RESETN_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY 4
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWROKIN_PHY_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY 3
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_PWRONIN_PHY_RESETVALUE 0x0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI 2
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_DFI_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_REGS_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL 0
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_WIDTH 1
-#define CRMU_DDR_PHY_AON_CTRL__CRMU_DDRPHY_ISO_PHY_PLL_RESETVALUE 0x1
-#define CRMU_DDR_PHY_AON_CTRL__RESERVED_L 31
-#define CRMU_DDR_PHY_AON_CTRL__RESERVED_R 6
-#define CRMU_DDR_PHY_AON_CTRL_WIDTH 6
-#define CRMU_DDR_PHY_AON_CTRL__WIDTH 6
-#define CRMU_DDR_PHY_AON_CTRL_ALL_L 5
-#define CRMU_DDR_PHY_AON_CTRL_ALL_R 0
-#define CRMU_DDR_PHY_AON_CTRL__ALL_L 5
-#define CRMU_DDR_PHY_AON_CTRL__ALL_R 0
-#define CRMU_DDR_PHY_AON_CTRL_DATAMASK 0x0000003f
-#define CRMU_DDR_PHY_AON_CTRL_RESETVALUE 0x7
-
-#define CRMU_IHOST_POR_WAKEUP_FLAG 0x03024c50
-#define CRMU_IHOST_POR_WAKEUP_FLAG_BASE 0xc50
-#define CRMU_IHOST_POR_WAKEUP_FLAG_OFFSET 0x03024c50
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG__IHOST_WAKE_FLAG_RESETVALUE 0x0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_L 31
-#define CRMU_IHOST_POR_WAKEUP_FLAG__RESERVED_R 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG_WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG__WIDTH 1
-#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_L 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG_ALL_R 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_L 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG__ALL_R 0
-#define CRMU_IHOST_POR_WAKEUP_FLAG_DATAMASK 0x00000001
-#define CRMU_IHOST_POR_WAKEUP_FLAG_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_00 0x18010000
-#define DDR_DENALI_CTL_00_BASE 0x000
-#define DDR_DENALI_CTL_00__VERSION_L 31
-#define DDR_DENALI_CTL_00__VERSION_R 16
-#define DDR_DENALI_CTL_00__VERSION_WIDTH 16
-#define DDR_DENALI_CTL_00__VERSION_RESETVALUE 0x2041
-#define DDR_DENALI_CTL_00__DRAM_CLASS_L 11
-#define DDR_DENALI_CTL_00__DRAM_CLASS_R 8
-#define DDR_DENALI_CTL_00__DRAM_CLASS_WIDTH 4
-#define DDR_DENALI_CTL_00__DRAM_CLASS_RESETVALUE 0x0
-#define DDR_DENALI_CTL_00__START 0
-#define DDR_DENALI_CTL_00__START_WIDTH 1
-#define DDR_DENALI_CTL_00__START_RESETVALUE 0x0
-#define DDR_DENALI_CTL_00__RESERVED_L 15
-#define DDR_DENALI_CTL_00__RESERVED_R 12
-#define DDR_DENALI_CTL_00_WIDTH 32
-#define DDR_DENALI_CTL_00__WIDTH 32
-#define DDR_DENALI_CTL_00_ALL_L 31
-#define DDR_DENALI_CTL_00_ALL_R 0
-#define DDR_DENALI_CTL_00__ALL_L 31
-#define DDR_DENALI_CTL_00__ALL_R 0
-#define DDR_DENALI_CTL_00_DATAMASK 0xffff0f01
-#define DDR_DENALI_CTL_00_RDWRMASK 0x0000f0fe
-#define DDR_DENALI_CTL_00_RESETVALUE 0x20410000
-
-#define DDR_DENALI_CTL_56 0x180100e0
-#define DDR_DENALI_CTL_56_BASE 0x0e0
-#define DDR_DENALI_CTL_56__LP_CMD_L 31
-#define DDR_DENALI_CTL_56__LP_CMD_R 24
-#define DDR_DENALI_CTL_56__LP_CMD_WIDTH 8
-#define DDR_DENALI_CTL_56__LP_CMD_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRX_F1_L 23
-#define DDR_DENALI_CTL_56__CKSRX_F1_R 16
-#define DDR_DENALI_CTL_56__CKSRX_F1_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRX_F1_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRE_F1_L 15
-#define DDR_DENALI_CTL_56__CKSRE_F1_R 8
-#define DDR_DENALI_CTL_56__CKSRE_F1_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRE_F1_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56__CKSRX_F0_L 7
-#define DDR_DENALI_CTL_56__CKSRX_F0_R 0
-#define DDR_DENALI_CTL_56__CKSRX_F0_WIDTH 8
-#define DDR_DENALI_CTL_56__CKSRX_F0_RESETVALUE 0x00
-#define DDR_DENALI_CTL_56_WIDTH 32
-#define DDR_DENALI_CTL_56__WIDTH 32
-#define DDR_DENALI_CTL_56_ALL_L 31
-#define DDR_DENALI_CTL_56_ALL_R 0
-#define DDR_DENALI_CTL_56__ALL_L 31
-#define DDR_DENALI_CTL_56__ALL_R 0
-#define DDR_DENALI_CTL_56_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_56_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_56_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57 0x180100e4
-#define DDR_DENALI_CTL_57_BASE 0x0e4
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_L 26
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_R 24
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_WIDTH 3
-#define DDR_DENALI_CTL_57__LP_AUTO_EXIT_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_L 18
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_R 16
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_WIDTH 3
-#define DDR_DENALI_CTL_57__LP_AUTO_ENTRY_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_L 11
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_R 8
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_WIDTH 4
-#define DDR_DENALI_CTL_57__LP_ARB_STATE_RESETVALUE 0x0
-#define DDR_DENALI_CTL_57__LP_STATE_L 5
-#define DDR_DENALI_CTL_57__LP_STATE_R 0
-#define DDR_DENALI_CTL_57__LP_STATE_WIDTH 6
-#define DDR_DENALI_CTL_57__LP_STATE_RESETVALUE 0x20
-#define DDR_DENALI_CTL_57__RESERVED_0_L 31
-#define DDR_DENALI_CTL_57__RESERVED_0_R 27
-#define DDR_DENALI_CTL_57__RESERVED_1_L 23
-#define DDR_DENALI_CTL_57__RESERVED_1_R 19
-#define DDR_DENALI_CTL_57__RESERVED_2_L 15
-#define DDR_DENALI_CTL_57__RESERVED_2_R 12
-#define DDR_DENALI_CTL_57__RESERVED_3_L 7
-#define DDR_DENALI_CTL_57__RESERVED_3_R 6
-#define DDR_DENALI_CTL_57__RESERVED_L 31
-#define DDR_DENALI_CTL_57__RESERVED_R 27
-#define DDR_DENALI_CTL_57_WIDTH 27
-#define DDR_DENALI_CTL_57__WIDTH 27
-#define DDR_DENALI_CTL_57_ALL_L 26
-#define DDR_DENALI_CTL_57_ALL_R 0
-#define DDR_DENALI_CTL_57__ALL_L 26
-#define DDR_DENALI_CTL_57__ALL_R 0
-#define DDR_DENALI_CTL_57_DATAMASK 0x07070f3f
-#define DDR_DENALI_CTL_57_RDWRMASK 0xf8f8f0c0
-#define DDR_DENALI_CTL_57_RESETVALUE 0x20
-#define DDR_DENALI_CTL_58 0x180100e8
-#define DDR_DENALI_CTL_58_BASE 0x0e8
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_L 31
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_R 24
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_WIDTH 8
-#define DDR_DENALI_CTL_58__LP_AUTO_SR_IDLE_RESETVALUE 0x00
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_L 19
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_R 8
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_WIDTH 12
-#define DDR_DENALI_CTL_58__LP_AUTO_PD_IDLE_RESETVALUE 0x000
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_L 1
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_R 0
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_WIDTH 2
-#define DDR_DENALI_CTL_58__LP_AUTO_MEM_GATE_EN_RESETVALUE 0x0
-#define DDR_DENALI_CTL_58__RESERVED_L 23
-#define DDR_DENALI_CTL_58__RESERVED_R 20
-#define DDR_DENALI_CTL_58_WIDTH 32
-#define DDR_DENALI_CTL_58__WIDTH 32
-#define DDR_DENALI_CTL_58_ALL_L 31
-#define DDR_DENALI_CTL_58_ALL_R 0
-#define DDR_DENALI_CTL_58__ALL_L 31
-#define DDR_DENALI_CTL_58__ALL_R 0
-#define DDR_DENALI_CTL_58_DATAMASK 0xff0fff03
-#define DDR_DENALI_CTL_58_RDWRMASK 0x00f000fc
-#define DDR_DENALI_CTL_58_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_175 0x180102bc
-#define DDR_DENALI_CTL_175_BASE 0x2bc
-#define DDR_DENALI_CTL_175__INT_STATUS_L 31
-#define DDR_DENALI_CTL_175__INT_STATUS_R 0
-#define DDR_DENALI_CTL_175__INT_STATUS_WIDTH 32
-#define DDR_DENALI_CTL_175__INT_STATUS_RESETVALUE 0x00000000
-#define DDR_DENALI_CTL_175_WIDTH 32
-#define DDR_DENALI_CTL_175__WIDTH 32
-#define DDR_DENALI_CTL_175_ALL_L 31
-#define DDR_DENALI_CTL_175_ALL_R 0
-#define DDR_DENALI_CTL_175__ALL_L 31
-#define DDR_DENALI_CTL_175__ALL_R 0
-#define DDR_DENALI_CTL_175_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_175_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_175_RESETVALUE 0x0
-
-#define DDR_DENALI_CTL_177 0x180102c4
-#define DDR_DENALI_CTL_177_BASE 0x2c4
-#define DDR_DENALI_CTL_177__INT_ACK_L 31
-#define DDR_DENALI_CTL_177__INT_ACK_R 0
-#define DDR_DENALI_CTL_177__INT_ACK_WIDTH 32
-#define DDR_DENALI_CTL_177__INT_ACK_RESETVALUE 0x00000000
-#define DDR_DENALI_CTL_177_WIDTH 32
-#define DDR_DENALI_CTL_177__WIDTH 32
-#define DDR_DENALI_CTL_177_ALL_L 31
-#define DDR_DENALI_CTL_177_ALL_R 0
-#define DDR_DENALI_CTL_177__ALL_L 31
-#define DDR_DENALI_CTL_177__ALL_R 0
-#define DDR_DENALI_CTL_177_DATAMASK 0xffffffff
-#define DDR_DENALI_CTL_177_RDWRMASK 0x00000000
-#define DDR_DENALI_CTL_177_RESETVALUE 0x0
-
-#define DDR_BistConfig 0x18010c00
-#define DDR_BistConfig_BASE 0xc00
-#define DDR_BistConfig__bist_finished_period_L 24
-#define DDR_BistConfig__bist_finished_period_R 17
-#define DDR_BistConfig__bist_finished_period_WIDTH 8
-#define DDR_BistConfig__bist_finished_period_RESETVALUE 0x00
-#define DDR_BistConfig__clr_bist_last_data_err 16
-#define DDR_BistConfig__clr_bist_last_data_err_WIDTH 1
-#define DDR_BistConfig__clr_bist_last_data_err_RESETVALUE 0x0
-#define DDR_BistConfig__bus16_mode 15
-#define DDR_BistConfig__bus16_mode_WIDTH 1
-#define DDR_BistConfig__bus16_mode_RESETVALUE 0x0
-#define DDR_BistConfig__enable_8_banks_mode 14
-#define DDR_BistConfig__enable_8_banks_mode_WIDTH 1
-#define DDR_BistConfig__enable_8_banks_mode_RESETVALUE 0x0
-#define DDR_BistConfig__disable_col_bank_swapping 13
-#define DDR_BistConfig__disable_col_bank_swapping_WIDTH 1
-#define DDR_BistConfig__disable_col_bank_swapping_RESETVALUE 0x0
-#define DDR_BistConfig__bist_arpriority_L 12
-#define DDR_BistConfig__bist_arpriority_R 10
-#define DDR_BistConfig__bist_arpriority_WIDTH 3
-#define DDR_BistConfig__bist_arpriority_RESETVALUE 0x0
-#define DDR_BistConfig__bist_arapcmd 9
-#define DDR_BistConfig__bist_arapcmd_WIDTH 1
-#define DDR_BistConfig__bist_arapcmd_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awuser 8
-#define DDR_BistConfig__bist_awuser_WIDTH 1
-#define DDR_BistConfig__bist_awuser_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awpriority_L 7
-#define DDR_BistConfig__bist_awpriority_R 5
-#define DDR_BistConfig__bist_awpriority_WIDTH 3
-#define DDR_BistConfig__bist_awpriority_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awcobuf 4
-#define DDR_BistConfig__bist_awcobuf_WIDTH 1
-#define DDR_BistConfig__bist_awcobuf_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awapcmd 3
-#define DDR_BistConfig__bist_awapcmd_WIDTH 1
-#define DDR_BistConfig__bist_awapcmd_RESETVALUE 0x0
-#define DDR_BistConfig__bist_awcache_0 2
-#define DDR_BistConfig__bist_awcache_0_WIDTH 1
-#define DDR_BistConfig__bist_awcache_0_RESETVALUE 0x0
-#define DDR_BistConfig__axi_port_sel 1
-#define DDR_BistConfig__axi_port_sel_WIDTH 1
-#define DDR_BistConfig__axi_port_sel_RESETVALUE 0x0
-#define DDR_BistConfig__bist_resetb 0
-#define DDR_BistConfig__bist_resetb_WIDTH 1
-#define DDR_BistConfig__bist_resetb_RESETVALUE 0x0
-#define DDR_BistConfig__RESERVED_L 31
-#define DDR_BistConfig__RESERVED_R 25
-#define DDR_BistConfig_WIDTH 25
-#define DDR_BistConfig__WIDTH 25
-#define DDR_BistConfig_ALL_L 24
-#define DDR_BistConfig_ALL_R 0
-#define DDR_BistConfig__ALL_L 24
-#define DDR_BistConfig__ALL_R 0
-#define DDR_BistConfig_DATAMASK 0x01ffffff
-#define DDR_BistConfig_RDWRMASK 0xfe000000
-#define DDR_BistConfig_RESETVALUE 0x0
-
-#define DDR_BistGeneralConfigurations 0x18010c08
-#define DDR_BistGeneralConfigurations_BASE 0xc08
-#define DDR_BistGeneralConfigurations__NumCols_L 6
-#define DDR_BistGeneralConfigurations__NumCols_R 4
-#define DDR_BistGeneralConfigurations__NumCols_WIDTH 3
-#define DDR_BistGeneralConfigurations__NumCols_RESETVALUE 0x2
-#define DDR_BistGeneralConfigurations__RESERVED_L 31
-#define DDR_BistGeneralConfigurations__RESERVED_R 7
-#define DDR_BistGeneralConfigurations_WIDTH 7
-#define DDR_BistGeneralConfigurations__WIDTH 7
-#define DDR_BistGeneralConfigurations_ALL_L 6
-#define DDR_BistGeneralConfigurations_ALL_R 0
-#define DDR_BistGeneralConfigurations__ALL_L 6
-#define DDR_BistGeneralConfigurations__ALL_R 0
-#define DDR_BistGeneralConfigurations_DATAMASK 0x00000070
-#define DDR_BistGeneralConfigurations_RDWRMASK 0xffffff8f
-#define DDR_BistGeneralConfigurations_RESETVALUE 0x20
-
-#define DDR_PHY_CONTROL_REGS_REVISION 0x18011000
-#define DDR_PHY_CONTROL_REGS_REVISION_BASE 0x000
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_R 25
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_WIDTH 7
-#define DDR_PHY_CONTROL_REGS_REVISION__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_L 24
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_R 23
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_REVISION__PERFORMANCE_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_L 22
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_R 20
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_REVISION__TECHNOLOGY_RESETVALUE 0x2
-#define DDR_PHY_CONTROL_REGS_REVISION__WB 19
-#define DDR_PHY_CONTROL_REGS_REVISION__WB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_REVISION__WB_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_L 18
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_R 16
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_REVISION__BITS_RESETVALUE 0x2
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_L 15
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_R 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MAJOR_RESETVALUE 0xe2
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_L 7
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_REVISION__MINOR_RESETVALUE 0x01
-#define DDR_PHY_CONTROL_REGS_REVISION_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_REVISION__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_REVISION_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_REVISION__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_REVISION_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_REVISION_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_REVISION_RESETVALUE 0xa2e201
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS 0x18011004
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_BASE 0x004
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_WIDTH 4
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCK_GEN_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_L 19
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_R 17
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_WIDTH 3
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST 16
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_LOST_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X 15
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_8X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X 14
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_4X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X 13
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__CLOCKING_2X_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_L 12
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_R 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_WIDTH 12
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__STATUS_RESETVALUE 0x000
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__LOCK_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__RESERVED_R 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_WIDTH 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__WIDTH 24
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_L 23
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_DATAMASK 0x00ffffff
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RDWRMASK 0xff000000
-#define DDR_PHY_CONTROL_REGS_PLL_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG 0x18011008
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_BASE 0x008
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_for_eco_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_L 26
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_R 25
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_REF_CTRL_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_L 24
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_R 23
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__CK_LDO_BIAS_RESETVALUE 0x3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL 22
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_SEL_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_L 21
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_REF_CTRL_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_L 19
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_R 18
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PLL_LDO_BIAS_RESETVALUE 0x3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD 17
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__HOLD_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE 16
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ENABLE_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_L 13
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_R 8
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__FB_OFFSET_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV 4
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_POST_DIV_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_L 3
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESET_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__PWRDN_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_0_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_L 15
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_1_R 14
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_L 7
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_2_R 5
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_DATAMASK 0x0fff3f1f
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RDWRMASK 0xf000c0e0
-#define DDR_PHY_CONTROL_REGS_PLL_CONFIG_RESETVALUE 0x39d0000
-
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS 0x18011018
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_BASE 0x018
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_R 20
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_WIDTH 8
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__MDIV_RESETVALUE 0x01
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_L 15
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_R 12
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_WIDTH 4
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__PDIV_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_L 11
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_R 10
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_L 9
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_WIDTH 10
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__NDIV_INT_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_DATAMASK 0x0ff0ffff
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RDWRMASK 0xf00f0000
-#define DDR_PHY_CONTROL_REGS_PLL_DIVIDERS_RESETVALUE 0x101020
-
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x1801102c
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_BASE 0x02c
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE 30
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DIB_MODE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_L 29
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_R 4
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_WIDTH 26
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RESETVALUE 0xa
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x18011030
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_BASE 0x030
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_R 11
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_WIDTH 21
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_L 10
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x18011034
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_BASE 0x034
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_R 22
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_WIDTH 10
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_L 21
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_WIDTH 22
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_RESETVALUE 0x0
-
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x1801103c
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_BASE 0x03c
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__AUTO_OEB_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5 26
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_GDDR5_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR 25
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_LPDDR_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1 24
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0 23
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CLK0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT 22
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_ODT_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR 21
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_PAR_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA 20
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_BA_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2 19
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX2_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1 18
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0 17
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_AUX0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1 16
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_CS1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15 15
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A15_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14 14
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A14_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13 13
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A13_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12 12
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A12_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11 11
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A11_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10 10
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A10_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09 9
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__IDDQ_A09_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_L 8
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_WIDTH 7
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_L 1
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RX_MODE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__RESERVED_R 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_WIDTH 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__WIDTH 28
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_L 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_L 27
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_DATAMASK 0x0fffffff
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RDWRMASK 0xf0000000
-#define DDR_PHY_CONTROL_REGS_STATIC_PAD_CTL_RESETVALUE 0x0
-
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x18011200
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_BASE 0x200
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_R 20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_WIDTH 12
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__reserved_RESETVALUE 0x000
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT 19
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__AUX_GT_INT_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_L 18
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_R 17
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_WIDTH 2
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TESTOUT_MUX_CTL_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST 16
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__TEST_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3 15
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN3_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2 14
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN2_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1 13
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN1_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0 12
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__PDN0_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_L 11
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_R 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC1_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_L 5
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_WIDTH 6
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__DAC0_RESETVALUE 0x20
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_VREF_DAC_CONTROL_RESETVALUE 0xf820
-
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL 0x1801123c
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_BASE 0x23c
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_R 10
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_WIDTH 22
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1 9
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0 8
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__SELF_REFRESH_CS0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1 7
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS1_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0 6
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CS0_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N 5
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_RST_N_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1 4
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE1_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0 3
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__DFI_CKE0_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE 2
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ACK_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ASSERT_REQ_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_WIDTH 32
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__WIDTH 32
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_L 31
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_DATAMASK 0xffffffff
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RDWRMASK 0x00000000
-#define DDR_PHY_CONTROL_REGS_DFI_CNTRL_RESETVALUE 0xe1
-
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL 0x18011248
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_BASE 0x248
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS 18
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_STATUS_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ 17
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_IDDQ_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_L 16
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_R 12
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_P_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_L 11
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_R 7
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_DRIVE_N_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_L 6
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_R 2
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_WIDTH 5
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__reserved_RESETVALUE 0x0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_PCOMP_ENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_WIDTH 1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ZQ_NCOMP_ENB_RESETVALUE 0x1
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_L 31
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__RESERVED_R 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_WIDTH 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__WIDTH 20
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_L 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_ALL_R 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_L 19
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL__ALL_R 0
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_DATAMASK 0x000fffff
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RDWRMASK 0xfff00000
-#define DDR_PHY_CONTROL_REGS_ZQ_CAL_RESETVALUE 0x20003
-
-#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x18011400
-#define DDR_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P_BASE 0x400
-
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x180114c8
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_BASE 0x4c8
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved 15
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_L 30
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__RESERVED_R 20
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
-#define DDR_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_RESETVALUE 0x5000a
-
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x180116c8
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_BASE 0x6c8
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_L 19
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_R 18
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_RXENB_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_L 17
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_R 16
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_WIDTH 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__AUTO_DQ_IDDQ_MODE_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved 15
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__reserved_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_L 14
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_R 4
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_WIDTH 11
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IO_IDLE_ENABLE_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB 3
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RXENB_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ 2
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__IDDQ_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_N_RESETVALUE 0x1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_WIDTH 1
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__DOUT_P_RESETVALUE 0x0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_L 30
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__RESERVED_R 20
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_WIDTH 32
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__WIDTH 32
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_L 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_ALL_R 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_L 31
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL__ALL_R 0
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_DATAMASK 0x800fffff
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RDWRMASK 0x7ff00000
-#define DDR_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_RESETVALUE 0x5000a
-
-#define IHOST_SCU_POWER_STATUS 0x19020008
-#define IHOST_SCU_POWER_STATUS_BASE 0x008
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_L 25
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_R 24
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU3_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_L 17
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_R 16
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU2_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_L 9
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_R 8
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU1_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__reserved_L 7
-#define IHOST_SCU_POWER_STATUS__reserved_R 2
-#define IHOST_SCU_POWER_STATUS__reserved_WIDTH 6
-#define IHOST_SCU_POWER_STATUS__reserved_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_L 1
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_R 0
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_WIDTH 2
-#define IHOST_SCU_POWER_STATUS__CPU0_STATUS_RESETVALUE 0x0
-#define IHOST_SCU_POWER_STATUS__RESERVED_0_L 31
-#define IHOST_SCU_POWER_STATUS__RESERVED_0_R 26
-#define IHOST_SCU_POWER_STATUS__RESERVED_1_L 23
-#define IHOST_SCU_POWER_STATUS__RESERVED_1_R 18
-#define IHOST_SCU_POWER_STATUS__RESERVED_2_L 15
-#define IHOST_SCU_POWER_STATUS__RESERVED_2_R 10
-#define IHOST_SCU_POWER_STATUS__RESERVED_L 31
-#define IHOST_SCU_POWER_STATUS__RESERVED_R 26
-#define IHOST_SCU_POWER_STATUS_WIDTH 26
-#define IHOST_SCU_POWER_STATUS__WIDTH 26
-#define IHOST_SCU_POWER_STATUS_ALL_L 25
-#define IHOST_SCU_POWER_STATUS_ALL_R 0
-#define IHOST_SCU_POWER_STATUS__ALL_L 25
-#define IHOST_SCU_POWER_STATUS__ALL_R 0
-#define IHOST_SCU_POWER_STATUS_DATAMASK 0x030303ff
-#define IHOST_SCU_POWER_STATUS_RDWRMASK 0xfcfcfc00
-#define IHOST_SCU_POWER_STATUS_RESETVALUE 0x0
-
-#define IHOST_GTIM_GLOB_CTRL 0x19020208
-#define IHOST_GTIM_GLOB_CTRL_BASE 0x208
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_L 15
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_R 8
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_WIDTH 8
-#define IHOST_GTIM_GLOB_CTRL__Prescaler_G_RESETVALUE 0x00
-#define IHOST_GTIM_GLOB_CTRL__reserved_L 7
-#define IHOST_GTIM_GLOB_CTRL__reserved_R 4
-#define IHOST_GTIM_GLOB_CTRL__reserved_WIDTH 4
-#define IHOST_GTIM_GLOB_CTRL__reserved_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G 3
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Autoincr_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G 2
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__IRQ_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G 1
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Comp_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G 0
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_WIDTH 1
-#define IHOST_GTIM_GLOB_CTRL__Timer_en_G_RESETVALUE 0x0
-#define IHOST_GTIM_GLOB_CTRL__RESERVED_L 31
-#define IHOST_GTIM_GLOB_CTRL__RESERVED_R 16
-#define IHOST_GTIM_GLOB_CTRL_WIDTH 16
-#define IHOST_GTIM_GLOB_CTRL__WIDTH 16
-#define IHOST_GTIM_GLOB_CTRL_ALL_L 15
-#define IHOST_GTIM_GLOB_CTRL_ALL_R 0
-#define IHOST_GTIM_GLOB_CTRL__ALL_L 15
-#define IHOST_GTIM_GLOB_CTRL__ALL_R 0
-#define IHOST_GTIM_GLOB_CTRL_DATAMASK 0x0000ffff
-#define IHOST_GTIM_GLOB_CTRL_RDWRMASK 0xffff0000
-#define IHOST_GTIM_GLOB_CTRL_RESETVALUE 0x0
-
-#define DDR_S0_IDM_RESET_CONTROL 0xf8101800
-#define DDR_S0_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S0_IDM_RESET_CONTROL__RESET 0
-#define DDR_S0_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL__RESET_RESETVALUE 0x0
-#define DDR_S0_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S0_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S0_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S0_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S0_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S0_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S0_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S0_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S0_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S0_IDM_RESET_CONTROL_RESETVALUE 0x0
-
-#define DDR_S1_IDM_IO_CONTROL_DIRECT 0xf8102408
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_BASE 0x408
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_use_master_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf 30
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcobuf_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0 29
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__axi_s1_awcache_0_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn 28
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_pwrdn_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n 27
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_force_cke_rst_n_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb 26
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_pll_resetb_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby 13
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_standby_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps 12
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_read_straps_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank 11
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_dual_rank_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_L 10
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_R 9
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_WIDTH 2
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_volts_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_L 8
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_R 4
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_WIDTH 5
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_jedec_RESETVALUE 0xb
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid 3
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_phy_straps_valid_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init 2
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__i_sw_init_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_WIDTH 1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__clk_enable_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_L 25
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__RESERVED_R 14
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_WIDTH 32
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__WIDTH 32
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_L 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_ALL_R 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_L 31
-#define DDR_S1_IDM_IO_CONTROL_DIRECT__ALL_R 0
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_DATAMASK 0xfc003ffd
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_RDWRMASK 0x03ffc002
-#define DDR_S1_IDM_IO_CONTROL_DIRECT_RESETVALUE 0x600010b9
-#define DDR_S1_IDM_IO_STATUS 0xf8102500
-#define DDR_S1_IDM_IO_STATUS_BASE 0x500
-#define DDR_S1_IDM_IO_STATUS__RESERVED_L 31
-#define DDR_S1_IDM_IO_STATUS__RESERVED_R 4
-#define DDR_S1_IDM_IO_STATUS__RESERVED_WIDTH 28
-#define DDR_S1_IDM_IO_STATUS__RESERVED_RESETVALUE 0x0000000
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb 3
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_WIDTH 1
-#define DDR_S1_IDM_IO_STATUS__o_phy_pwrup_rsb_RESETVALUE 0x1
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready 2
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready_WIDTH 1
-#define DDR_S1_IDM_IO_STATUS__o_phy_ready_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_STATUS__ddr_type_L 1
-#define DDR_S1_IDM_IO_STATUS__ddr_type_R 0
-#define DDR_S1_IDM_IO_STATUS__ddr_type_WIDTH 2
-#define DDR_S1_IDM_IO_STATUS__ddr_type_RESETVALUE 0x0
-#define DDR_S1_IDM_IO_STATUS_WIDTH 32
-#define DDR_S1_IDM_IO_STATUS__WIDTH 32
-#define DDR_S1_IDM_IO_STATUS_ALL_L 31
-#define DDR_S1_IDM_IO_STATUS_ALL_R 0
-#define DDR_S1_IDM_IO_STATUS__ALL_L 31
-#define DDR_S1_IDM_IO_STATUS__ALL_R 0
-#define DDR_S1_IDM_IO_STATUS_DATAMASK 0xffffffff
-#define DDR_S1_IDM_IO_STATUS_RDWRMASK 0x00000000
-#define DDR_S1_IDM_IO_STATUS_RESETVALUE 0x8
-#define DDR_S1_IDM_RESET_CONTROL 0xf8102800
-#define DDR_S1_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S1_IDM_RESET_CONTROL__RESET 0
-#define DDR_S1_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
-#define DDR_S1_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S1_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S1_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S1_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S1_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S1_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S1_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S1_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S1_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S1_IDM_RESET_CONTROL_RESETVALUE 0x1
-
-#define DDR_S2_IDM_RESET_CONTROL 0xf8103800
-#define DDR_S2_IDM_RESET_CONTROL_BASE 0x800
-#define DDR_S2_IDM_RESET_CONTROL__RESET 0
-#define DDR_S2_IDM_RESET_CONTROL__RESET_WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL__RESET_RESETVALUE 0x1
-#define DDR_S2_IDM_RESET_CONTROL__RESERVED_L 31
-#define DDR_S2_IDM_RESET_CONTROL__RESERVED_R 1
-#define DDR_S2_IDM_RESET_CONTROL_WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL__WIDTH 1
-#define DDR_S2_IDM_RESET_CONTROL_ALL_L 0
-#define DDR_S2_IDM_RESET_CONTROL_ALL_R 0
-#define DDR_S2_IDM_RESET_CONTROL__ALL_L 0
-#define DDR_S2_IDM_RESET_CONTROL__ALL_R 0
-#define DDR_S2_IDM_RESET_CONTROL_DATAMASK 0x00000001
-#define DDR_S2_IDM_RESET_CONTROL_RDWRMASK 0xfffffffe
-#define DDR_S2_IDM_RESET_CONTROL_RESETVALUE 0x1
-
-#define ROM_S0_IDM_IO_STATUS 0xf8104500
-#define ROM_S0_IDM_IO_STATUS_BASE 0x500
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl 16
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_WIDTH 1
-#define ROM_S0_IDM_IO_STATUS__jump_to_sbl_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_L 11
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_R 8
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_WIDTH 4
-#define ROM_S0_IDM_IO_STATUS__strap_sku_vect_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_L 3
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_R 0
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_WIDTH 4
-#define ROM_S0_IDM_IO_STATUS__strap_boot_dev_RESETVALUE 0x0
-#define ROM_S0_IDM_IO_STATUS__RESERVED_0_L 31
-#define ROM_S0_IDM_IO_STATUS__RESERVED_0_R 17
-#define ROM_S0_IDM_IO_STATUS__RESERVED_1_L 15
-#define ROM_S0_IDM_IO_STATUS__RESERVED_1_R 12
-#define ROM_S0_IDM_IO_STATUS__RESERVED_2_L 7
-#define ROM_S0_IDM_IO_STATUS__RESERVED_2_R 4
-#define ROM_S0_IDM_IO_STATUS__RESERVED_L 31
-#define ROM_S0_IDM_IO_STATUS__RESERVED_R 17
-#define ROM_S0_IDM_IO_STATUS_WIDTH 17
-#define ROM_S0_IDM_IO_STATUS__WIDTH 17
-#define ROM_S0_IDM_IO_STATUS_ALL_L 16
-#define ROM_S0_IDM_IO_STATUS_ALL_R 0
-#define ROM_S0_IDM_IO_STATUS__ALL_L 16
-#define ROM_S0_IDM_IO_STATUS__ALL_R 0
-#define ROM_S0_IDM_IO_STATUS_DATAMASK 0x00010f0f
-#define ROM_S0_IDM_IO_STATUS_RDWRMASK 0xfffef0f0
-#define ROM_S0_IDM_IO_STATUS_RESETVALUE 0x0
-#endif /* __SOC_BROADCOM_CYGNUS_DDR_REGS_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/hw_init.h b/src/soc/broadcom/cygnus/include/soc/hw_init.h
deleted file mode 100644
index 83dd7f3..0000000
--- a/src/soc/broadcom/cygnus/include/soc/hw_init.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2015 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_HW_INIT_H__
-#define __SOC_BROADCOM_CYGNUS_HW_INIT_H__
-
-void hw_init(void);
-
-#endif
diff --git a/src/soc/broadcom/cygnus/include/soc/i2c.h b/src/soc/broadcom/cygnus/include/soc/i2c.h
deleted file mode 100644
index 96b5346..0000000
--- a/src/soc/broadcom/cygnus/include/soc/i2c.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_I2C_H__
-#define __SOC_BROADCOM_CYGNUS_I2C_H__
-
-void i2c_init(unsigned int bus, unsigned int hz);
-
-#endif	/* __SOC_BROADCOM_CYGNUS_I2C_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/memlayout.ld b/src/soc/broadcom/cygnus/include/soc/memlayout.ld
deleted file mode 100644
index 42b59da..0000000
--- a/src/soc/broadcom/cygnus/include/soc/memlayout.ld
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <memlayout.h>
-
-#include <arch/header.ld>
-
-SECTIONS
-{
-	SRAM_START(0x02000000)
-	REGION(reserved_for_system_status, 0x02000000, 4K, 4)
-	TTB(0x02004000, 16K)		/* must be aligned to 16K */
-	TTB_SUBTABLES(0x02008000, 1K)
-	REGION(reserved_for_maskrom, 0x02009400, 4K, 4)
-	BOOTBLOCK(0x0200A440, 18K)
-	PRERAM_CBMEM_CONSOLE(0x0200F000, 2K)
-	VBOOT2_WORK(0x0200f800, 16K)
-	OVERLAP_VERSTAGE_ROMSTAGE(0x02013800, 122K)
-	PRERAM_CBFS_CACHE(0x02032000, 1K)
-	TIMESTAMP(0x02032400, 1K)
-	STACK(0x02033000, 12K)
-	REGION(reserved_for_secure_service_api, 0x0203F000, 4K, 4)
-	SRAM_END(0x02040000)
-
-	DRAM_START(0x60000000)
-	RAMSTAGE(0x60000000, 128K)
-	POSTRAM_CBFS_CACHE(0x60100000, 1M)
-	DMA_COHERENT(0x60200000, 2M)
-}
diff --git a/src/soc/broadcom/cygnus/include/soc/ns16550.h b/src/soc/broadcom/cygnus/include/soc/ns16550.h
deleted file mode 100644
index b95bf88..0000000
--- a/src/soc/broadcom/cygnus/include/soc/ns16550.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2000 Flying Pig Systems
- * Copyright (C) 2005 Wind River Systems
- * Copyright (C) 2009 DENX Software Engineering GmbH
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-
-struct ns16550 {
-	union {
-		uint32_t thr;	/* Transmit holding register. */
-		uint32_t rbr;	/* Receive buffer register. */
-		uint32_t dll;	/* Divisor latch lsb. */
-	};
-	union {
-		uint32_t ier;	/* Interrupt enable register. */
-		uint32_t dlm;	/* Divisor latch msb. */
-	};
-	union {
-		uint32_t iir;	/* Interrupt identification register. */
-		uint32_t fcr;	/* FIFO control register. */
-	};
-	uint32_t lcr;		/* 3 */
-	uint32_t mcr;		/* 4 */
-	uint32_t lsr;		/* 5 */
-	uint32_t msr;		/* 6 */
-	uint32_t spr;		/* 7 */
-	uint32_t mdr1;		/* 8 */
-	uint32_t reg9;		/* 9 */
-	uint32_t regA;		/* A */
-	uint32_t regB;		/* B */
-	uint32_t regC;		/* C */
-	uint32_t regD;		/* D */
-	uint32_t regE;		/* E */
-	uint32_t uasr;		/* F */
-	uint32_t scr;		/* 10*/
-	uint32_t ssr;		/* 11*/
-	uint32_t reg12;		/* 12*/
-	uint32_t osc_12m_sel;	/* 13*/
-};
-
-/*
- * These are the definitions for the FIFO Control Register
- */
-#define UART_FCR_FIFO_EN	0x01 /* Fifo enable */
-#define UART_FCR_CLEAR_RCVR	0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT	0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT	0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK	0xC0 /* Mask for the FIFO trigger range */
-#define UART_FCR_TRIGGER_1	0x00 /* Mask for trigger set at 1 */
-#define UART_FCR_TRIGGER_4	0x40 /* Mask for trigger set at 4 */
-#define UART_FCR_TRIGGER_8	0x80 /* Mask for trigger set at 8 */
-#define UART_FCR_TRIGGER_14	0xC0 /* Mask for trigger set at 14 */
-
-#define UART_FCR_RXSR		0x02 /* Receiver soft reset */
-#define UART_FCR_TXSR		0x04 /* Transmitter soft reset */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_DTR	0x01		/* DTR   */
-#define UART_MCR_RTS	0x02		/* RTS   */
-#define UART_MCR_OUT1	0x04		/* Out 1 */
-#define UART_MCR_OUT2	0x08		/* Out 2 */
-#define UART_MCR_LOOP	0x10		/* Enable loopback test mode */
-
-#define UART_MCR_DMA_EN	0x04
-#define UART_MCR_TX_DFR	0x08
-
-/*
- * These are the definitions for the Line Control Register
- *
- * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
- * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
- */
-#define UART_LCR_WLS_MSK 0x03		/* character length select mask */
-#define UART_LCR_WLS_5	0x00		/* 5 bit character length */
-#define UART_LCR_WLS_6	0x01		/* 6 bit character length */
-#define UART_LCR_WLS_7	0x02		/* 7 bit character length */
-#define UART_LCR_WLS_8	0x03		/* 8 bit character length */
-#define UART_LCR_STB	0x04		/* # stop Bits, off=1, on=1.5 or 2) */
-#define UART_LCR_PEN	0x08		/* Parity eneble */
-#define UART_LCR_EPS	0x10		/* Even Parity Select */
-#define UART_LCR_STKP	0x20		/* Stick Parity */
-#define UART_LCR_SBRK	0x40		/* Set Break */
-#define UART_LCR_BKSE	0x80		/* Bank select enable */
-#define UART_LCR_DLAB	0x80		/* Divisor latch access bit */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_DR	0x01		/* Data ready */
-#define UART_LSR_OE	0x02		/* Overrun */
-#define UART_LSR_PE	0x04		/* Parity error */
-#define UART_LSR_FE	0x08		/* Framing error */
-#define UART_LSR_BI	0x10		/* Break */
-#define UART_LSR_THRE	0x20		/* Xmit holding register empty */
-#define UART_LSR_TEMT	0x40		/* Xmitter empty */
-#define UART_LSR_ERR	0x80		/* Error */
-
-#define UART_MSR_DCD	0x80		/* Data Carrier Detect */
-#define UART_MSR_RI	0x40		/* Ring Indicator */
-#define UART_MSR_DSR	0x20		/* Data Set Ready */
-#define UART_MSR_CTS	0x10		/* Clear to Send */
-#define UART_MSR_DDCD	0x08		/* Delta DCD */
-#define UART_MSR_TERI	0x04		/* Trailing edge ring indicator */
-#define UART_MSR_DDSR	0x02		/* Delta DSR */
-#define UART_MSR_DCTS	0x01		/* Delta CTS */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT	0x01	/* No interrupts pending */
-#define UART_IIR_ID	0x06	/* Mask for the interrupt ID */
-
-#define UART_IIR_MSI	0x00	/* Modem status interrupt */
-#define UART_IIR_THRI	0x02	/* Transmitter holding register empty */
-#define UART_IIR_RDI	0x04	/* Receiver data interrupt */
-#define UART_IIR_RLSI	0x06	/* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI	0x08	/* Enable Modem status interrupt */
-#define UART_IER_RLSI	0x04	/* Enable receiver line status interrupt */
-#define UART_IER_THRI	0x02	/* Enable Transmitter holding register int. */
-#define UART_IER_RDI	0x01	/* Enable receiver data interrupt */
-
-/* useful defaults for LCR: 8 data, 1 stop, no parity */
-#define UART_LCR_8N1	0x03
diff --git a/src/soc/broadcom/cygnus/include/soc/reg_utils.h b/src/soc/broadcom/cygnus/include/soc/reg_utils.h
deleted file mode 100644
index e276613..0000000
--- a/src/soc/broadcom/cygnus/include/soc/reg_utils.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_REG_UTILS__
-#define __SOC_BROADCOM_CYGNUS_REG_UTILS__
-
-/* ---- Include Files ---------------------------------------------------- */
-
-#include <stdint.h>
-
-/* ---- Public Constants and Types --------------------------------------- */
-
-#define __REG32(x)      (*((volatile uint32_t *)(x)))
-#define __REG16(x)      (*((volatile uint16_t *)(x)))
-#define __REG8(x)       (*((volatile uint8_t *) (x)))
-
-/* ---- Public Variable Externs ------------------------------------------ */
-/* ---- Public Function Prototypes --------------------------------------- */
-
-/****************************************************************************/
-/*
- *   32-bit register access functions
- */
-/****************************************************************************/
-
-extern uint32_t reg_debug;
-#define	REG_DEBUG(val) (reg_debug = val)
-
-static inline void
-reg32_clear_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & ~(value)));
-#endif
-	*reg &= ~(value);
-}
-
-static inline void
-reg32_set_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg | value));
-#endif
-	*reg |= value;
-}
-
-static inline void
-reg32_toggle_bits(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg ^ value));
-#endif
-	*reg ^= value;
-}
-
-static inline void
-reg32_write_masked(volatile uint32_t *reg, uint32_t mask, uint32_t value)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x): 0x%x 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg, (*reg & (~mask)) | (value & mask));
-#endif
-	*reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void reg32_write(volatile uint32_t *reg, uint32_t value)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x, 0x%x)\n", __FUNCTION__, (uint32_t)reg, value);
-#endif
-	*reg = value;
-}
-
-static inline uint32_t
-reg32_read(volatile uint32_t *reg)
-{
-#ifdef DEBUG_REG
-	if (reg_debug)
-		printf("%s reg (0x%x): 0x%x\n", __FUNCTION__, (uint32_t)reg, *reg);
-#endif
-	return *reg;
-}
-
-/****************************************************************************/
-/*
- *   16-bit register access functions
- */
-/****************************************************************************/
-
-static inline void
-reg16_clear_bits(volatile uint16_t *reg, uint16_t value)
-{
-	*reg &= ~(value);
-}
-
-static inline void
-reg16_set_bits(volatile uint16_t *reg, uint16_t value)
-{
-	*reg |= value;
-}
-
-static inline void
-reg16_toggle_bits(volatile uint16_t *reg, uint16_t value)
-{
-	*reg ^= value;
-}
-
-static inline void
-reg16_write_masked(volatile uint16_t *reg, uint16_t mask, uint16_t value)
-{
-	*reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void
-reg16_write(volatile uint16_t *reg, uint16_t value)
-{
-	*reg = value;
-}
-
-static inline uint16_t
-reg16_read(volatile uint16_t *reg)
-{
-	return *reg;
-}
-
-/****************************************************************************/
-/*
- *   8-bit register access functions
- */
-/****************************************************************************/
-
-static inline void
-reg8_clear_bits(volatile uint8_t *reg, uint8_t value)
-{
-	*reg &= ~(value);
-}
-
-static inline void
-reg8_set_bits(volatile uint8_t *reg, uint8_t value)
-{
-	*reg |= value;
-}
-
-static inline void
-reg8_toggle_bits(volatile uint8_t *reg, uint8_t value)
-{
-	*reg ^= value;
-}
-
-static inline void
-reg8_write_masked(volatile uint8_t *reg, uint8_t mask, uint8_t value)
-{
-	*reg = (*reg & (~mask)) | (value & mask);
-}
-
-static inline void
-reg8_write(volatile uint8_t *reg, uint8_t value)
-{
-	*reg = value;
-}
-
-static inline uint8_t
-reg8_read(volatile uint8_t *reg)
-{
-	return *reg;
-}
-#endif /* __SOC_BROADCOM_CYGNUS_REG_UTILS__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/sdram.h b/src/soc/broadcom/cygnus/include/soc/sdram.h
deleted file mode 100644
index 18a4b64..0000000
--- a/src/soc/broadcom/cygnus/include/soc/sdram.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SOC_BROADCOM_CYGNUS_SDRAM_H__
-#define __SOC_BROADCOM_CYGNUS_SDRAM_H__
-
-#include <stdint.h>
-
-void ddr_init2(void);
-void sdram_init(void);
-uint32_t sdram_size_mb(void);
-
-#endif	/* __SOC_BROADCOM_CYGNUS_SDRAM_H__ */
diff --git a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h b/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
deleted file mode 100644
index 7e233fa..0000000
--- a/src/soc/broadcom/cygnus/include/soc/shmoo_and28/phy_and28_e2.h
+++ /dev/null
@@ -1,11271 +0,0 @@
-/*
-* Copyright (C) 2015 Broadcom Corporation
-*
-* This program is free software; you can redistribute it and/or
-* modify it under the terms of the GNU General Public License as
-* published by the Free Software Foundation version 2.
-*
-* This program is distributed "as is" WITHOUT ANY WARRANTY of any
-* kind, whether express or implied; without even the implied warranty
-* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-* GNU General Public License for more details.
-*/
-
-#ifndef __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__
-#define __SOC_BROADCOM_CYGNUS_PHY_AND28_E2_H__
-
-/**
- * m = memory, c = core, r = register, f = field, d = data.
- */
-#if !defined(GET_FIELD) && !defined(SET_FIELD)
-#define BRCM_ALIGN(c, r, f)   c##_##r##_##f##_ALIGN
-#define BRCM_BITS(c, r, f)    c##_##r##_##f##_BITS
-#define BRCM_MASK(c, r, f)    c##_##r##_##f##_MASK
-#define BRCM_SHIFT(c, r, f)   c##_##r##_##f##_SHIFT
-
-#define GET_FIELD(m, c, r, f) \
-	((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f))
-
-#define SET_FIELD(m, c, r, f, d) \
-	((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \
-	 BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \
-	)
-
-#define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d)
-#define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)
-#define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d)
-
-#endif /* GET & SET */
-
-/***************************************************************************
- *DDR34_CORE_PHY_CONTROL_REGS - DDR34 CORE DDR34 Address/Command control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION     0x00000000 /* Address & Control revision register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS   0x00000004 /* PHY PLL status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG   0x00000008 /* PHY PLL configuration register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1 0x0000000c /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2 0x00000010 /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3 0x00000014 /* PHY PLL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS 0x00000018 /* PHY PLL integer divider register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER 0x0000001c /* PHY PLL fractional divider register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL 0x00000020 /* PHY PLL spread spectrum control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT 0x00000024 /* PHY PLL spread spectrum limit register */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL  0x00000028 /* Aux Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x0000002c /* Idle mode pad control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0 0x00000030 /* Idle mode pad enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1 0x00000034 /* Idle mode pad enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x00000038 /* PVT Compensation control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL 0x0000003c /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG  0x00000040 /* DRAM configuration register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1 0x00000044 /* DRAM timing register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2 0x00000048 /* DRAM timing register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3 0x0000004c /* DRAM timing register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4 0x00000050 /* DRAM timing register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE 0x00000060 /* PHY VDL calibration control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1 0x00000064 /* PHY VDL calibration status register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2 0x00000068 /* PHY VDL calibration status register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL 0x0000006c /* PHY VDL delay monitoring control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF 0x00000070 /* PHY VDL delay monitoring reference register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS 0x00000074 /* PHY VDL delay monitoring status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE 0x00000078 /* PHY VDL delay monitoring override register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL 0x0000007c /* PHY VDL delay monitoring output control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS 0x00000080 /* PHY VDL delay monitoring output status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR 0x00000084 /* PHY VDL delay monitoring output status clear register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00 0x00000090 /* DDR interface signal AD[00] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01 0x00000094 /* DDR interface signal AD[01] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02 0x00000098 /* DDR interface signal AD[02] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03 0x0000009c /* DDR interface signal AD[03] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04 0x000000a0 /* DDR interface signal AD[04] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05 0x000000a4 /* DDR interface signal AD[05] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06 0x000000a8 /* DDR interface signal AD[06] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07 0x000000ac /* DDR interface signal AD[07] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08 0x000000b0 /* DDR interface signal AD[08] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09 0x000000b4 /* DDR interface signal AD[09] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10 0x000000b8 /* DDR interface signal AD[10] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11 0x000000bc /* DDR interface signal AD[11] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12 0x000000c0 /* DDR interface signal AD[12] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13 0x000000c4 /* DDR interface signal AD[13] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14 0x000000c8 /* DDR interface signal AD[14] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15 0x000000cc /* DDR interface signal AD[15] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0 0x000000d0 /* DDR interface signal BA[0] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1 0x000000d4 /* DDR interface signal BA[1] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2 0x000000d8 /* DDR interface signal BA[2] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0 0x000000dc /* DDR interface signal AUX[0] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1 0x000000e0 /* DDR interface signal AUX[1] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2 0x000000e4 /* DDR interface signal AUX[2] VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0 0x000000e8 /* DDR interface signal CS0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1 0x000000ec /* DDR interface signal CS1 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR 0x000000f0 /* DDR interface signal PAR VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N 0x000000f4 /* DDR interface signal RAS_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N 0x000000f8 /* DDR interface signal CAS_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE 0x000000fc /* DDR interface signal CKE0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N 0x00000100 /* DDR interface signal RST_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT 0x00000104 /* DDR interface signal ODT0 VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N 0x00000108 /* DDR interface signal WE_N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P 0x0000010c /* DDR interface signal DDR_CK-P VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N 0x00000110 /* DDR interface signal DDR_CK-N VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL 0x00000114 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL 0x00000118 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH      0x00000130 /* Refresh engine controller */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL   0x00000134 /* Update VDL control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1 0x00000138 /* Update VDL snoop control register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2 0x0000013c /* Update VDL snoop control register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1 0x00000140 /* DRAM Command Register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1 0x00000144 /* DRAM AUX_N Command Register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2 0x00000148 /* DRAM Command Register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2 0x0000014c /* DRAM AUX_N Command Register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3 0x00000150 /* DRAM Command Register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3 0x00000154 /* DRAM AUX_N Command Register #3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4 0x00000158 /* DRAM Command Register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4 0x0000015c /* DRAM AUX_N Command Register #4 */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER 0x00000160 /* DRAM Command Timer Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0    0x00000164 /* DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1    0x00000168 /* DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2    0x0000016c /* DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3    0x00000170 /* DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4    0x00000174 /* DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5    0x00000178 /* DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6    0x0000017c /* DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7    0x00000180 /* DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8    0x00000184 /* GDDR5 Mode Register 8 and LPDDR Mode Register 42 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15   0x00000188 /* GDDR5 Mode Register 15 and LPDDR Mode Register 48 */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63   0x0000018c /* LPDDR Mode Register 63 */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR  0x00000190 /* DDR4 Alert status clear register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS 0x00000194 /* DDR4 Alert status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY    0x00000198 /* DDR4 CA parity control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL 0x0000019c /* GDDR5 CA playback control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0 0x000001a0 /* LPDDR3 and GDDR5 CA playback status register0 */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL 0x000001ac /* Write leveling control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS 0x000001b0 /* Write leveling status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL 0x000001b4 /* Read enable test cycle control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS 0x000001b8 /* Read enable test cycle status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED 0x000001c0 /* Traffic generator seed register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1 0x000001c4 /* Traffic generator address register #1 */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2 0x000001c8 /* Traffic generator address register #2 */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL 0x000001cc /* Traffic generator control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL 0x000001d0 /* Traffic generator data control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK 0x000001d4 /* Traffic generator DQ mask register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK 0x000001d8 /* Traffic generator ECC DQ mask register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS 0x000001dc /* Traffic generator status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS 0x000001e0 /* Traffic generator DQ status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS 0x000001e4 /* Traffic generator ECC DQ status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL 0x000001e8 /* Traffic generator error count control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS 0x000001ec /* Traffic generator error count status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL 0x000001f0 /* Virtual VTT Control and Status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS 0x000001f4 /* Virtual VTT Control and Status register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS 0x000001f8 /* Virtual VTT Connections register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE 0x000001fc /* Virtual VTT Override register */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL 0x00000200 /* VREF DAC Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL 0x00000204 /* PhyBist Control Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED 0x00000208 /* PhyBist Seed Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK 0x0000020c /* PhyBist Command/Address Bus Mask */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS 0x00000210 /* PhyBist General Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS 0x00000214 /* PhyBist Per-Bit Control Pad Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS 0x00000218 /* PhyBist Byte Lane #0 Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS 0x0000021c /* PhyBist Byte Lane #1 Status Register */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL 0x00000230 /* Standby Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE 0x00000234 /* Freeze-on-error enable register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_MUX_CONTROL 0x00000238 /* Debug Mux Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_DFI_CNTRL    0x0000023c /* DFI Interface Ownership Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_ODT_CNTRL 0x00000240 /* Write ODT Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ABI_PAR_CNTRL 0x00000244 /* ABI and PAR Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_ZQ_CAL       0x00000248 /* ZQ Calibration Control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_CTL 0x0000024c /* Ring-Osc control register */
-#define DDR34_CORE_PHY_CONTROL_REGS_RO_PROC_MON_STATUS 0x00000250 /* Ring-Osc count register */
-#define DDR34_CORE_PHY_CONTROL_REGS_AC_SPARE_REG 0x0000011c /* Address and Control Spare register */
-
-/***************************************************************************
- *DDR34_CORE_PHY_BYTE_LANE_0 - DDR34 CORE DDR34 Byte Lane #0 control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_P 0x00000400 /* Write channel DQS-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQS_N 0x00000404 /* Write channel DQS-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ0 0x00000408 /* Write channel DQ0 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ1 0x0000040c /* Write channel DQ1 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ2 0x00000410 /* Write channel DQ2 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ3 0x00000414 /* Write channel DQ3 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ4 0x00000418 /* Write channel DQ4 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ5 0x0000041c /* Write channel DQ5 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ6 0x00000420 /* Write channel DQ6 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DQ7 0x00000424 /* Write channel DQ7 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_DM 0x00000428 /* Write channel DM VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_WR_EDC 0x0000042c /* Write channel EDC VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSP 0x00000430 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQSN 0x00000434 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0P 0x00000438 /* Read channel DQ0-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ0N 0x0000043c /* Read channel DQ0-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1P 0x00000440 /* Read channel DQ1-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ1N 0x00000444 /* Read channel DQ1-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2P 0x00000448 /* Read channel DQ2-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ2N 0x0000044c /* Read channel DQ2-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3P 0x00000450 /* Read channel DQ3-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ3N 0x00000454 /* Read channel DQ3-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4P 0x00000458 /* Read channel DQ4-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ4N 0x0000045c /* Read channel DQ4-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5P 0x00000460 /* Read channel DQ5-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ5N 0x00000464 /* Read channel DQ5-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6P 0x00000468 /* Read channel DQ6-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ6N 0x0000046c /* Read channel DQ6-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7P 0x00000470 /* Read channel DQ7-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DQ7N 0x00000474 /* Read channel DQ7-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMP 0x00000478 /* Read channel DM-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_DMN 0x0000047c /* Read channel DM-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCP 0x00000480 /* Read channel EDC-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EDCN 0x00000484 /* Read channel EDC-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS0 0x00000488 /* Read channel CS_N[0] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CONTROL_RD_EN_CS1 0x0000048c /* Read channel CS_N[1] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_CLK_CONTROL 0x00000490 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_VDL_LDE_CONTROL 0x00000494 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DLY_CYC 0x000004a0 /* Read enable bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_CHAN_DLY_CYC 0x000004a4 /* Write leveling bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_CONTROL  0x000004b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_ADDR 0x000004b4 /* Read fifo address pointer register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DATA 0x000004b8 /* Read fifo data register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_DM_DBI 0x000004bc /* Read fifo dm/dbi register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x000004c0 /* Read fifo status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x000004c4 /* Read fifo status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x000004c8 /* Idle mode SSTL pad control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x000004cc /* SSTL pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_RD_EN_DRIVE_PAD_CTL 0x000004d0 /* SSTL read enable pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_STATIC_PAD_CTL 0x000004d4 /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x000004d8 /* Write cycle preamble control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_ODT_CONTROL   0x000004e0 /* Read channel ODT control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_CONTROL 0x000004f0 /* GDDR5M EDC digital phase detector control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_STATUS 0x000004f4 /* GDDR5M EDC digital phase detector status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_CONTROL 0x000004f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS 0x000004fc /* GDDR5M EDC digital phase detector output signal status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_DPD_OUT_STATUS_CLEAR 0x00000500 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_CONTROL 0x00000504 /* GDDR5M EDC signal path CRC control register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS 0x00000508 /* GDDR5M EDC signal path CRC status register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_COUNT 0x0000050c /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_EDC_CRC_STATUS_CLEAR 0x00000510 /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_0_BL_SPARE_REG  0x00000514 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *DDR34_CORE_PHY_BYTE_LANE_1 - DDR34 CORE DDR34 Byte Lane #1 control registers
- ***************************************************************************/
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_P 0x00000600 /* Write channel DQS-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQS_N 0x00000604 /* Write channel DQS-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ0 0x00000608 /* Write channel DQ0 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ1 0x0000060c /* Write channel DQ1 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ2 0x00000610 /* Write channel DQ2 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ3 0x00000614 /* Write channel DQ3 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ4 0x00000618 /* Write channel DQ4 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ5 0x0000061c /* Write channel DQ5 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ6 0x00000620 /* Write channel DQ6 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DQ7 0x00000624 /* Write channel DQ7 VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_DM 0x00000628 /* Write channel DM VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_WR_EDC 0x0000062c /* Write channel EDC VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSP 0x00000630 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQSN 0x00000634 /* Read channel DQSP VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0P 0x00000638 /* Read channel DQ0-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ0N 0x0000063c /* Read channel DQ0-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1P 0x00000640 /* Read channel DQ1-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ1N 0x00000644 /* Read channel DQ1-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2P 0x00000648 /* Read channel DQ2-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ2N 0x0000064c /* Read channel DQ2-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3P 0x00000650 /* Read channel DQ3-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ3N 0x00000654 /* Read channel DQ3-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4P 0x00000658 /* Read channel DQ4-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ4N 0x0000065c /* Read channel DQ4-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5P 0x00000660 /* Read channel DQ5-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ5N 0x00000664 /* Read channel DQ5-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6P 0x00000668 /* Read channel DQ6-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ6N 0x0000066c /* Read channel DQ6-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7P 0x00000670 /* Read channel DQ7-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DQ7N 0x00000674 /* Read channel DQ7-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMP 0x00000678 /* Read channel DM-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_DMN 0x0000067c /* Read channel DM-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCP 0x00000680 /* Read channel EDC-P VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EDCN 0x00000684 /* Read channel EDC-N VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS0 0x00000688 /* Read channel CS_N[0] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CONTROL_RD_EN_CS1 0x0000068c /* Read channel CS_N[1] read enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_CLK_CONTROL 0x00000690 /* DDR interface signal Write Leveling CLK VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_VDL_LDE_CONTROL 0x00000694 /* DDR interface signal Write Leveling Capture Enable VDL control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DLY_CYC 0x000006a0 /* Read enable bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_CHAN_DLY_CYC 0x000006a4 /* Write leveling bit-clock cycle delay control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_CONTROL  0x000006b0 /* Read channel datapath control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_ADDR 0x000006b4 /* Read fifo address pointer register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DATA 0x000006b8 /* Read fifo data register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_DM_DBI 0x000006bc /* Read fifo dm/dbi register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x000006c0 /* Read fifo status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x000006c4 /* Read fifo status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x000006c8 /* Idle mode SSTL pad control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x000006cc /* SSTL pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_RD_EN_DRIVE_PAD_CTL 0x000006d0 /* SSTL read enable pad drive characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_STATIC_PAD_CTL 0x000006d4 /* pad rx and tx characteristics control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x000006d8 /* Write cycle preamble control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_ODT_CONTROL   0x000006e0 /* Read channel ODT control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_CONTROL 0x000006f0 /* GDDR5M EDC digital phase detector control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_STATUS 0x000006f4 /* GDDR5M EDC digital phase detector status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_CONTROL 0x000006f8 /* GDDR5M EDC digital phase detector output signal control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS 0x000006fc /* GDDR5M EDC digital phase detector output signal status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_DPD_OUT_STATUS_CLEAR 0x00000700 /* GDDR5M EDC digital phase detector output signal status clear register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_CONTROL 0x00000704 /* GDDR5M EDC signal path CRC control register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS 0x00000708 /* GDDR5M EDC signal path CRC status register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_COUNT 0x0000070c /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_EDC_CRC_STATUS_CLEAR 0x00000710 /* GDDR5M EDC signal path CRC counter register */
-#define DDR34_CORE_PHY_BYTE_LANE_1_BL_SPARE_REG  0x00000714 /* Byte-Lane Spare register */
-
-/***************************************************************************
- *REVISION - Address & Control revision register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_MASK        0xfe000000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_ALIGN       0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_BITS        7
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_reserved0_SHIFT       25
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: PERFORMANCE [24:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_MASK      0x01800000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_PERFORMANCE_SHIFT     23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: TECHNOLOGY [22:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_MASK       0x00700000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_BITS       3
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_TECHNOLOGY_SHIFT      20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: WB [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_MASK               0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_ALIGN              0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_BITS               1
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_WB_SHIFT              19
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: BITS [18:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_MASK             0x00070000
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_ALIGN            0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_BITS             3
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_BITS_SHIFT            16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_MASK            0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_ALIGN           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_BITS            8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT           8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MAJOR_DEFAULT         0x000000e2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_MASK            0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_ALIGN           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_BITS            8
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REVISION_MINOR_DEFAULT         0x00000001
-
-/***************************************************************************
- *PLL_STATUS - PHY PLL status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_MASK      0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_BITS      8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved0_SHIFT     24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCK_GEN [23:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_MASK      0x00f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_BITS      4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_SHIFT     20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCK_GEN_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: reserved1 [19:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_MASK      0x000e0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_BITS      3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_reserved1_SHIFT     17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK_LOST [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_MASK      0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_LOST_SHIFT     16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_8X [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_MASK    0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_8X_SHIFT   15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_4X [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_MASK    0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_4X_SHIFT   14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: CLOCKING_2X [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_MASK    0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_CLOCKING_2X_SHIFT   13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: STATUS [12:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_MASK         0x00001ffe
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_BITS         12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_STATUS_SHIFT        1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK           0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT          0
-
-/***************************************************************************
- *PLL_CONFIG - PHY PLL configuration register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_MASK      0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_BITS      4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_SHIFT     28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved_for_eco1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_SHIFT 27
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_REF_CTRL [26:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_MASK 0x06000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: CK_LDO_BIAS [24:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_MASK    0x01800000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_SHIFT   23
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_CK_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_SEL [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_REF_CTRL [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_MASK 0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_REF_CTRL_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PLL_LDO_BIAS [19:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_MASK   0x000c0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_BITS   2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_SHIFT  18
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PLL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: HOLD [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_MASK           0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_SHIFT          17
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_HOLD_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: ENABLE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_MASK         0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_BITS         1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_SHIFT        16
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_ENABLE_DEFAULT      0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved2 [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_MASK      0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_SHIFT     14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: FB_OFFSET [13:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_MASK      0x00003f00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_BITS      6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_SHIFT     8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_FB_OFFSET_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved3 [07:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_MASK      0x000000e0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_BITS      3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved3_SHIFT     5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET_POST_DIV [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved4 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_MASK      0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_reserved4_SHIFT     2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: RESET [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_MASK          0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_SHIFT         1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_RESET_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK          0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT         0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_DEFAULT       0x00000000
-
-/***************************************************************************
- *PLL_CONTROL1 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_MASK    0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_BITS    22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_reserved0_SHIFT   10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KP [09:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_MASK         0x000003c0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_BITS         4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_SHIFT        6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KP_DEFAULT      0x00000005
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KI [05:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_MASK         0x00000038
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_BITS         3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_SHIFT        3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KI_DEFAULT      0x00000002
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL1 :: I_KA [02:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_MASK         0x00000007
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_BITS         3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL1_I_KA_DEFAULT      0x00000000
-
-/***************************************************************************
- *PLL_CONTROL2 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_RANGE [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_MASK    0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_SHIFT   30
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_RANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED2 [29:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_MASK      0x20000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_SHIFT     29
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED2_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: NDIV_RELOCK [28:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_MASK  0x10000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_NDIV_RELOCK_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: FAST_LOCK [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_MASK    0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_SHIFT   27
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_FAST_LOCK_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: VCO_FB_DIV2 [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_MASK  0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_VCO_FB_DIV2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: POST_CTRL_RESETB [25:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_MASK 0x03000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_POST_CTRL_RESETB_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PWM_RATE [23:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_MASK     0x00c00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_BITS     2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_SHIFT    22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_PWM_RATE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_MODE [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_MASK    0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_SHIFT   20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: UNUSED1 [19:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_MASK      0x000c0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_SHIFT     18
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_UNUSED1_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_UPDATE [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_MASK  0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_SELECT [16:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_MASK  0x0001c000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_BITS  3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_SELECT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: STAT_RESET [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_MASK   0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_SHIFT  13
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_STAT_RESET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS_ENABLE [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL2 :: DCO_CTRL_BYPASS [11:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_MASK 0x00000fff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL2_DCO_CTRL_BYPASS_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_CONTROL3 - PHY PLL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_CONTROL3 :: PLL_CONTROL [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_MASK  0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_BITS  32
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_CONTROL3_PLL_CONTROL_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_DIVIDERS - PHY PLL integer divider register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_MASK    0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_BITS    4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved0_SHIFT   28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: MDIV [27:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_MASK         0x0ff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_SHIFT        20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_MDIV_DEFAULT      0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved1 [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_MASK    0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_BITS    4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved1_SHIFT   16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: PDIV [15:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_MASK         0x0000f000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_BITS         4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_SHIFT        12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_PDIV_DEFAULT      0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: reserved2 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_MASK    0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_reserved2_SHIFT   10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_DIVIDERS :: NDIV_INT [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_MASK     0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_BITS     10
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_SHIFT    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_DIVIDERS_NDIV_INT_DEFAULT  0x00000020
-
-/***************************************************************************
- *PLL_FRAC_DIVIDER - PHY PLL fractional divider register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_FRAC_DIVIDER :: NDIV_FRAC [19:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_MASK 0x000fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_FRAC_DIVIDER_NDIV_FRAC_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_CONTROL - PHY PLL spread spectrum control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_MASK  0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_BITS  12
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_STEP [19:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_MASK   0x000ffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_BITS   16
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_SHIFT  4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_STEP_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_MASK  0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_BITS  3
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_CONTROL :: SSC_MODE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_MASK   0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_SHIFT  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_CONTROL_SSC_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *PLL_SS_LIMIT - PHY PLL spread spectrum limit register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved0 [31:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_MASK    0xfc000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_BITS    6
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved0_SHIFT   26
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: SSC_LIMIT [25:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_MASK    0x03fffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_BITS    22
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_SHIFT   4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_SSC_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PLL_SS_LIMIT :: reserved1 [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_MASK    0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_BITS    4
-#define DDR34_CORE_PHY_CONTROL_REGS_PLL_SS_LIMIT_reserved1_SHIFT   0
-
-/***************************************************************************
- *AUX_CONTROL - Aux Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved0 [31:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_MASK     0xffe00000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_BITS     11
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved0_SHIFT    21
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_ODT [20:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_MASK        0x001f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_ALIGN       0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_BITS        5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_SHIFT       16
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_ODT_DEFAULT     0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_MASK     0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_BITS     3
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved1_SHIFT    13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_CS [12:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_MASK         0x00001f00
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_BITS         5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_SHIFT        8
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_CS_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: reserved2 [07:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_MASK     0x000000e0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_BITS     3
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_reserved2_SHIFT    5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: AUX_CONTROL :: IS_AD [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_MASK         0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_BITS         5
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_AUX_CONTROL_IS_AD_DEFAULT      0x00000000
-
-/***************************************************************************
- *IDLE_PAD_CONTROL - Idle mode pad control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDLE [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDLE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DIB_MODE [30:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_MASK 0x40000000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_SHIFT 30
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DIB_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [29:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_MASK 0x3ffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_BITS 26
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: RXENB [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_MASK    0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_SHIFT   3
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: IDDQ [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_MASK     0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_SHIFT    2
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_IDDQ_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_MASK   0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_SHIFT  1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_MASK   0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_SHIFT  0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE0 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: reserved0 [31:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_MASK 0xfffff800
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_BITS 21
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_reserved0_SHIFT 11
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE0 :: IO_IDLE_ENABLE [10:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_MASK 0x000007ff
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_BITS 11
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE0_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *IDLE_PAD_ENABLE1 - Idle mode pad enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: IDLE_PAD_ENABLE1 :: IO_IDLE_ENABLE [21:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_MASK 0x003fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_IDLE_PAD_ENABLE1_IO_IDLE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRIVE_PAD_CTL - PVT Compensation control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK   0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_BITS   2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT  30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_IDLE_STRENGTH [29:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_MASK 0x3e000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_IDLE_STRENGTH [24:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_MASK 0x01f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_IDLE_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_TERM_STRENGTH [19:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_MASK 0x000f8000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_SHIFT 15
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_TERM_STRENGTH [14:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_MASK 0x00007c00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_TERM_STRENGTH_DEFAULT 0x00000006
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_PD_STRENGTH [09:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_MASK 0x000003e0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_PD_STRENGTH_DEFAULT 0x0000001f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: ADDR_CTL_ND_STRENGTH [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_MASK 0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRIVE_PAD_CTL_ADDR_CTL_ND_STRENGTH_DEFAULT 0x0000001f
-
-/***************************************************************************
- *STATIC_PAD_CTL - pad rx and tx characteristics control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved0 [31:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_MASK  0xf0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_BITS  4
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved0_SHIFT 28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: AUTO_OEB [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_MASK   0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_SHIFT  27
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_AUTO_OEB_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_GDDR5 [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_MASK 0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_GDDR5_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_LPDDR [25:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_MASK 0x02000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_SHIFT 25
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_LPDDR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK1 [24:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_MASK  0x01000000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CLK0 [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_MASK  0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_SHIFT 23
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CLK0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_ODT [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_MASK   0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_SHIFT  22
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_ODT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_PAR [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_MASK   0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_SHIFT  21
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_PAR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_BA [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_MASK    0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_SHIFT   20
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_BA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX2 [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_MASK  0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX1 [18:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_MASK  0x00040000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_AUX0 [17:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_MASK  0x00020000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_AUX0_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_CS1 [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_MASK   0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_SHIFT  16
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_CS1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A15 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_MASK   0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_SHIFT  15
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A15_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A14 [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_MASK   0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_SHIFT  14
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A14_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A13 [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_MASK   0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_SHIFT  13
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A13_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A12 [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A12_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A11 [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_MASK   0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_SHIFT  11
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A11_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A10 [10:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_MASK   0x00000400
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_SHIFT  10
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A10_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: IDDQ_A09 [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_MASK   0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_SHIFT  9
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_IDDQ_A09_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: reserved1 [08:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_MASK  0x000001fc
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_BITS  7
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_reserved1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STATIC_PAD_CTL :: RX_MODE [01:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_MASK    0x00000003
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_SHIFT   0
-#define DDR34_CORE_PHY_CONTROL_REGS_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000
-
-/***************************************************************************
- *DRAM_CONFIG - DRAM configuration register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: INIT_MODE [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_INIT_MODE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved0 [30:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_MASK     0x70000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_BITS     3
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved0_SHIFT    28
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: ECC_ENABLED [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_MASK   0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_SHIFT  27
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ECC_ENABLED_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: SPLIT_DQ_BUS [26:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_MASK  0x04000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_SHIFT 26
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_SPLIT_DQ_BUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS16 [25:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_MASK         0x02000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_BITS         1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_SHIFT        25
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS16_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BUS8 [24:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_MASK          0x01000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_SHIFT         24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BUS8_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: reserved1 [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_MASK     0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_BITS     8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_reserved1_SHIFT    16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: EDC_MODE [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_MASK      0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_SHIFT     15
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_EDC_MODE_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: RDQS_MODE [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_MASK     0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_SHIFT    14
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_RDQS_MODE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: GROUP_BITS [13:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_MASK    0x00003000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_GROUP_BITS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: BANK_BITS [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_MASK     0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_BITS     2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_SHIFT    10
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_BANK_BITS_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: COL_BITS [09:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_MASK      0x00000300
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_SHIFT     8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_COL_BITS_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: ROW_BITS [07:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_MASK      0x000000f0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_BITS      4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_SHIFT     4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_ROW_BITS_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_CONFIG :: DRAM_TYPE [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_MASK     0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_BITS     4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_SHIFT    0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_CONFIG_DRAM_TYPE_DEFAULT  0x00000000
-
-/***************************************************************************
- *DRAM_TIMING1 - DRAM timing register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRAS [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_MASK         0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_SHIFT        24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRAS_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRRD [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_MASK         0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_SHIFT        16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRRD_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRP [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_MASK          0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_BITS          8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_SHIFT         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRP_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING1 :: TRCD [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_MASK         0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING1_TRCD_DEFAULT      0x00000000
-
-/***************************************************************************
- *DRAM_TIMING2 - DRAM timing register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TRTP [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_MASK         0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_SHIFT        24
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TRTP_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TWR [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_MASK          0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_BITS          8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_SHIFT         16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TWR_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCWL [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_MASK         0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_SHIFT        8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCWL_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING2 :: TCAS [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_MASK         0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_BITS         8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING2_TCAS_DEFAULT      0x00000000
-
-/***************************************************************************
- *DRAM_TIMING3 - DRAM timing register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_MASK    0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_BITS    8
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_reserved0_SHIFT   24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TCAL [23:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_MASK         0x00f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_BITS         4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_SHIFT        20
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TCAL_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRTW [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_MASK         0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_BITS         4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_SHIFT        16
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRTW_DEFAULT      0x00000004
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TWTR [15:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_MASK         0x0000f000
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_BITS         4
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_SHIFT        12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TWTR_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING3 :: TRFC [11:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_MASK         0x00000fff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_BITS         12
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING3_TRFC_DEFAULT      0x00000000
-
-/***************************************************************************
- *DRAM_TIMING4 - DRAM timing register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DRAM_TIMING4 :: temp [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_MASK         0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_BITS         32
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_DRAM_TIMING4_temp_DEFAULT      0x00000000
-
-/***************************************************************************
- *VDL_CALIBRATE - PHY VDL calibration control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_MASK   0xffffffc0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_BITS   26
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_reserved0_SHIFT  6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: HALF_STEPS [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_MASK  0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_HALF_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_FAST [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_FAST_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: UPDATE_REGS [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_UPDATE_REGS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_FTM2 [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_MASK  0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_FTM2_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_PHYBIST [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_PHYBIST_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIBRATE :: CALIB_ONCE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_MASK  0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIBRATE_CALIB_ONCE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CALIB_STATUS1 - PHY VDL calibration status register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved0 [31:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_MASK 0xfffc0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved0_SHIFT 18
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_TOTAL_STEPS [17:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_MASK 0x0003ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_TOTAL_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: reserved1 [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_BUS_ERROR [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_REGS_DONE [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_REGS_DONE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_6B [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_6B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_4B [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_4B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_LOCK_2B [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_LOCK_2B_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS1 :: CALIB_IDLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS1_CALIB_IDLE_DEFAULT 0x00000001
-
-/***************************************************************************
- *VDL_CALIB_STATUS2 - PHY VDL calibration status register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_4B_STEPS [21:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_MASK 0x003ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: reserved1 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CALIB_STATUS2 :: CALIB_2B_STEPS [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CALIB_STATUS2_CALIB_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_CONTROL - PHY VDL delay monitoring control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: INTERVAL [21:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_MASK 0x003fff00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_INTERVAL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: reserved1 [07:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_MASK 0x000000f0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_reserved1_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: UPDATE [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_UPDATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: FORCE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: DATA_RATE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_DATA_RATE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_REF - PHY VDL delay monitoring reference register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_4B_STEPS [21:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_MASK 0x003ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_4B_STEPS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: reserved1 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_REF :: MONITOR_2B_STEPS [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_REF_MONITOR_2B_STEPS_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_STATUS - PHY VDL delay monitoring status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved0 [31:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_MASK 0xe0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved0_SHIFT 29
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_BUS_ERROR [28:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_MASK 0x10000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_BUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved1 [27:25] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_MASK 0x0e000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved1_SHIFT 25
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_ADJ [24:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_MASK 0x01f00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_ADJ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_CHANGE [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_MASK 0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: reserved2 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_MASK 0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_reserved2_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_STATUS :: MONITOR_TOTAL [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OVERRIDE - PHY VDL delay monitoring override register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved1 [15:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_MASK 0x0000fe00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_BITS 7
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved1_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ADJ [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_MASK  0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_BITS  5
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ADJ_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OVERRIDE :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OVERRIDE_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_CONTROL - PHY VDL delay monitoring output control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: LOWER_LIMIT [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: UPPER_LIMIT [11:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS - PHY VDL delay monitoring output status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved0 [31:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_MASK 0xff000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved0_SHIFT 24
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_CHANGE [23:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_MASK 0x00ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_CHANGE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved1 [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_MASK 0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved1_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: MONITOR_TOTAL [13:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_MASK 0x00003ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_MONITOR_TOTAL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_MONITOR_OUT_STATUS_CLEAR - PHY VDL delay monitoring output status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_MONITOR_OUT_STATUS_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_MONITOR_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD00 - DDR interface signal AD[00] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD00 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD00_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD01 - DDR interface signal AD[01] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD01 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD01_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD02 - DDR interface signal AD[02] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD02 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD02_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD03 - DDR interface signal AD[03] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD03 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD03_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD04 - DDR interface signal AD[04] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD04 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD04_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD05 - DDR interface signal AD[05] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD05 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD05_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD06 - DDR interface signal AD[06] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD06 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD06_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD07 - DDR interface signal AD[07] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD07 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD07_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD08 - DDR interface signal AD[08] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD08 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD08_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD09 - DDR interface signal AD[09] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD09 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD09_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD10 - DDR interface signal AD[10] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD10 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD10_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD11 - DDR interface signal AD[11] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD11 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD11_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD12 - DDR interface signal AD[12] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD12 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD12_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD13 - DDR interface signal AD[13] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD13 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD13_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD14 - DDR interface signal AD[14] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD14 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD14_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AD15 - DDR interface signal AD[15] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AD15 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AD15_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA0 - DDR interface signal BA[0] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA1 - DDR interface signal BA[1] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_BA2 - DDR interface signal BA[2] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_BA2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_BA2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX0 - DDR interface signal AUX[0] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX1 - DDR interface signal AUX[1] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_AUX2 - DDR interface signal AUX[2] VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_AUX2 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_AUX2_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS0 - DDR interface signal CS0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS0 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS0_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CS1 - DDR interface signal CS1 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CS1 :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CS1_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_PAR - DDR interface signal PAR VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_PAR :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_PAR_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RAS_N - DDR interface signal RAS_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_MASK    0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_SHIFT   31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_MASK   0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_SHIFT  16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_MASK  0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RAS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CAS_N - DDR interface signal CAS_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_MASK    0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_SHIFT   31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_MASK   0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_SHIFT  16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_MASK  0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CAS_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CAS_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_CKE - DDR interface signal CKE0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_CKE :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_CKE_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_RST_N - DDR interface signal RST_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_MASK    0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_SHIFT   31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_MASK   0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_SHIFT  16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_MASK  0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_RST_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_RST_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_ODT - DDR interface signal ODT0 VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_ODT :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_ODT_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_WE_N - DDR interface signal WE_N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_MASK     0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_SHIFT    31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_BUSY_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_MASK    0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_MASK   0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_WE_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_WE_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_P - DDR interface signal DDR_CK-P VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_P :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_P_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CONTROL_DDR_CK_N - DDR interface signal DDR_CK-N VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_BUSY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_MASK 0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_FORCE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CONTROL_DDR_CK_N :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_MASK 0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CONTROL_DDR_CK_N_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_CLK_CONTROL - DDR interface signal Write Leveling CLK VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *VDL_LDE_CONTROL - DDR interface signal Write Leveling Capture Enable VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: BUSY [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_MASK      0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_SHIFT     31
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_BUSY_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved0 [30:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_MASK 0x7ffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_BITS 14
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved0_SHIFT 17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: FORCE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_FORCE_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved1 [15:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_MASK 0x0000e000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved1_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: ADJ_EN [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_MASK    0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_SHIFT   12
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_ADJ_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: reserved2 [11:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_MASK 0x00000e00
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_reserved2_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VDL_LDE_CONTROL :: VDL_STEP [08:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_MASK  0x000001ff
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_BITS  9
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VDL_LDE_CONTROL_VDL_STEP_DEFAULT 0x00000000
-
-/***************************************************************************
- *REFRESH - Refresh engine controller
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_MASK         0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_BITS         15
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_reserved0_SHIFT        17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: ENABLE [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_MASK            0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_ALIGN           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_BITS            1
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_SHIFT           16
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_ENABLE_DEFAULT         0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: REFRESH :: PERIOD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_MASK            0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_ALIGN           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_BITS            16
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_SHIFT           0
-#define DDR34_CORE_PHY_CONTROL_REGS_REFRESH_PERIOD_DEFAULT         0x00000000
-
-/***************************************************************************
- *UPDATE_VDL - Update VDL control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved0 [31:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_MASK      0xffffffc0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_BITS      26
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved0_SHIFT     6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: MODE [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_MASK           0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_BITS           2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_SHIFT          4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_MODE_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: reserved1 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_MASK      0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_reserved1_SHIFT     2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: DISABLE_INPUT [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_MASK  0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_DISABLE_INPUT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_MASK         0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_BITS         1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_ENABLE_DEFAULT      0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP1 - Update VDL snoop control register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MODE [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_MASK    0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_SHIFT   28
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved1_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: MASK [26:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_MASK    0x07ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_BITS    11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_MASK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: CMD [14:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_MASK     0x00007ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_BITS     11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_SHIFT    4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_CMD_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: reserved3 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_reserved3_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP1 :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_MASK  0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP1_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *UPDATE_VDL_SNOOP2 - Update VDL snoop control register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_MASK 0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved0_SHIFT 30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MODE [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_MASK    0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_BITS    2
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_SHIFT   28
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MODE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_MASK 0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved1_SHIFT 27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: MASK [26:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_MASK    0x07ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_BITS    11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_SHIFT   16
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_MASK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved2 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_MASK 0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved2_SHIFT 15
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: CMD [14:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_MASK     0x00007ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_BITS     11
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_SHIFT    4
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_CMD_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: reserved3 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_reserved3_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: UPDATE_VDL_SNOOP2 :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_MASK  0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_UPDATE_VDL_SNOOP2_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *COMMAND_REG1 - DRAM Command Register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_MASK          0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_SHIFT         31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_MCP_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_MASK           0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_BITS           2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_SHIFT          29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CS_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_MASK          0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_BITS          5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_SHIFT         24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AUX_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_MASK          0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_SHIFT         23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_ACT_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_MASK           0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_SHIFT          22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_WE_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_MASK          0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_SHIFT         21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_CAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_MASK          0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_SHIFT         20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_RAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_MASK           0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_BITS           4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_BA_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG1 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_MASK           0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_BITS           16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_SHIFT          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG1_AD_DEFAULT        0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG1 - DRAM AUX_N Command Register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG1 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_MASK      0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_BITS      5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG1_AUX_DEFAULT   0x00000000
-
-/***************************************************************************
- *COMMAND_REG2 - DRAM Command Register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_MASK          0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_SHIFT         31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_MCP_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_MASK           0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_BITS           2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_SHIFT          29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CS_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_MASK          0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_BITS          5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_SHIFT         24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AUX_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_MASK          0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_SHIFT         23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_ACT_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_MASK           0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_SHIFT          22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_WE_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_MASK          0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_SHIFT         21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_CAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_MASK          0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_SHIFT         20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_RAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_MASK           0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_BITS           4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_BA_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG2 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_MASK           0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_BITS           16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_SHIFT          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG2_AD_DEFAULT        0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG2 - DRAM AUX_N Command Register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG2 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_MASK      0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_BITS      5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG2_AUX_DEFAULT   0x00000000
-
-/***************************************************************************
- *COMMAND_REG3 - DRAM Command Register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_MASK          0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_SHIFT         31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_MCP_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_MASK           0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_BITS           2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_SHIFT          29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CS_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_MASK          0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_BITS          5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_SHIFT         24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AUX_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_MASK          0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_SHIFT         23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_ACT_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_MASK           0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_SHIFT          22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_WE_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_MASK          0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_SHIFT         21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_CAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_MASK          0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_SHIFT         20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_RAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_MASK           0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_BITS           4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_BA_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG3 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_MASK           0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_BITS           16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_SHIFT          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG3_AD_DEFAULT        0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG3 - DRAM AUX_N Command Register #3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG3 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_MASK      0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_BITS      5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG3_AUX_DEFAULT   0x00000000
-
-/***************************************************************************
- *COMMAND_REG4 - DRAM Command Register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: MCP [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_MASK          0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_SHIFT         31
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_MCP_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: CS [30:29] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_MASK           0x60000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_BITS           2
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_SHIFT          29
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CS_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: AUX [28:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_MASK          0x1f000000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_BITS          5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_SHIFT         24
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AUX_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: ACT [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_MASK          0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_SHIFT         23
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_ACT_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: WE [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_MASK           0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_SHIFT          22
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_WE_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: CAS [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_MASK          0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_SHIFT         21
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_CAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: RAS [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_MASK          0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_SHIFT         20
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_RAS_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: BA [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_MASK           0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_BITS           4
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_BA_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG4 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_MASK           0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_BITS           16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_SHIFT          0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG4_AD_DEFAULT        0x00000000
-
-/***************************************************************************
- *COMMAND_AUX_REG4 - DRAM AUX_N Command Register #4
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_AUX_REG4 :: AUX [04:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_MASK      0x0000001f
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_BITS      5
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_AUX_REG4_AUX_DEFAULT   0x00000000
-
-/***************************************************************************
- *COMMAND_REG_TIMER - DRAM Command Timer Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: INIT_VAL [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_INIT_VAL_DEFAULT 0x0000000f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: COMMAND_REG_TIMER :: COUNT [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_MASK   0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_BITS   8
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_SHIFT  0
-#define DDR34_CORE_PHY_CONTROL_REGS_COMMAND_REG_TIMER_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *MODE_REG0 - DDR3/DDR4/GDDR5 Mode Register 0 and LPDDR Mode Register 1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG0 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG0_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG1 - DDR3/DDR4/GDDR5 Mode Register 1 and LPDDR Mode Register 2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG1 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG1_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG2 - DDR3/DDR4/GDDR5 Mode Register 2 and LPDDR Mode Register 3
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG2 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG2_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG3 - DDR3/DDR4/GDDR5 Mode Register 3 and LPDDR Mode Register 9
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG3 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG3_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG4 - DDR4/GDDR5 Mode Register 4 and LPDDR Mode Register 10
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG4 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG4_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG5 - DDR4/GDDR5 Mode Register 5 and LPDDR Mode Register 16
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG5 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG5_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG6 - DDR4/GDDR5 Mode Register 6 and LPDDR Mode Register 17
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG6 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG6_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG7 - DDR4/GDDR5 Mode Register 7 and LPDDR Mode Register 41
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG7 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG7_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG8 - GDDR5 Mode Register 8 and LPDDR Mode Register 42
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_MASK       0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_BITS       15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_reserved0_SHIFT      17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_MASK           0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_SHIFT          16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_VALID_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG8 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_MASK              0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_ALIGN             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_BITS              16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_SHIFT             0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG8_AD_DEFAULT           0x00000000
-
-/***************************************************************************
- *MODE_REG15 - GDDR5 Mode Register 15 and LPDDR Mode Register 48
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_MASK      0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_BITS      15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_reserved0_SHIFT     17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_MASK          0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_SHIFT         16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_VALID_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG15 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_MASK             0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_ALIGN            0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_BITS             16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_SHIFT            0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG15_AD_DEFAULT          0x00000000
-
-/***************************************************************************
- *MODE_REG63 - LPDDR Mode Register 63
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: reserved0 [31:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_MASK      0xfffe0000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_BITS      15
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_reserved0_SHIFT     17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: VALID [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_MASK          0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_SHIFT         16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_VALID_DEFAULT       0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: MODE_REG63 :: AD [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_MASK             0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_ALIGN            0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_BITS             16
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_SHIFT            0
-#define DDR34_CORE_PHY_CONTROL_REGS_MODE_REG63_AD_DEFAULT          0x00000000
-
-/***************************************************************************
- *ALERT_CLEAR - DDR4 Alert status clear register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_CLEAR :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_MASK     0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_BITS     31
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_reserved0_SHIFT    1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_CLEAR :: CLEAR [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_MASK         0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_BITS         1
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_CLEAR_CLEAR_DEFAULT      0x00000000
-
-/***************************************************************************
- *ALERT_STATUS - DDR4 Alert status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_STATUS :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_MASK    0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_BITS    31
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_reserved0_SHIFT   1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: ALERT_STATUS :: STATUS [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_MASK       0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_BITS       1
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_SHIFT      0
-#define DDR34_CORE_PHY_CONTROL_REGS_ALERT_STATUS_STATUS_DEFAULT    0x00000000
-
-/***************************************************************************
- *CA_PARITY - DDR4 CA parity control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: reserved0 [31:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_MASK       0xfffffffc
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_BITS       30
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_reserved0_SHIFT      2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: ERROR [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_MASK           0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_ALIGN          0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_BITS           1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_SHIFT          1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ERROR_DEFAULT        0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PARITY :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_MASK          0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_ALIGN         0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_BITS          1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_SHIFT         0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PARITY_ENABLE_DEFAULT       0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_CONTROL - GDDR5 CA playback control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: COUNT [11:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_MASK 0x00000ff0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_COUNT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_CONTROL :: SAMPLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *CA_PLAYBACK_STATUS0 - LPDDR3 and GDDR5 CA playback status register0
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: VALID [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_SHIFT 31
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_VALID_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved0 [30:26] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_MASK 0x7c000000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved0_SHIFT 26
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA1 [25:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_MASK 0x03ff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: reserved1 [15:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_MASK 0x0000fc00
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_reserved1_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: CA_PLAYBACK_STATUS0 :: DATA0 [09:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_MASK 0x000003ff
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_CA_PLAYBACK_STATUS0_DATA0_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_CONTROL - Write leveling control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: COUNT [15:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_MASK 0x0000ff00
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_BITS 8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_COUNT_DEFAULT 0x0000000f
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: reserved1 [07:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_MASK 0x000000f8
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_reserved1_SHIFT 3
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: SAMPLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_SAMPLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: CONTINUOUS [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_CONTINUOUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *WRITE_LEVELING_STATUS - Write leveling status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved0 [31:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_MASK 0xffffc000
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_BITS 18
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved0_SHIFT 14
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: EDC [13:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_MASK 0x00003e00
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_EDC_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: STATUS [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_MASK 0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: reserved1 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_reserved1_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: WRITE_LEVELING_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_WRITE_LEVELING_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_CONTROL - Read enable test cycle control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved0 [31:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_MASK 0xffffe000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_BITS 19
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: TEST_CYCLE [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_TEST_CYCLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: SELECT [11:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_MASK 0x00000f00
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_SELECT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: reserved1 [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_MASK 0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: CS_N [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_MASK  0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_BITS  2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_CS_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_DATA [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_DATA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: EDC_PHASE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_EDC_PHASE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: DQS [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_MASK   0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_SHIFT  1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_DQS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *READ_ENABLE_STATUS - Read enable test cycle status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: DATA [19:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_MASK   0x000ff000
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_BITS   8
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_SHIFT  12
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_DATA_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved1 [11:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_MASK 0x00000fc0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_BITS 6
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved1_SHIFT 6
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL1_STATUS [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL1_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: BL0_STATUS [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_BL0_STATUS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: reserved2 [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_MASK 0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_reserved2_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: READ_ENABLE_STATUS :: VALID [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_MASK  0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_READ_ENABLE_STATUS_VALID_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_LFSR_SEED - Traffic generator seed register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_LFSR_SEED :: SEED [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_LFSR_SEED_SEED_DEFAULT 0xba5eba11
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS1 - Traffic generator address register #1
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: BANK [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_BANK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS1 :: ROW [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_MASK  0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_BITS  16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS1_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ADDRESS2 - Traffic generator address register #2
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: BANK [19:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_MASK 0x000f0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_BANK_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ADDRESS2 :: ROW [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_MASK  0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_BITS  16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ADDRESS2_ROW_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_CONTROL - Traffic generator control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: reserved0 [31:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_MASK 0xffffe000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_BITS 19
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_reserved0_SHIFT 13
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WRO_RD [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WRO_RD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: DIAG_WR_RD [10:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_MASK 0x00000400
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_SHIFT 10
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_DIAG_WR_RD_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: WR_NOISE [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_WR_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_NOISE [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: CLEAR_DRAM [07:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_MASK 0x00000080
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_CLEAR_DRAM_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MASK_DM [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MASK_DM_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: INIT_LFSR [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_INIT_LFSR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: FIFO [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_MASK  0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_FIFO_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: MPR [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_MASK   0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_SHIFT  3
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_MPR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_WR [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_WR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: RD_EN [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_RD_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_CONTROL_ENABLE_SHIFT 0
-
-/***************************************************************************
- *TRAFFIC_GEN_DATA_CONTROL - Traffic generator data control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: reserved0 [31:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_MASK 0xffc00000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_BITS 10
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_reserved0_SHIFT 22
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: PATTERN [21:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_MASK 0x00300000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_PATTERN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DATA_CONTROL :: LENGTH [19:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_MASK 0x000fffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DATA_CONTROL_LENGTH_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_MASK - Traffic generator DQ mask register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_MASK :: MASK [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_MASK  0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_BITS  32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_DQ_MASK - Traffic generator ECC DQ mask register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_DQ_MASK :: MASK [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_DQ_MASK_MASK_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_STATUS - Traffic generator status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: reserved0 [31:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_MASK 0xfffffffe
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_reserved0_SHIFT 1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_STATUS :: BUSY [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_MASK   0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_SHIFT  0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_STATUS_BUSY_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_DQ_STATUS - Traffic generator DQ status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_DQ_STATUS :: STATUS [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_MASK 0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_BITS 32
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_DQ_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ECC_STATUS - Traffic generator ECC DQ status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_MASK 0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_BITS 28
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ECC_STATUS :: STATUS [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_MASK 0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ECC_STATUS_STATUS_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_CONTROL - Traffic generator error count control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved0 [31:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_MASK 0xfffffe00
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_BITS 23
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved0_SHIFT 9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: DQ_SEL [08:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_MASK 0x000001f0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_DQ_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: reserved1 [03:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_MASK 0x0000000c
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_reserved1_SHIFT 2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: CLEAR [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_CLEAR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_CONTROL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_CONTROL_ENABLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *TRAFFIC_GEN_ERR_CNT_STATUS - Traffic generator error count status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: reserved0 [31:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_MASK 0xffff0000
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_reserved0_SHIFT 16
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: TRAFFIC_GEN_ERR_CNT_STATUS :: COUNT [15:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_MASK 0x0000ffff
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_BITS 16
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_TRAFFIC_GEN_ERR_CNT_STATUS_COUNT_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved0 [31:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xfffff000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_BITS 20
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 12
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: reserved_for_eco1 [11:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_MASK 0x00000f00
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_BITS 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_reserved_for_eco1_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: MAX_NOISE [07:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_MASK 0x00000080
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_MAX_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_NOISE [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_MASK 0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_NOISE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: LOW_VTT [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_MASK 0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_SHIFT 5
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_LOW_VTT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: HIGH_VTT [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_HIGH_VTT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ERROR_RESET [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ERROR_RESET_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CTL_IDLE [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CTL_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CS_IDLE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CS_IDLE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONTROL :: ENABLE_CKE_IDLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_MASK 0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONTROL_ENABLE_CKE_IDLE_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_BITS 13
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR [18:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_MASK  0x0007fff8
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_BITS  16
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_LOW [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_MASK 0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_SHIFT 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_LOW_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: ERROR_HIGH [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_MASK 0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_SHIFT 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_ERROR_HIGH_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_STATUS :: READY [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_MASK  0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_STATUS_READY_DEFAULT 0x00000000
-
-/***************************************************************************
- *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_CONNECTIONS :: MASK [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_CONNECTIONS_MASK_DEFAULT 0x1fffffff
-
-/***************************************************************************
- *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VIRTUAL_VTT_OVERRIDE :: MASK [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_SHIFT 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VIRTUAL_VTT_OVERRIDE_MASK_DEFAULT 0x0000ffff
-
-/***************************************************************************
- *VREF_DAC_CONTROL - VREF DAC Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: reserved0 [31:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_MASK 0xfff00000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_BITS 12
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_reserved0_SHIFT 20
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: AUX_GT_INT [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_MASK 0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_SHIFT 19
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_AUX_GT_INT_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TESTOUT_MUX_CTL [18:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_MASK 0x00060000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_SHIFT 17
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TESTOUT_MUX_CTL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: TEST [16:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_MASK     0x00010000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_SHIFT    16
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_TEST_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN3 [15:15] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_MASK     0x00008000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_SHIFT    15
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN3_DEFAULT  0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN2 [14:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_MASK     0x00004000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_SHIFT    14
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN2_DEFAULT  0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN1 [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_MASK     0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_SHIFT    13
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN1_DEFAULT  0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: PDN0 [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_MASK     0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_SHIFT    12
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_PDN0_DEFAULT  0x00000001
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC1 [11:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_MASK     0x00000fc0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_BITS     6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_SHIFT    6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC1_DEFAULT  0x00000020
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: VREF_DAC_CONTROL :: DAC0 [05:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_MASK     0x0000003f
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_BITS     6
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_SHIFT    0
-#define DDR34_CORE_PHY_CONTROL_REGS_VREF_DAC_CONTROL_DAC0_DEFAULT  0x00000020
-
-/***************************************************************************
- *PHYBIST_CNTRL - PhyBist Control Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved0 [31:30] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_MASK   0xc0000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_BITS   2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved0_SHIFT  30
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: CLK_PAD_ENB [29:28] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_MASK 0x30000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_SHIFT 28
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_CLK_PAD_ENB_DEFAULT 0x00000002
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved1 [27:27] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_MASK   0x08000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved1_SHIFT  27
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DQ_ERROR_SEL [26:24] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_MASK 0x07000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_SHIFT 24
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DQ_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved2 [23:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_MASK   0x00800000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved2_SHIFT  23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_BL_ERROR_SEL [22:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_MASK 0x00700000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_BITS 3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_BL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved3 [19:17] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_MASK   0x000e0000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_BITS   3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved3_SHIFT  17
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR_SEL [16:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_MASK 0x0001f000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_BITS 5
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SEL_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: reserved4 [11:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_MASK   0x00000c00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_BITS   2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_reserved4_SHIFT  10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_DAT_ERROR [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_MASK 0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_DAT_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: FORCE_CTL_ERROR [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_MASK 0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_SHIFT 8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_FORCE_CTL_ERROR_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: SSO [07:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_MASK         0x000000c0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_BITS         2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_SHIFT        6
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_SSO_DEFAULT      0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: LENGTH [05:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_MASK      0x00000030
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_BITS      2
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_SHIFT     4
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_LENGTH_DEFAULT   0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: MODE [03:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_MASK        0x0000000e
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_ALIGN       0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_BITS        3
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_SHIFT       1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_MODE_DEFAULT     0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CNTRL :: ENABLE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_MASK      0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_BITS      1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CNTRL_ENABLE_DEFAULT   0x00000000
-
-/***************************************************************************
- *PHYBIST_SEED - PhyBist Seed Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_SEED :: SEED [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_MASK         0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_ALIGN        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_BITS         32
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_SHIFT        0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_SEED_SEED_DEFAULT      0xba5eba11
-
-/***************************************************************************
- *PHYBIST_CA_MASK - PhyBist Command/Address Bus Mask
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CA_MASK :: MASK [31:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_MASK      0xffffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_ALIGN     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_BITS      32
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_SHIFT     0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CA_MASK_MASK_DEFAULT   0x00000000
-
-/***************************************************************************
- *PHYBIST_STATUS - PhyBist General Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: reserved0 [31:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_MASK  0xfffffff0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_BITS  28
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_reserved0_SHIFT 4
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_PASS [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_MASK   0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_PASS_SHIFT  3
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_PASS [02:02] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_MASK   0x00000004
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_PASS_SHIFT  2
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: DAT_DONE [01:01] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_MASK   0x00000002
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_DAT_DONE_SHIFT  1
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_STATUS :: CTL_DONE [00:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_MASK   0x00000001
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_BITS   1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_STATUS_CTL_DONE_SHIFT  0
-
-/***************************************************************************
- *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: reserved0 [31:31] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_MASK 0x80000000
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_reserved0_SHIFT 31
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_CTL_STATUS :: CTL_ERRORS [30:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_MASK 0x7fffffff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_BITS 31
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_CTL_STATUS_CTL_ERRORS_SHIFT 0
-
-/***************************************************************************
- *PHYBIST_BL0_STATUS - PhyBist Byte Lane #0 Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: EDC [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_MASK    0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_EDC_SHIFT   9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DM [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_MASK     0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DM_SHIFT    8
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL0_STATUS :: DQ [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_MASK     0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_BITS     8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL0_STATUS_DQ_SHIFT    0
-
-/***************************************************************************
- *PHYBIST_BL1_STATUS - PhyBist Byte Lane #1 Status Register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: reserved0 [31:10] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_MASK 0xfffffc00
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_BITS 22
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_reserved0_SHIFT 10
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: EDC [09:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_MASK    0x00000200
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_ALIGN   0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_BITS    1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_EDC_SHIFT   9
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DM [08:08] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_MASK     0x00000100
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DM_SHIFT    8
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: PHYBIST_BL1_STATUS :: DQ [07:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_MASK     0x000000ff
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_BITS     8
-#define DDR34_CORE_PHY_CONTROL_REGS_PHYBIST_BL1_STATUS_DQ_SHIFT    0
-
-/***************************************************************************
- *STANDBY_CONTROL - Standby Control register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: reserved0 [31:23] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_MASK 0xff800000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_BITS 9
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_reserved0_SHIFT 23
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_READY [22:22] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_MASK 0x00400000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_SHIFT 22
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_READY_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_EXIT_PIN_EN [21:21] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_MASK 0x00200000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_SHIFT 21
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_EXIT_PIN_EN_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY_ACTIVE [20:20] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_MASK 0x00100000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_SHIFT 20
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ACTIVE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: ARMED [19:19] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_MASK     0x00080000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_SHIFT    19
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_ARMED_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: WARMSTART [18:18] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_MASK 0x00040000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_SHIFT 18
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_WARMSTART_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_BIAS [17:16] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_MASK 0x00030000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_SHIFT 16
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_BIAS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_LDO_VOLTS [15:14] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_MASK 0x0000c000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_SHIFT 14
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_LDO_VOLTS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_SKIP_MRS [13:13] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_MASK 0x00002000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_SHIFT 13
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_RST_N [12:12] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_MASK 0x00001000
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_SHIFT 12
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_RST_N_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: PWRDOWN_CKE [11:11] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_MASK 0x00000800
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_SHIFT 11
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_PWRDOWN_CKE_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_BIAS [10:09] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_MASK  0x00000600
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_BITS  2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_SHIFT 9
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_BIAS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: LDO_VOLTS [08:07] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_MASK 0x00000180
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_BITS 2
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_SHIFT 7
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_LDO_VOLTS_DEFAULT 0x00000003
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: SKIP_MRS [06:06] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_MASK  0x00000040
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_BITS  1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_SHIFT 6
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_SKIP_MRS_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: RST_N [05:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_MASK     0x00000020
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_ALIGN    0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_BITS     1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_SHIFT    5
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_RST_N_DEFAULT  0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: CKE [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_MASK       0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_ALIGN      0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_BITS       1
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_SHIFT      4
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_CKE_DEFAULT    0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: STANDBY_CONTROL :: STANDBY [03:00] */
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_MASK   0x0000000f
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_ALIGN  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_BITS   4
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_SHIFT  0
-#define DDR34_CORE_PHY_CONTROL_REGS_STANDBY_CONTROL_STANDBY_DEFAULT 0x00000000
-
-/***************************************************************************
- *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
- ***************************************************************************/
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: reserved0 [31:05] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xffffffe0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_BITS 27
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 5
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WLECC [04:04] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_MASK 0x00000010
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_SHIFT 4
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WLECC_DEFAULT 0x00000000
-
-/* DDR34_CORE_PHY_CONTROL_REGS :: DEBUG_FREEZE_ENABLE :: WL1_BL1 [03:03] */
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_MASK 0x00000008
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_ALIGN 0
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_BITS 1
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_SHIFT 3
-#define DDR34_CORE_PHY_CONTROL_REGS_DEBUG_FREEZE_ENABLE_WL1_BL1_DEFAULT 0x00000000
-
-/