Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
ada36d4cff54c419479a7865278108d2ae44bc6e
/
.
/
src
/
southbridge
/
amd
/
cs5535
/
Makefile.inc
blob: 3785cd400256f527d35765bfec1dc0d78143ef4d [
file
] [
log
] [
blame
]
ifeq
(
$
(
CONFIG_SOUTHBRIDGE_AMD_CS5535
),
y
)
ramstage
-
y
+=
cs5535
.
c
#ramstage-y += pci.c
#ramstage-y += ide.c
ramstage
-
y
+=
chipsetinit
.
c
endif