newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
diff --git a/src/arch/i386/Config.lb b/src/arch/i386/Config.lb
deleted file mode 100644
index 7234c33..0000000
--- a/src/arch/i386/Config.lb
+++ /dev/null
@@ -1,73 +0,0 @@
-uses CONFIG_SMP
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_USE_INIT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_USE_FALLBACK_IMAGE
-
-init init/crt0.S.lb
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-	initobject /src/lib/cbfs.o
-	initobject /src/lib/lzma.o
-end
-
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		ldscript init/ldscript_failover.lb
-	else
-			ldscript init/ldscript_cbfs.lb
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		ldscript init/ldscript_fallback_cbfs.lb
-	else
-		ldscript init/ldscript_cbfs.lb
-	end
-end
-
-makerule all
-	depends	"coreboot.rom"
-end
-
-makerule floppy 
-	depends	"all" 
-	action	"mcopy -o coreboot.rom a:"
-end
-
-makerule nrv2b 
-	depends	"$(TOP)/util/nrv2b/nrv2b.c"
-	action	"$(HOSTCC) -O2 -DENCODE -DDECODE -DMAIN -DVERBOSE -DNDEBUG -DBITSIZE=32 -DENDIAN=0 $< -o $@"
-end
-
-if CONFIG_USE_FAILOVER_IMAGE
-	makedefine COREBOOT_APC:=
-	makedefine COREBOOT_RAM_ROM:=
-end
-
-makerule crt0.S
-	depends "$(CONFIG_CRT0)"
-	action  "cp $< $@"
-end
-
-addaction clean "rm -f romimage payload.*"
-
-if CONFIG_USE_INIT
-	makerule init.o
-        	depends "$(INIT-OBJECTS)"
-	        action  "$(LD) -melf_i386 -r -o init.pre.o $(INIT-OBJECTS)"
-	        action  "$(CONFIG_OBJCOPY) --rename-section .text=.init.text --rename-section .data=.init.data --rename-section .rodata=.init.rodata --rename-section .rodata.str1.1=.init.rodata.str1.1 init.pre.o init.o"
-	end
-
-        makerule coreboot   
-		depends	"crt0.o init.o $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
-		action	"$(CC) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o init.o"
-		action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
-        end
-
-end
-
-dir lib
-dir boot
-dir smp
diff --git a/src/arch/i386/boot/Config.lb b/src/arch/i386/boot/Config.lb
deleted file mode 100644
index ec5c669..0000000
--- a/src/arch/i386/boot/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_MULTIBOOT
-uses CONFIG_HAVE_ACPI_RESUME
-
-object boot.o
-object coreboot_table.o
-if CONFIG_MULTIBOOT
-object multiboot.o
-end
-object tables.o
-if CONFIG_GENERATE_PIRQ_TABLE
-object pirq_routing.o 
-end
-if CONFIG_GENERATE_ACPI_TABLES
-object acpi.o
-object acpigen.o
-if CONFIG_HAVE_ACPI_RESUME
-object wakeup.S
-end
-end
-object gdt.o
diff --git a/src/arch/i386/lib/Config.lb b/src/arch/i386/lib/Config.lb
deleted file mode 100644
index 1d434e2..0000000
--- a/src/arch/i386/lib/Config.lb
+++ /dev/null
@@ -1,18 +0,0 @@
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_USE_FAILOVER_IMAGE
-
-object c_start.S
-object cpu.c
-object pci_ops_conf1.c
-object pci_ops_conf2.c
-object pci_ops_mmconf.c
-object pci_ops_auto.c
-object exception.c
-
-initobject printk_init.o
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-	initobject cbfs_and_run.o
-end
diff --git a/src/arch/i386/smp/Config.lb b/src/arch/i386/smp/Config.lb
deleted file mode 100644
index 70981a9..0000000
--- a/src/arch/i386/smp/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_IOAPIC
-
-if CONFIG_GENERATE_MP_TABLE
-  object mpspec.o 
-end
-if CONFIG_IOAPIC
-  object ioapic.o
-end
-
diff --git a/src/boot/Config.lb b/src/boot/Config.lb
deleted file mode 100644
index 8afe637..0000000
--- a/src/boot/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-object hardwaremain.o
-object selfboot.o
diff --git a/src/config/Config.lb b/src/config/Config.lb
deleted file mode 100644
index 082cf80..0000000
--- a/src/config/Config.lb
+++ /dev/null
@@ -1,214 +0,0 @@
-## This is Architecture independant part of the makefile
-
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_ASSEMBLER_DEBUG
-
-makedefine CPP:= $(CC) -x assembler-with-cpp -DASSEMBLY -E
-makedefine LIBGCC_FILE_NAME := $(shell $(CC) -print-libgcc-file-name)
-makedefine GCC ?= $(CC)
-makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
-
-makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(CONFIG_ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS = $(CONFIG_CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer -pipe
-
-if CONFIG_ASSEMBLER_DEBUG
-makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
-end
-
-makedefine HOSTCFLAGS:= -Os -Wall -Wstrict-prototypes -Wmissing-prototypes -Wredundant-decls -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow
-
-makerule ldscript.ld   
-	depends	"ldoptions $(LDSUBSCRIPTS-1)" 
-	action  "echo 'INCLUDE ldoptions' > $@; for file in $(LDSUBSCRIPTS-1) ; do echo /\* $$file \*/ >> $@; cat $$file >> $@ ; done"
-end
-
-#makerule cpuflags   
-#	depends	"Makefile.settings" 
-#	action	"perl -e 'print \"CPUFLAGS :=\n\"; foreach $$var (split(\" \", $$ENV{VARIABLES})) { if (exists($$ENV{$$var})) { print \"CPUFLAGS += -D$$var\" . (length($$ENV{$$var})?\"=\x27$$ENV{$$var}\x27\":\"\") .\"\n\"} else { print \"CPUFLAGS += -U$$var\n\"} }' > $@"
-#end
-
-#makerule ldoptions   
-#	depends	"Makefile.settings" 
-#	action	"perl -e 'foreach $$var (split(\" \", $$ENV{VARIABLES})) { if ($$ENV{$$var} =~ m/^(0x[0-9a-fA-F]+|0[0-7]+|[0-9]+)$$/) { print \"$$var = $$ENV{$$var};\n\"; }}' > $@"
-#end
-
-makerule coreboot.rom
-	depends	"coreboot" 
-	action	"$(CONFIG_OBJCOPY) -O binary coreboot coreboot.rom"
-end
-
-makerule coreboot.a
-        depends "$(OBJECTS)"
-        action  "rm -f coreboot.a"
-        action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot.a $(OBJECTS)"
-end
-
-
-makerule coreboot_ram.o
-	depends	"src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) coreboot.a $(LIBGCC_FILE_NAME)" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ src/arch/$(CONFIG_ARCH)/lib/c_start.o $(DRIVER) -Wl,--wrap,__divdi3 -Wl,--wrap,__udivdi3 -Wl,--wrap,__moddi3 -Wl,--wrap,__umoddi3 -Wl,-\( coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)"
-end
-
-makerule coreboot_ram
-	depends	"coreboot_ram.o $(TOP)/src/config/coreboot_ram.ld ldoptions" 
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o"
-	action 	"$(CONFIG_CROSS_COMPILE)nm -n coreboot_ram | sort > coreboot_ram.map"
-end
-
-##
-## By default compress the part of coreboot that runs from RAM
-##
-makedefine COREBOOT_RAM-$(CONFIG_COMPRESS):=coreboot_ram.nrv2b
-makedefine COREBOOT_RAM-$(CONFIG_UNCOMPRESSED):=coreboot_ram.bin
-
-makerule coreboot_ram.bin 
-	depends	"coreboot_ram" 
-	action	"$(CONFIG_OBJCOPY) -O binary $< $@"
-end
-
-makerule coreboot_ram.nrv2b 
-	depends	"coreboot_ram.bin nrv2b" 
-	action	"./nrv2b e $< $@"
-end
-
-makerule coreboot_ram.rom
-	depends	"$(COREBOOT_RAM-1)" 
-	action	"cp $(COREBOOT_RAM-1) coreboot_ram.rom"
-end
-
-makedefine COREBOOT_APC:=
-
-if CONFIG_AP_CODE_IN_CAR
-	#for ap code in cache
-
-	makerule coreboot_apc.a
-		depends "apc_auto.o"
-		action  "rm -f coreboot_apc.a"
-		action  "$(CONFIG_CROSS_COMPILE)ar cr coreboot_apc.a apc_auto.o"
-	end
-
-	makerule coreboot_apc.o
-		depends "src/arch/$(CONFIG_ARCH)/lib/c_start.o coreboot_apc.a"
-        	action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
-	end
-
-	makerule coreboot_apc
-		depends "coreboot_apc.o $(TOP)/src/config/coreboot_apc.ld ldoptions"
-		action  "$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T $(TOP)/src/config/coreboot_apc.ld coreboot_apc.o"
-		action  "$(CONFIG_CROSS_COMPILE)nm -n coreboot_apc | sort > coreboot_apc.map"
-	end
-
-	##
-	## By default compress the part of coreboot that runs from cache as ram
-	##
-	makedefine COREBOOT_APC-$(CONFIG_COMPRESS):=coreboot_apc.nrv2b
-	makedefine COREBOOT_APC-$(CONFIG_UNCOMPRESSED):=coreboot_apc.bin
-
-	makerule coreboot_apc.bin
-		depends "coreboot_apc"
-		action  "$(CONFIG_OBJCOPY) -O binary $< $@"
-	end
-
-	makerule coreboot_apc.nrv2b
-        depends "coreboot_apc.bin nrv2b"
-        action  "./nrv2b e $< $@"
-	end
-
-	makerule coreboot_apc.rom
-		depends "$(COREBOOT_APC-1)"
-		action  "cp $(COREBOOT_APC-1) coreboot_apc.rom"
-	end
-
-	makedefine COREBOOT_APC:=coreboot_apc.rom
-
-end
-
-makedefine COREBOOT_RAM_ROM:=coreboot_ram.rom
-
-makerule coreboot   
-	depends	"crt0.o $(INIT-OBJECTS) $(COREBOOT_APC) $(COREBOOT_RAM_ROM) ldscript.ld"
-	action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o $@ -T ldscript.ld crt0.o $(INIT-OBJECTS)"
-	action	"$(CONFIG_CROSS_COMPILE)nm -n coreboot | sort > coreboot.map"
-	action 	"$(CONFIG_CROSS_COMPILE)objdump -dS coreboot > coreboot.disasm"	
-end
-
-# Force crt0.s (which has build time version code in it to rebuild every time)
-makedefine .PHONY : crt0.s
-makerule crt0.s   
-	depends	"crt0.S $(CRT0_INCLUDES)" 
-	action	"$(CPP) $(CPPFLAGS) -I. -I$(TOP)/src  $< > $@.new && mv $@.new $@"
-end
-
-# generate an assembly listing via -a switch.
-makerule crt0.o  
-	depends	"crt0.s" 
-	action	"$(CC) -Wa,-acdlns -c $(CONFIG_CPU_OPT) -o $@ $< >crt0.disasm"
-end
-
-makerule etags   
-	depends	"$(SOURCES)" 
-	action	"etags $(SOURCES)"
-end
-makerule tags   
-	depends	"$(SOURCES)" 
-	action	"ctags $(SOURCES)"
-end
-makerule corebootDoc.config
-	depends	"$(TOP)/src/config/corebootDoc.config" 
-	action "cat $(TOP)/src/config/corebootDoc.config > corebootDoc.config"
-        action "echo 'INPUT=$(SOURCES)' >> corebootDoc.config"
-end
-makerule documentation   
-	depends	"corebootDoc.config"
-	action	"doxygen corebootDoc.config"
-end
-
-# Yes, the rule doesn't seem to make sense, but multiple images could try to
-# create a romcc binary at the same time, clobbering each other.
-# Our makefile architecture won't allow us to easily have the romcc target
-# in the main makefile, so keep it here and move the race condition winner
-# in place. That way, romcc may get compiled twice, but the binary will always
-# be in a correct and valid state if it exists because the move is atomic.
-makerule ../romcc   
-	depends	"$(TOP)/util/romcc/romcc.c" 
-	action	"$(HOSTCC) -g $(HOSTCFLAGS) $< -o romcc.tmpfile"
-	action	"mv romcc.tmpfile $@"
-end
-
-makerule build_opt_tbl   
-	depends	"$(TOP)/util/options/build_opt_tbl.c $(TOP)/src/include/pc80/mc146818rtc.h $(TOP)/src/include/boot/coreboot_tables.h Makefile.settings Makefile"
-	action	"$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) $< -o $@" 
-end
-
-makerule option_table.h option_table.c
-	depends	"build_opt_tbl $(CONFIG_MAINBOARD)/cmos.layout" 
-	action	"./build_opt_tbl --config $(CONFIG_MAINBOARD)/cmos.layout --header option_table.h --option option_table.c"
-end
-
-if CONFIG_HAVE_OPTION_TABLE
-object ./option_table.o 
-end
-
-makerule clean 
-	action  "rm -f $(OBJECTS)"
-	action  "rm -f $(DRIVER)"
-	action	"rm -f coreboot.* *~"
-	action	"rm -f coreboot"
-	action	"rm -f ldscript.ld"
-	action	"rm -f a.out *.s *.l *.o *.E *.inc"
-	action	"rm -f TAGS tags romcc*"
-	action	"rm -f docipl chips.c *chip.c coreboot_apc* coreboot_ram* coreboot_pay*"
-	action	"rm -f build_opt_tbl* nrv2b* option_table.c option_table.h crt0.S crt0.disasm"
-	action	"rm -f smm smm.elf smm.map smm_bin.c"
-	action	"rm -f dsdt.aml dsdt.c"
-	action	"rm -f payload"
-end
-
-# do standard config files that the user need not specify
-# for now, this is just 'lib', but it may be more later. 
-dir /lib
-dir /console
-dir /devices
-dir /pc80
-dir /boot
diff --git a/src/config/Options.lb b/src/config/Options.lb
deleted file mode 100644
index 9af3daf..0000000
--- a/src/config/Options.lb
+++ /dev/null
@@ -1,1122 +0,0 @@
-#######################################################
-#
-# Main options file for coreboot
-#
-# Each option used by a part must be defined in
-# this file. The format for options is:
-#
-#   define <name> 
-#	default <expr> | {<expr>} | "<string>" | none
-#	format "<string>"
-#	export always | used | never
-#	comment "<string>"
-#   end
-#
-# where 
-#
-#   <name> is the name of the option
-#   <expr> is a numeric expression
-#   <string> is a string
-#
-# Either a default value or 'default none' must
-# be specified for every option. An option
-# specified as 'default none' will not be exported
-# (i.e. will remain undefined) unless it has
-# been assigned a value.
-#
-# Option values can be an immediate expression that 
-# evaluates to a numeric value, a delayed expression 
-# (surrounded by curley braces), or a string 
-# (surrounded by double quotes.)
-#
-# Immediate expressions are evaluated at the time an
-# option is defined or set and the numeric result 
-# becomes the value of the option.
-#
-# Delayed expression are evaluated at the time the 
-# option is used, either in another expression or 
-# when being exported.
-#
-# String values will have the double quotes removed 
-# automatically. 
-#
-# Format strings determine the print format that is 
-# used when exporting options. The default format
-# is "%s" for strings and "%d" for numbers.
-#
-# Exported options generate entries in the 
-# Makefile.settings file. Options can be always 
-# exported, exported only if used, or never exported.
-#
-# A comment string must be supplied for every option.
-#
-#######################################################
-
-###############################################
-# Architecture options
-###############################################
-
-define CONFIG_ARCH_X86
-	default 1
-	export always
-	comment "X86 is the default"
-end
-define CONFIG_ARCH
-	default "i386"
-	export always
-	comment "Default architecture is i386, options are alpha and ppc"
-end
-define CONFIG_HAVE_MOVNTI
-	default 0
-	export always
-	comment "This cpu supports the MOVNTI directive"
-end
-
-###############################################
-# Build options
-###############################################
-
-define CONFIG_CROSS_COMPILE
-	default ""
-	export always
-	comment "Cross compiler prefix"
-end
-define CC
-	default "$(CONFIG_CROSS_COMPILE)gcc"
-	export always
-	comment "Target C Compiler"
-end
-define HOSTCC
-	default "gcc"
-	export always
-	comment "Host C Compiler"
-end
-define CONFIG_CPU_OPT
-	default none
-	export used
-	comment "Additional per-cpu CFLAGS"
-end
-define CONFIG_OBJCOPY
-	default "$(CONFIG_CROSS_COMPILE)objcopy --gap-fill 0xff"
-	export always
-	comment "Objcopy command"
-end
-
-# Try to determine svn revision first.
-# If that fails, try last svn revision in git log.
-define COREBOOT_VERSION
-	default "2.0.0-r$(shell if [ -d $(TOP)/.svn -a -f `which svnversion` ]; then svnversion $(TOP); else if [ -d $(TOP)/.git -a -f `which git` ]; then git --git-dir=/$(TOP)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)"
-	export always
-	format "\"%s\""
-	comment "coreboot version"
-end
-define COREBOOT_EXTRA_VERSION
-        default ""
-        export used
-	format "\"%s\""
-        comment "coreboot extra version"
-end
-define COREBOOT_BUILD
-	default "$(shell date)"
-	export always
-	format "\"%s\""
-	comment "Build date"
-end
-define COREBOOT_COMPILE_TIME
-	default "$(shell date +%T)"
-	export always
-	format "\"%s\""
-	comment "Build time"
-end
-define COREBOOT_COMPILE_BY
-	default "$(shell whoami)"
-	export always
-	format "\"%s\""
-	comment "Who build this image"
-end
-define COREBOOT_COMPILE_HOST
-	default "$(shell hostname)"
-	export always
-	format "\"%s\""
-	comment "Build host"
-end
-
-define COREBOOT_COMPILE_DOMAIN
-	default "$(shell dnsdomainname)"
-	export always
-	format "\"%s\""
-	comment "Build domain name"
-end
-define COREBOOT_COMPILER
-	default "$(shell $(CC) $(CFLAGS) -v 2>&1 | tail -1)"
-	export always
-	format "\"%s\""
-	comment "Build compiler"
-end
-define COREBOOT_LINKER
-	default "$(shell  $(CC) -Wl,--version 2>&1 | grep \" ld\")"
-	export always
-	format "\"%s\""
-	comment "Build linker"
-end
-define COREBOOT_ASSEMBLER
-	default "$(shell  touch dummy.s ; $(CC) -c -Wa,-v dummy.s 2>&1; rm -f dummy.s dummy.o )"
-	export always
-	format "\"%s\""
-	comment "Build assembler"
-end
-define CONFIG_CHIP_CONFIGURE
-	default 0
-	export used
-	comment "Use new chip_configure method for configuring (non-pci) devices"
-end
-define CONFIG_USE_INIT
-	default 0
-	export always
-	comment "Use stage 1 initialization code"
-end
-
-###############################################
-# ROM image options
-###############################################
-
-define CONFIG_HAVE_FALLBACK_BOOT
-	format "%d"
-	default 0
-	export always
-	comment "Set if fallback booting required"
-end
-define CONFIG_HAVE_FAILOVER_BOOT
-	format "%d"
-	default 0
-	export always
-	comment "Set if failover booting required"
-end
-define CONFIG_USE_FALLBACK_IMAGE
-	format "%d"
-	default 0
-	export used
-	comment "Set to build a fallback image"
-end
-define CONFIG_USE_FAILOVER_IMAGE
-        format "%d"
-        default 0
-        export used
-        comment "Set to build a failover image"
-end
-define CONFIG_FALLBACK_SIZE
-	default 65536
-	format "0x%x"
-	export used
-	comment "Default fallback image size"
-end
-define CONFIG_FAILOVER_SIZE
-        default 0
-        format "0x%x"
-        export used
-        comment "Default failover image size"
-end
-define CONFIG_ROM_SIZE
-	default none
-	format "0x%x"
-	export used
-	comment "Size of your ROM"
-end
-define CONFIG_ROM_IMAGE_SIZE
-	default 65535
-	format "0x%x"
-	export always
-	comment "Default image size"
-end
-define CONFIG_ROM_SECTION_SIZE
-	default {CONFIG_FALLBACK_SIZE}
-	format "0x%x"
-	export used
-	comment "Default rom section size"
-end
-define CONFIG_ROM_SECTION_OFFSET
-	default {CONFIG_ROM_SIZE - CONFIG_FALLBACK_SIZE}
-	format "0x%x"
-	export used
-	comment "Default rom section offset"
-end
-define CONFIG_ROMBASE
-	default {0xffffffff - CONFIG_ROM_SIZE + 1}
-	format "0x%x"
-	export always
-	comment "Base address of coreboot in ROM"
-end
-define CONFIG_ROMSTART
-	default none
-	format "0x%x"
-	export used
-	comment "Start address of coreboot in ROM"
-end
-define CONFIG_RESET
-	default {CONFIG_ROMBASE}
-	format "0x%x"
-	export always
-	comment "Hardware reset vector address"
-end
-define CONFIG_STACK_SIZE
-	default 0x2000
-	format "0x%x"
-	export always
-	comment "Default stack size"
-end
-define CONFIG_HEAP_SIZE
-	default 0x2000
-	format "0x%x"
-	export always
-	comment "Default heap size"
-end
-define CONFIG_RAMBASE
-	default none
-	format "0x%x"
-	export always
-	comment "Base address of coreboot in RAM"
-end
-define CONFIG_RAMSTART
-	default none
-	format "0x%x"
-	export used
-	comment "Start address of coreboot in RAM"
-end
-define CONFIG_USE_DCACHE_RAM
-	default 0
-	export always
-	comment "Use data cache as temporary RAM if possible"
-end
-define CONFIG_DCACHE_RAM_BASE
-	default 0xc0000
-	format "0x%x"
-	export always
-	comment "Base address of data cache when using it for temporary RAM"
-end
-define CONFIG_DCACHE_RAM_SIZE
-	default 0x1000
-	format "0x%x"
-	export always
-	comment "Size of data cache when using it for temporary RAM"
-end
-define CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-	default 0
-	format "0x%x"
-	export always
-	comment "Size of region that for global variable of cache as ram stage"
-end
-define CONFIG_AP_CODE_IN_CAR
-        default 0
-        export always
-        comment "will copy coreboot_apc to AP cache ane execute in AP"
-end
-define CONFIG_MEM_TRAIN_SEQ
-        default 0
-        export always
-        comment "0: three for in bsp, 1: on every core0, 2: one for on bsp"
-end
-define CONFIG_WAIT_BEFORE_CPUS_INIT
-        default 0
-        export always
-        comment "execute cpus_ready_for_init if it is set to 1"
-end
-define CONFIG_XIP_ROM_BASE
-	default 0
-	format "0x%x"
-	export used
-	comment "Start address of area to cache during coreboot execution directly from ROM"
-end
-define CONFIG_XIP_ROM_SIZE
-	default 0
-	format "0x%x"
-	export used
-	comment "Size of area to cache during coreboot execution directly from ROM"
-end
-define CONFIG_COMPRESS
-	default 1
-	export always
-	comment "Set for compressed image"
-end
-define CONFIG_UNCOMPRESSED
-	format "%d"
-	default {!CONFIG_COMPRESS}
-	export always
-	comment "Set for uncompressed image"
-end
-define CONFIG_RAMTOP
-	format "%d"
-	default 2048*1024
-	export always
-	comment "Highest RAM that coreboot_ram will use"
-end
-define CONFIG_HAVE_OPTION_TABLE
-	default 0
-	export always
-	comment "Export CMOS option table"
-end
-define CONFIG_USE_OPTION_TABLE
-	format "%d"
-	default {CONFIG_HAVE_OPTION_TABLE && !CONFIG_USE_FALLBACK_IMAGE}
-	export always
-	comment "Use option table"
-end
-
-###############################################
-# CMOS variable options
-###############################################
-define CONFIG_LB_CKS_RANGE_START
-	default 49
-	format "%d"
-	export always
-	comment "First CMOS byte to use for coreboot options"
-end
-define CONFIG_LB_CKS_RANGE_END
-	default 125
-	format "%d"
-	export always
-	comment "Last CMOS byte to use for coreboot options"
-end
-define CONFIG_LB_CKS_LOC
-	default 126
-	format "%d"
-	export always
-	comment "Pair of bytes to use for CMOS checksum"
-end
-
-
-###############################################
-# Build targets
-###############################################
-
-define CONFIG_CRT0
-	default "$(TOP)/src/arch/$(CONFIG_ARCH)/init/crt0.S.lb"
-	export always
-	comment "Main initialization target"
-end
-
-###############################################
-# Debugging/Logging options
-###############################################
-
-define CONFIG_DEBUG
-	default 0
-	export always
-	comment "Enable x86emu debugging code"
-end
-define CONFIG_VGA_BRIDGE_SETUP
-	default 1
-	export always
-	comment "Set bridge bits to enable legacy VGA ranges"
-end
-define CONFIG_CONSOLE_VGA
-	default 0
-	export always
-	comment "Log messages to any VGA-compatible device (may require *_ROM_RUN to bring up)"
-end
-define CONFIG_CONSOLE_VGA_MULTI
-        default 0
-        export always
-        comment "Multi VGA console"
-end
-define CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST
-        default 0
-        export always
-        comment "Use onboard VGA instead of add on VGA card"
-end
-define CONFIG_CONSOLE_BTEXT
-        default 0
-        export always
-        comment "Log messages to btext fb console"
-end
-define CONFIG_CONSOLE_LOGBUF
-	default 0
-	export always
-	comment "Log messages to buffer"
-end
-define CONFIG_CONSOLE_SROM
-	default 0
-	export always
-	comment "Log messages to SROM console"
-end
-define CONFIG_CONSOLE_SERIAL8250
-	default 0
-	export always
-	comment "Log messages to 8250 uart based serial console"
-end
-define CONFIG_USBDEBUG_DIRECT
-	default 0
-	export always
-	comment "Log messages to ehci debug port console"
-end
-define CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-	default 7
-	export always
-	comment "Console will log at this level unless changed"
-end
-define CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-	default 8
-	export always
- 	comment "Error messages up to this level can be printed"
-end
-define CONFIG_SERIAL_POST
-	default 0
-	export always
-	comment "Enable SERIAL POST codes"
-end
-define CONFIG_NO_POST
-	default none
-	export used
-	comment "Disable POST codes"
-end
-define CONFIG_TTYS0_BASE
-	default 0x3f8
-	format "0x%x"
-	export always
-	comment "Base address for 8250 uart for the serial console"
-end
-define CONFIG_TTYS0_BAUD
-	default 115200
-	export always
-	comment "Default baud rate for serial console"
-end
-define CONFIG_TTYS0_DIV
-	default none
-	format "%d"
-	export used
-	comment "Allow UART divisor to be set explicitly"
-end
-define CONFIG_TTYS0_LCS
-	default 0x3
-	format "0x%x"
-	export always
-	comment "Default flow control settings for the 8250 serial console uart"
-end
-
-define CONFIG_USE_PRINTK_IN_CAR
-	default 0
-	export always
-	comment "use printk instead of print in CAR stage code"
-end
-define CONFIG_ASSEMBLER_DEBUG
-	default 0
-	export always
-	comment "Create disassembly files for debugging"
-end
-
-###############################################
-# Mainboard options
-###############################################
-
-define CONFIG_MAINBOARD
-	default "Mainboard_not_set"
-	export always
-	comment "Mainboard name"
-end
-define CONFIG_MAINBOARD_PART_NUMBER
-	default "Part_number_not_set"
-	export always
-	format "\"%s\""
-	comment "Part number of mainboard"
-end
-define CONFIG_MAINBOARD_VENDOR
-	default "Vendor_not_set"
-	export always
-	format "\"%s\""
-	comment "Vendor of mainboard"
-end
-define CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-	default 0
-	export always
-	comment "PCI Vendor ID of mainboard manufacturer"
-end
-define CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-	default 0
-	format "0x%x"
-	export always
-	comment "PCI susbsystem device id assigned my mainboard manufacturer"
-end
-define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-	default none
-	export used
-	comment "Default power on after power fail setting"
-end
-define CONFIG_SYS_CLK_FREQ
-	default none
-	export used
-	comment "System clock frequency in MHz"
-end
-define CONFIG_EPIA_VT8237R_INIT
-	default none
-	export used
-	comment "Enable EPIA Specific Initialisation of VT8237R SB" 
-end
-###############################################
-# SMP options
-###############################################
-
-define CONFIG_SMP
-	default 0
-	export always
-	comment "Define if we support SMP"
-end
-define CONFIG_MAX_CPUS
-        default 1
-        export always
-        comment "Maximum CPU count for this machine"
-end
-define CONFIG_MAX_PHYSICAL_CPUS
-        default 1
-        export always
-        comment "Maximum physical CPU count for this machine"
-end
-define CONFIG_LOGICAL_CPUS
-	default 0
-	export always
-	comment "Should multiple cpus per die be enabled?"
-end
-define CONFIG_AP_IN_SIPI_WAIT
-	default 0
-	export always
-	comment "Should application processors go to SIPI wait state after initialization? (Required for Intel Core Duo)"
-end
-define CONFIG_GENERATE_MP_TABLE
-	default none
-	export used
-	comment "Define to build an MP table"
-end
-define CONFIG_SERIAL_CPU_INIT
-        default 1
-        export always
-        comment "Serialize CPU init"
-end
-define CONFIG_APIC_ID_OFFSET
-	default 0
-	export always
-	comment "We need to share this value between cache_as_ram_auto.c and northbridge.c"
-end
-define CONFIG_ENABLE_APIC_EXT_ID
-	default 0
-	export always
-	comment "Enable APIC ext id mode 8 bit"
-end
-define CONFIG_LIFT_BSP_APIC_ID
-	default 0
-	export always
-	comment "decide if we lift bsp apic id while ap apic id"
-end
-###############################################
-# Boot options
-###############################################
-
-define CONFIG_MULTIBOOT
-	default 1
-	export always
-	comment "Use Multiboot (rather than ELF boot notes) to boot the payload"
-end
-define CONFIG_ROM_PAYLOAD
-	default 0
-	export always
-	comment "Boot image is located in ROM" 
-end
-define CONFIG_COMPRESSED_PAYLOAD_NRV2B
-	default 0
-	export always
-	comment "NRV2B compressed boot image is located in ROM" 
-end
-define CONFIG_COMPRESSED_PAYLOAD_LZMA
-	default 0
-	export always
-	comment "LZMA compressed boot image is located in ROM" 
-end
-define CONFIG_PRECOMPRESSED_PAYLOAD
-	default 0
-	export always
-	comment "boot image is already compressed" 
-end
-
-define CONFIG_USE_WATCHDOG_ON_BOOT
-	default 0
-	export always
-	comment "Use the watchdog on booting"
-end
-
-###############################################
-# Plugin Device support options
-###############################################
-
-define CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin Hypertransport busses"
-end
-define CONFIG_AGP_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin AGP busses"
-end
-define CONFIG_CARDBUS_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support cardbus plugin cards"
-end
-define CONFIG_PCIX_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin PCI-X busses"
-end
-define CONFIG_PCIEXP_PLUGIN_SUPPORT
-	default 1
-	export always
-	comment "Enable support for plugin PCI-E busses"
-end
-
-###############################################
-# IRQ options
-###############################################
-
-define CONFIG_GENERATE_PIRQ_TABLE
-	default none
-	export used
-	comment "Define if we have a PIRQ table"
-end
-define CONFIG_PIRQ_ROUTE
-	default 0
-	export always
-	comment "Define if we have a PIRQ table and want routing IRQs"
-end
-define CONFIG_IRQ_SLOT_COUNT
-	default none
-	export used
-	comment "Number of IRQ slots"
-end
-define CONFIG_PCIBIOS_IRQ
-	default none
-	export used
-	comment "PCIBIOS IRQ support"
-end
-define CONFIG_IOAPIC
-	default 0
-	export always
-	comment "IOAPIC support"
-end
-
-###############################################
-# Options for memory mapped I/O
-###############################################
-
-define CONFIG_PCI_IO_CFG_EXT
-	default 0
-	export always
-	comment "allow 4K register space via io CFG port"
-end
-
-define CONFIG_PCIC0_CFGADDR
-	default none
-	format "0x%x"
-	export used
-	comment "Address of PCI Configuration Address Register"
-end
-define CONFIG_PCIC0_CFGDATA
-	default none
-	format "0x%x"
-	export used
-	comment "Address of PCI Configuration Data Register"
-end
-define CONFIG_ISA_IO_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of PCI/ISA I/O address range"
-end
-define CONFIG_ISA_MEM_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of PCI/ISA memory address range"
-end
-define CONFIG_PNP_CFGADDR
-	default none
-	format "0x%x"
-	export used
-	comment "PNP Configuration Address Register offset"
-end
-define CONFIG_PNP_CFGDATA
-	default none
-	format "0x%x"
-	export used
-	comment "PNP Configuration Data Register offset"
-end
-define CONFIG_IO_BASE
-	default none
-	format "0x%x"
-	export used
-	comment "Base address of memory mapped I/O operations"
-end
-
-###############################################
-# Options for embedded systems
-###############################################
-
-define CONFIG_EMBEDDED_RAM_SIZE
-	default none
-	export used
-	comment "Embedded boards generally have fixed RAM size"
-end
-
-###############################################
-# Misc options
-###############################################
-
-define CONFIG_GDB_STUB
-	default 0
-	export used
-	comment "Compile in gdb stub support?"
-end
-
-define CONFIG_HAVE_INIT_TIMER
-	default 0
-	export always
-	comment "Have a init_timer function"
-end
-define CONFIG_HAVE_HARD_RESET
-	default none
-	export used
-	comment "Have hard reset"
-end
-define CONFIG_HAVE_SMI_HANDLER
-	default 0
-	export always
-	comment "Set, if the board needs an SMI handler"
-end
-define CONFIG_MEMORY_HOLE
-	default none
-	export used
-	comment "Set to deal with memory hole"
-end
-define CONFIG_MAX_REBOOT_CNT
-	default 3
-	export always
-	comment "Set maximum reboots"
-end
-
-###############################################
-# Misc device options
-###############################################
-
-define CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL
-	default 0
-	export used
-	comment "Include board specific FAN control initialization"
-end
-define CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-	default 0
-	export used
-	comment "Use timer2 to callibrate the x86 time stamp counter"
-end
-define CONFIG_INTEL_PPRO_MTRR
-	default none
-	export used
-	comment ""
-end
-define CONFIG_UDELAY_TSC
-	default 0
-	export used
-	comment "Implement udelay with the x86 time stamp counter"
-end
-define CONFIG_UDELAY_IO
-	default 0
-	export used
-	comment "Implement udelay with x86 io registers"
-end
-define CONFIG_UDELAY_LAPIC
-	default 0
-	export used
-	comment "Implement udelay with the x86 Local APIC"
-end
-
-define CONFIG_GENERATE_ACPI_TABLES
-	default 0
-	export always
-	comment "Define to build ACPI tables"
-end
-
-define CONFIG_HAVE_ACPI_RESUME
-	default 0
-	export always
-	comment "Define to build ACPI with resume support"
-end
-
-define CONFIG_ACPI_SSDTX_NUM
-	default 0
-	export always
-	comment "extra ssdt num for PCI Device"
-end
-
-define CONFIG_AGP_APERTURE_SIZE
-	default none
-	export used
-	format "0x%x"
-	comment "AGP graphics virtual memory aperture size"
-end
-
-define CONFIG_HT_CHAIN_UNITID_BASE
-	default 1
-	export always
-	comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
-end
-
-define CONFIG_HT_CHAIN_END_UNITID_BASE
-        default 0x20
-        export always
-        comment "this will be unit id of the end of hypertransport chain (usually the real SB) if it is small than CONFIG_HT_CHAIN_UNITID_BASE, it could be 0"
-end
-
-define CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-        default 1
-        export always
-        comment "this will decided if only offset SB hypertransport chain"
-end
-
-define CONFIG_SB_HT_CHAIN_ON_BUS0
-        default 0 
-        export always
-        comment "this will make SB hypertransport chain sit on bus 0, if it is 1, will put sb ht chain on bus 0, if it is 2 will put other chain on 0x40, 0x80, 0xc0"
-end
-
-define CONFIG_PCI_BUS_SEGN_BITS
-        default 0
-        export always
-        comment "It could be 0, 1, 2, 3 and 4 only"
-end
-
-define CONFIG_MMCONF_SUPPORT
-	default 0
-	export always
-	comment "enable mmconfig for pci conf"
-end
-
-define CONFIG_MMCONF_SUPPORT_DEFAULT
-	default 0
-	export always
-	comment "enable mmconfig for pci conf"
-end
-
-define CONFIG_MMCONF_BASE_ADDRESS
-	default none
-	format "0x%x"
-	export used
-	comment "enable mmconfig base address"
-end
-
-define CONFIG_HW_MEM_HOLE_SIZEK
-        default 0
-        export always
-        comment "Opteron E0 later memory hole size in K, 0 mean disable"
-end
-
-define CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-        default 0
-        export always
-        comment "Opteron E0 later memory hole size auto increase to avoid hole startk equal to basek"
-end
-
-define CONFIG_VAR_MTRR_HOLE
-	default 1
-	export always
-	comment "using hole in MTRR instead of increasing method"
-end
-
-define CONFIG_K8_HT_FREQ_1G_SUPPORT
-	default 0 
-	export always
-	comment "Optern E0 later could support 1G HT, but still depends MB design"
-end
-
-define CONFIG_K8_REV_F_SUPPORT
-        default 0
-        export always
-        comment "Opteron Rev F (DDR2) support"
-end
-
-define CONFIG_CBB
-	default 0
-	export always
-	comment "Opteron cpu bus num base"
-end
-
-define CONFIG_CDB
-	default 0x18
-	export always
-	comment "Opteron cpu device num base"
-end
-
-define CONFIG_HT3_SUPPORT
-	default 0
-	export always
-	comment "Hypertransport 3 support, include ac HT and unganged sublink feature"
-end
-
-define CONFIG_EXT_RT_TBL_SUPPORT
-	default 0
-	export always
-	comment "support AMD family 10 extended routing table via F0x158, normally is enabled when node nums is greater than 8"
-end
-
-define CONFIG_EXT_CONF_SUPPORT
-	default 0
-	export always
-	comment "support AMD family 10 extended config space for ram, bus, io, mmio via F1x110, normally is enabled when HT3 is enabled and non ht chain nums is greater than 4"
-end
-
-define CONFIG_DIMM_SUPPORT
-        default 0x0108
-	format "0x%x"
-        export always
-        comment "DIMM support: bit 0 - sdram, bit 1: ddr1, bit 2: ddr2, bit 3: ddr3, bit 4: fbdimm, bit 8: reg"
-end
-
-define CONFIG_CPU_SOCKET_TYPE
-	default 0x10
-	export always
-	comment "cpu socket type, 0x10 mean Socket F, 0x11 mean socket M2, 0x20, Soxket G, and 0x21 mean socket M3"
-end
-
-define CONFIG_CPU_ADDR_BITS
-	default 36
-	export always
-	comment "CPU hardware address lines num, for AMD K8 could be 40, and AMD family 10 could be 48"
-end
-
-define CONFIG_VGA
-	default 0
-	export always
-	comment "Include VGA initialisation code"
-end
-
-define CONFIG_VGA_ROM_RUN
-	default 0
-	export always
-	comment "Init x86 ROMs on VGA-class PCI devices"
-end
-
-define CONFIG_PCI_ROM_RUN
-	default 0
-	export always
-	comment "Init x86 ROMs on all PCI devices"
-end
-
-define CONFIG_PCI_OPTION_ROM_RUN_YABEL
-	default 0
-	export used
-	comment "Use Yabel instead of old bios emulator"
-end
-
-define CONFIG_YABEL_DEBUG_FLAGS
-	default 0
-	export used
-	comment "YABEL debug flags, for possible values, see util/x86emu/yabel/debug.h"
-end
-
-define CONFIG_YABEL_PCI_ACCESS_OTHER_DEVICES
-	default 0
-	export used
-	comment "Allow Option ROMs executed by YABEL to access the config space of devices other than the one YABEL is running for. This may be needed by some onboard Graphics cards ROMs."
-
-end
-
-define CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-	default 0
-	export used
-	comment "Use Yabel instead of old bios emulator"
-end
-
-define CONFIG_PCI_64BIT_PREF_MEM
-        default 0
-        export always
-        comment "allow PCI device get 4G above Region as pref mem"
-end
-
-define CONFIG_AMDMCT
-	default 0
-	export always
-	comment "use AMD MCT to init RAM instead of native code"
-end
-
-define CONFIG_AMD_UCODE_PATCH_FILE
-	default none
-	export used
-	format "\"%s\""
-	comment "name of the microcode patch file"	
-end
-
-define CONFIG_K8_MEM_BANK_B_ONLY
-	default 0
-	export always
-	comment "use AMD K8's memory bank B only to make a 64bit memory system and memory bank A is free, such as Filbert."
-end
-
-define CONFIG_VIDEO_MB
-        default 0
-        export always
-        comment "Integrated graphics with UMA has dynamic setup"
-end
-
-define CONFIG_GFXUMA
-        default 0
-        export always
-        comment "GFX UMA"
-end
-
-define CONFIG_HAVE_MAINBOARD_RESOURCES
-	default 0
-	export always
-	comment "Enable if the mainboard/chipset requires extra entries in the memory map"
-end
-
-define CONFIG_HAVE_LOW_TABLES
-	default 1
-	export always
-	comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
-end
-
-define CONFIG_WRITE_HIGH_TABLES
-	default 0
-	export always
-	comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
-end
-
-define CONFIG_SPLASH_GRAPHIC
-	default 0
-	export used
-	comment "Paint a splash screen"
-end
-
-define CONFIG_GX1_VIDEO
-	default 0
-	export used
-	comment "Build in GX1's graphic support"
-end
-
-define CONFIG_GX1_VIDEOMODE
-	default none
-	export used
-	comment "Define video mode after reset"
-# could be
-# 0 for 640x480
-# 1 for 800x600
-# 2 for 1024x768
-# 3 for 1280x960
-# 4 for 1280x1024
-end
-
-define CONFIG_PCIE_CONFIGSPACE_HOLE
-	default 0
-	export always
-	comment "Leave a hole for PCIe config space in the device allocator"
-end
-
-define CONFIG_ID_SECTION_OFFSET
-	default 0x10
-	export always
-	comment "Offset of the .id section. Only needs to change if something like a romstrap is in the way"
-end
diff --git a/src/console/Config.lb b/src/console/Config.lb
deleted file mode 100644
index eda9cf4..0000000
--- a/src/console/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_CONSOLE_LOGBUF
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-object printk.o
-if CONFIG_CONSOLE_SERIAL8250
-	driver uart8250_console.o
-end
-if CONFIG_USBDEBUG_DIRECT
-	driver usbdebug_direct_console.o
-end
-if CONFIG_CONSOLE_VGA
-	driver vga_console.o
-end
-if CONFIG_CONSOLE_BTEXT
-	driver btext_console.o
-	driver font-8x16.o
-end
-if CONFIG_CONSOLE_LOGBUF
-	driver logbuf_console.o
-end
-
-object console.o
-object vtxprintf.o
-object vsprintf.o
-
-initobject vtxprintf.o
diff --git a/src/cpu/amd/dualcore/Config.lb b/src/cpu/amd/dualcore/Config.lb
deleted file mode 100644
index acc5d2e..0000000
--- a/src/cpu/amd/dualcore/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object amd_sibling.o
diff --git a/src/cpu/amd/microcode/Config.lb b/src/cpu/amd/microcode/Config.lb
deleted file mode 100644
index f19d210..0000000
--- a/src/cpu/amd/microcode/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object microcode.o
\ No newline at end of file
diff --git a/src/cpu/amd/model_10xxx/Config.lb b/src/cpu/amd/model_10xxx/Config.lb
deleted file mode 100644
index 47f1600..0000000
--- a/src/cpu/amd/model_10xxx/Config.lb
+++ /dev/null
@@ -1,38 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_HAVE_MOVNTI
-uses CONFIG_CPU_ADDR_BITS
-
-default CONFIG_HAVE_INIT_TIMER=1
-default CONFIG_HAVE_MOVNTI=1
-default CONFIG_CPU_ADDR_BITS=48
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/pae
-dir /cpu/x86/smm
-dir /cpu/amd/mtrr
-dir /cpu/amd/quadcore
-dir /cpu/amd/microcode
-driver model_10xxx_init.o
-object update_microcode.o
-object apic_timer.o
-object processor_name.o
diff --git a/src/cpu/amd/model_fxx/Config.lb b/src/cpu/amd/model_fxx/Config.lb
deleted file mode 100644
index fad7560..0000000
--- a/src/cpu/amd/model_fxx/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_HAVE_MOVNTI
-uses CONFIG_CPU_ADDR_BITS
-
-default CONFIG_HAVE_INIT_TIMER=1
-default CONFIG_HAVE_MOVNTI=1
-default CONFIG_CPU_ADDR_BITS=40
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/pae
-dir /cpu/x86/smm
-dir /cpu/amd/mtrr
-dir /cpu/amd/dualcore
-dir /cpu/amd/microcode
-driver model_fxx_init.o
-object apic_timer.o
-object model_fxx_update_microcode.o
-object processor_name.o
-object powernow_acpi.o
diff --git a/src/cpu/amd/model_gx1/Config.lb b/src/cpu/amd/model_gx1/Config.lb
deleted file mode 100644
index d04be3d..0000000
--- a/src/cpu/amd/model_gx1/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_gx1_init.o
diff --git a/src/cpu/amd/model_gx2/Config.lb b/src/cpu/amd/model_gx2/Config.lb
deleted file mode 100644
index 0f57790..0000000
--- a/src/cpu/amd/model_gx2/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_gx2_init.o
-object cpubug.o
-object vsmsetup.o
diff --git a/src/cpu/amd/model_lx/Config.lb b/src/cpu/amd/model_lx/Config.lb
deleted file mode 100644
index 25324e7..0000000
--- a/src/cpu/amd/model_lx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-driver model_lx_init.o
-object cpubug.o
-object vsmsetup.o
diff --git a/src/cpu/amd/mtrr/Config.lb b/src/cpu/amd/mtrr/Config.lb
deleted file mode 100644
index f042c2c..0000000
--- a/src/cpu/amd/mtrr/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-dir /cpu/x86/mtrr
-object amd_mtrr.o
diff --git a/src/cpu/amd/quadcore/Config.lb b/src/cpu/amd/quadcore/Config.lb
deleted file mode 100644
index 680436f..0000000
--- a/src/cpu/amd/quadcore/Config.lb
+++ /dev/null
@@ -1,20 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-object amd_sibling.o
diff --git a/src/cpu/amd/sc520/Config.lb b/src/cpu/amd/sc520/Config.lb
deleted file mode 100644
index 10bb996..0000000
--- a/src/cpu/amd/sc520/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object sc520.o
-
diff --git a/src/cpu/amd/socket_754/Config.lb b/src/cpu/amd/socket_754/Config.lb
deleted file mode 100644
index bd96105..0000000
--- a/src/cpu/amd/socket_754/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-
-config chip.h
-object socket_754.o
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_939/Config.lb b/src/cpu/amd/socket_939/Config.lb
deleted file mode 100644
index 963a27e..0000000
--- a/src/cpu/amd/socket_939/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-
-object socket_939.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_940/Config.lb b/src/cpu/amd/socket_940/Config.lb
deleted file mode 100644
index 34d1405..0000000
--- a/src/cpu/amd/socket_940/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-
-object socket_940.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_AM2/Config.lb b/src/cpu/amd/socket_AM2/Config.lb
deleted file mode 100644
index 095643b..0000000
--- a/src/cpu/amd/socket_AM2/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0004  #DDR2 unbuffered
-default CONFIG_CPU_SOCKET_TYPE=0x11
-
-object socket_AM2.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_AM2r2/Config.lb b/src/cpu/amd/socket_AM2r2/Config.lb
deleted file mode 100644
index 2d3d12e..0000000
--- a/src/cpu/amd/socket_AM2r2/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_PCI_IO_CFG_EXT
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_HT3_SUPPORT
-uses CONFIG_EXT_RT_TBL_SUPPORT
-uses CONFIG_EXT_CONF_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-uses CONFIG_CBB
-uses CONFIG_CDB
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-config chip.h
-
-default CONFIG_PCI_IO_CFG_EXT=1
-
-default CONFIG_HT3_SUPPORT=1
-default CONFIG_EXT_RT_TBL_SUPPORT=0
-default CONFIG_EXT_CONF_SUPPORT=0
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x11
-
-if CONFIG_EXT_RT_TBL_SUPPORT
-	default CONFIG_CBB=0xff
-	default CONFIG_CDB=0
-end
-
-#default CONFIG_MMCONF_SUPPORT=1
-#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
-
-object socket_AM2r2.o
-
-dir /cpu/amd/model_10xxx
diff --git a/src/cpu/amd/socket_F/Config.lb b/src/cpu/amd/socket_F/Config.lb
deleted file mode 100644
index 72f2a1b..0000000
--- a/src/cpu/amd/socket_F/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x10
-
-object socket_F.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/amd/socket_F_1207/Config.lb b/src/cpu/amd/socket_F_1207/Config.lb
deleted file mode 100644
index 447b6cb..0000000
--- a/src/cpu/amd/socket_F_1207/Config.lb
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_PCI_IO_CFG_EXT
-uses CONFIG_MMCONF_SUPPORT
-uses CONFIG_HT3_SUPPORT
-uses CONFIG_EXT_RT_TBL_SUPPORT
-uses CONFIG_EXT_CONF_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-uses CONFIG_CBB
-uses CONFIG_CDB
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-config chip.h
-
-default CONFIG_PCI_IO_CFG_EXT=1
-
-default CONFIG_HT3_SUPPORT=1
-default CONFIG_EXT_RT_TBL_SUPPORT=0
-default CONFIG_EXT_CONF_SUPPORT=0
-default CONFIG_DIMM_SUPPORT=0x0104  #DDR2 and REG
-default CONFIG_CPU_SOCKET_TYPE=0x10
-
-if CONFIG_EXT_RT_TBL_SUPPORT
-	default CONFIG_CBB=0xff
-	default CONFIG_CDB=0
-end
-
-#default CONFIG_MMCONF_SUPPORT=1
-#default CONFIG_MMCONF_SUPPORT_DEFAULT=1
-
-object socket_F_1207.o
-
-dir /cpu/amd/model_10xxx
diff --git a/src/cpu/amd/socket_S1G1/Config.lb b/src/cpu/amd/socket_S1G1/Config.lb
deleted file mode 100644
index 6aa6b5a..0000000
--- a/src/cpu/amd/socket_S1G1/Config.lb
+++ /dev/null
@@ -1,16 +0,0 @@
-uses CONFIG_K8_REV_F_SUPPORT
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_DIMM_SUPPORT
-uses CONFIG_CPU_SOCKET_TYPE
-
-config chip.h
-
-default CONFIG_K8_REV_F_SUPPORT=1
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-default CONFIG_DIMM_SUPPORT=0x0204  #DDR2 and REG, S1G1
-default CONFIG_CPU_SOCKET_TYPE=0x12
-
-object socket_S1G1.o
-
-dir /cpu/amd/model_fxx
diff --git a/src/cpu/emulation/qemu-x86/Config.lb b/src/cpu/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 4a0c2c8..0000000
--- a/src/cpu/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object northbridge.o
diff --git a/src/cpu/intel/bga956/Config.lb b/src/cpu/intel/bga956/Config.lb
deleted file mode 100644
index f334dce..0000000
--- a/src/cpu/intel/bga956/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object bga956.o
-dir /cpu/intel/model_1067x
diff --git a/src/cpu/intel/ep80579/Config.lb b/src/cpu/intel/ep80579/Config.lb
deleted file mode 100644
index 04d2e3f..0000000
--- a/src/cpu/intel/ep80579/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Arastra, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License version 2 as
-## published by the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object ep80579.o
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver ep80579_init.o
diff --git a/src/cpu/intel/hyperthreading/Config.lb b/src/cpu/intel/hyperthreading/Config.lb
deleted file mode 100644
index dce4044..0000000
--- a/src/cpu/intel/hyperthreading/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object intel_sibling.o
diff --git a/src/cpu/intel/microcode/Config.lb b/src/cpu/intel/microcode/Config.lb
deleted file mode 100644
index f19d210..0000000
--- a/src/cpu/intel/microcode/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object microcode.o
\ No newline at end of file
diff --git a/src/cpu/intel/model_1067x/Config.lb b/src/cpu/intel/model_1067x/Config.lb
deleted file mode 100644
index 71b83a4..0000000
--- a/src/cpu/intel/model_1067x/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_1067x_init.o
diff --git a/src/cpu/intel/model_106cx/Config.lb b/src/cpu/intel/model_106cx/Config.lb
deleted file mode 100644
index 1df2919..0000000
--- a/src/cpu/intel/model_106cx/Config.lb
+++ /dev/null
@@ -1,31 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-dir /cpu/intel/speedstep
-driver model_106cx_init.o
diff --git a/src/cpu/intel/model_69x/Config.lb b/src/cpu/intel/model_69x/Config.lb
deleted file mode 100644
index c558cd0..0000000
--- a/src/cpu/intel/model_69x/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_69x_init.o
diff --git a/src/cpu/intel/model_6dx/Config.lb b/src/cpu/intel/model_6dx/Config.lb
deleted file mode 100644
index 802dcd0..0000000
--- a/src/cpu/intel/model_6dx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_6dx_init.o
diff --git a/src/cpu/intel/model_6ex/Config.lb b/src/cpu/intel/model_6ex/Config.lb
deleted file mode 100644
index 1dac2f2..0000000
--- a/src/cpu/intel/model_6ex/Config.lb
+++ /dev/null
@@ -1,12 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-dir /cpu/intel/speedstep
-driver model_6ex_init.o
diff --git a/src/cpu/intel/model_6fx/Config.lb b/src/cpu/intel/model_6fx/Config.lb
deleted file mode 100644
index ae3b6bd..0000000
--- a/src/cpu/intel/model_6fx/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_6fx_init.o
diff --git a/src/cpu/intel/model_6xx/Config.lb b/src/cpu/intel/model_6xx/Config.lb
deleted file mode 100644
index 3419512..0000000
--- a/src/cpu/intel/model_6xx/Config.lb
+++ /dev/null
@@ -1,7 +0,0 @@
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_6xx_init.o
diff --git a/src/cpu/intel/model_f0x/Config.lb b/src/cpu/intel/model_f0x/Config.lb
deleted file mode 100644
index b790c72..0000000
--- a/src/cpu/intel/model_f0x/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_f0x_init.o
diff --git a/src/cpu/intel/model_f1x/Config.lb b/src/cpu/intel/model_f1x/Config.lb
deleted file mode 100644
index 26fbeef..0000000
--- a/src/cpu/intel/model_f1x/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_f1x_init.o
diff --git a/src/cpu/intel/model_f2x/Config.lb b/src/cpu/intel/model_f2x/Config.lb
deleted file mode 100644
index 7843d4a..0000000
--- a/src/cpu/intel/model_f2x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f2x_init.o
diff --git a/src/cpu/intel/model_f3x/Config.lb b/src/cpu/intel/model_f3x/Config.lb
deleted file mode 100644
index 214c689..0000000
--- a/src/cpu/intel/model_f3x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f3x_init.o
diff --git a/src/cpu/intel/model_f4x/Config.lb b/src/cpu/intel/model_f4x/Config.lb
deleted file mode 100644
index adfc7d2..0000000
--- a/src/cpu/intel/model_f4x/Config.lb
+++ /dev/null
@@ -1,10 +0,0 @@
-uses CONFIG_HAVE_MOVNTI
-default CONFIG_HAVE_MOVNTI=1
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-dir /cpu/intel/hyperthreading
-driver model_f4x_init.o
diff --git a/src/cpu/intel/slot_2/Config.lb b/src/cpu/intel/slot_2/Config.lb
deleted file mode 100644
index f39eb77..0000000
--- a/src/cpu/intel/slot_2/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object slot_2.o
-dir /cpu/intel/model_6xx
diff --git a/src/cpu/intel/socket_441/Config.lb b/src/cpu/intel/socket_441/Config.lb
deleted file mode 100644
index 6e8b65e..0000000
--- a/src/cpu/intel/socket_441/Config.lb
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-config chip.h
-object socket_441.o
-dir /cpu/intel/model_106cx
diff --git a/src/cpu/intel/socket_PGA370/Config.lb b/src/cpu/intel/socket_PGA370/Config.lb
deleted file mode 100644
index 8db263b..0000000
--- a/src/cpu/intel/socket_PGA370/Config.lb
+++ /dev/null
@@ -1,3 +0,0 @@
-config chip.h
-object socket_PGA370.o
-dir /cpu/intel/model_6xx
diff --git a/src/cpu/intel/socket_mFCPGA478/Config.lb b/src/cpu/intel/socket_mFCPGA478/Config.lb
deleted file mode 100644
index baeda00..0000000
--- a/src/cpu/intel/socket_mFCPGA478/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-config chip.h
-object socket_mFCPGA478.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
-dir /cpu/intel/model_6ex
-dir /cpu/intel/model_6fx
diff --git a/src/cpu/intel/socket_mPGA478/Config.lb b/src/cpu/intel/socket_mPGA478/Config.lb
deleted file mode 100644
index a68eeeb..0000000
--- a/src/cpu/intel/socket_mPGA478/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mPGA478.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
diff --git a/src/cpu/intel/socket_mPGA479M/Config.lb b/src/cpu/intel/socket_mPGA479M/Config.lb
deleted file mode 100644
index 70eda9a..0000000
--- a/src/cpu/intel/socket_mPGA479M/Config.lb
+++ /dev/null
@@ -1,4 +0,0 @@
-config chip.h
-object socket_mPGA479M.o
-dir /cpu/intel/model_69x
-dir /cpu/intel/model_6dx
diff --git a/src/cpu/intel/socket_mPGA603/Config.lb b/src/cpu/intel/socket_mPGA603/Config.lb
deleted file mode 100644
index fa66e44..0000000
--- a/src/cpu/intel/socket_mPGA603/Config.lb
+++ /dev/null
@@ -1,6 +0,0 @@
-config chip.h
-object socket_mPGA603_400Mhz.o
-dir /cpu/intel/model_f0x
-dir /cpu/intel/model_f1x
-dir /cpu/intel/model_f2x
-
diff --git a/src/cpu/intel/socket_mPGA604/Config.lb b/src/cpu/intel/socket_mPGA604/Config.lb
deleted file mode 100644
index 21276eb..0000000
--- a/src/cpu/intel/socket_mPGA604/Config.lb
+++ /dev/null
@@ -1,5 +0,0 @@
-config chip.h
-object socket_mPGA604.o
-dir /cpu/intel/model_f2x
-dir /cpu/intel/model_f3x
-dir /cpu/intel/model_f4x
diff --git a/src/cpu/intel/speedstep/Config.lb b/src/cpu/intel/speedstep/Config.lb
deleted file mode 100644
index 6a75160..0000000
--- a/src/cpu/intel/speedstep/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object acpi.o
diff --git a/src/cpu/via/model_c3/Config.lb b/src/cpu/via/model_c3/Config.lb
deleted file mode 100644
index 0bb6b96..0000000
--- a/src/cpu/via/model_c3/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# This file is part of the coreboot project.
-# 
-# (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_c3_init.o
diff --git a/src/cpu/via/model_c7/Config.lb b/src/cpu/via/model_c7/Config.lb
deleted file mode 100644
index de22d8a..0000000
--- a/src/cpu/via/model_c7/Config.lb
+++ /dev/null
@@ -1,28 +0,0 @@
-#
-# This file is part of the coreboot project.
-# 
-# (C) 2007-2008 coresystems GmbH
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; version 2 of
-# the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
-# MA 02110-1301 USA
-#
-
-dir /cpu/x86/tsc
-dir /cpu/x86/mtrr
-dir /cpu/x86/lapic
-dir /cpu/x86/cache
-dir /cpu/x86/smm
-dir /cpu/intel/microcode
-driver model_c7_init.o
diff --git a/src/cpu/x86/cache/Config.lb b/src/cpu/x86/cache/Config.lb
deleted file mode 100644
index e39bb2d..0000000
--- a/src/cpu/x86/cache/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object cache.o
diff --git a/src/cpu/x86/lapic/Config.lb b/src/cpu/x86/lapic/Config.lb
deleted file mode 100644
index 9491687..0000000
--- a/src/cpu/x86/lapic/Config.lb
+++ /dev/null
@@ -1,11 +0,0 @@
-uses CONFIG_UDELAY_LAPIC
-
-object lapic.o
-object lapic_cpu_init.o
-object secondary.S
-
-if CONFIG_UDELAY_LAPIC
-	default CONFIG_HAVE_INIT_TIMER=1
-	object apic_timer.o
-end
-
diff --git a/src/cpu/x86/mtrr/Config.lb b/src/cpu/x86/mtrr/Config.lb
deleted file mode 100644
index df5c16f..0000000
--- a/src/cpu/x86/mtrr/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object mtrr.o
\ No newline at end of file
diff --git a/src/cpu/x86/pae/Config.lb b/src/cpu/x86/pae/Config.lb
deleted file mode 100644
index 45e7f57..0000000
--- a/src/cpu/x86/pae/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-object pgtbl.o
\ No newline at end of file
diff --git a/src/cpu/x86/smm/Config.lb b/src/cpu/x86/smm/Config.lb
deleted file mode 100644
index f725581..0000000
--- a/src/cpu/x86/smm/Config.lb
+++ /dev/null
@@ -1,48 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_HAVE_SMI_HANDLER
-
-if CONFIG_HAVE_SMI_HANDLER
-	object smmrelocate.S
-
-	smmobject smmhandler.S
-	smmobject smihandler.o
-	smmobject smiutil.o
-
-	makerule smm.o
-		depends	"$(SMM-OBJECTS) src/console/printk.o src/console/vtxprintf.o $(LIBGCC_FILE_NAME)" 
-		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -r -o $@ $^"
-	end
-
-	makerule smm
-		depends	"smm.o $(TOP)/src/cpu/x86/smm/smm.ld ldoptions" 
-		action	"$(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -static -o smm.elf -T $(TOP)/src/cpu/x86/smm/smm.ld smm.o"
-		action 	"$(CONFIG_CROSS_COMPILE)nm -n smm.elf | sort > smm.map"
-		action  "$(CONFIG_OBJCOPY) -O binary smm.elf smm"
-	end
-
-	makerule smm_bin.c
-		depends "smm"
-		action "(echo 'unsigned char smm[] = {'; od -vtx1 smm | sed -e 's,^[0-9]* *,,' -e 's:[0-9a-f][0-9a-f] :0x&,:g' -e 's:[0-9a-f][0-9a-f]$$:0x&,:'; echo '}; unsigned int smm_len = '; wc -c smm |awk '{print $$1;}' ; echo ';')  > smm_bin.c"
-	end
-
-	object ./smm_bin.o
-end
diff --git a/src/cpu/x86/tsc/Config.lb b/src/cpu/x86/tsc/Config.lb
deleted file mode 100644
index 21aa9a4..0000000
--- a/src/cpu/x86/tsc/Config.lb
+++ /dev/null
@@ -1,9 +0,0 @@
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_INIT_TIMER
-
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-if CONFIG_UDELAY_TSC 
-	default CONFIG_HAVE_INIT_TIMER=1
-	object delay_tsc.o  
-end
diff --git a/src/devices/Config.lb b/src/devices/Config.lb
deleted file mode 100644
index a8c08d8..0000000
--- a/src/devices/Config.lb
+++ /dev/null
@@ -1,25 +0,0 @@
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-
-object device.o
-object root_device.o
-object device_util.o
-object pci_device.o
-object hypertransport.o
-object pcix_device.o
-object pciexp_device.o
-object agp_device.o
-object cardbus_device.o
-object pnp_device.o
-object pci_ops.o
-object smbus_ops.o
-
-if CONFIG_PCI_ROM_RUN
-	object pci_rom.o
-	dir ../../util/x86emu
-else
-if CONFIG_VGA_ROM_RUN
-	object pci_rom.o
-	dir ../../util/x86emu
-end
-end
diff --git a/src/drivers/ati/ragexl/Config.lb b/src/drivers/ati/ragexl/Config.lb
deleted file mode 100644
index dc9ca32..0000000
--- a/src/drivers/ati/ragexl/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver xlinit.o
diff --git a/src/drivers/emulation/qemu/Config.lb b/src/drivers/emulation/qemu/Config.lb
deleted file mode 100644
index 3a8d35a..0000000
--- a/src/drivers/emulation/qemu/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver init.o
diff --git a/src/drivers/generic/debug/Config.lb b/src/drivers/generic/debug/Config.lb
deleted file mode 100644
index df69ac1..0000000
--- a/src/drivers/generic/debug/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object debug_dev.o
diff --git a/src/drivers/generic/generic/Config.lb b/src/drivers/generic/generic/Config.lb
deleted file mode 100644
index e69de29..0000000
--- a/src/drivers/generic/generic/Config.lb
+++ /dev/null
diff --git a/src/drivers/i2c/adm1026/Config.lb b/src/drivers/i2c/adm1026/Config.lb
deleted file mode 100644
index 52cbfaa..0000000
--- a/src/drivers/i2c/adm1026/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object adm1026.o
diff --git a/src/drivers/i2c/adm1027/Config.lb b/src/drivers/i2c/adm1027/Config.lb
deleted file mode 100644
index 395ebab..0000000
--- a/src/drivers/i2c/adm1027/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object adm1027.o
diff --git a/src/drivers/i2c/i2cmux/Config.lb b/src/drivers/i2c/i2cmux/Config.lb
deleted file mode 100644
index 6bce919..0000000
--- a/src/drivers/i2c/i2cmux/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object i2cmux.o
diff --git a/src/drivers/i2c/i2cmux2/Config.lb b/src/drivers/i2c/i2cmux2/Config.lb
deleted file mode 100644
index a0d83ba..0000000
--- a/src/drivers/i2c/i2cmux2/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object i2cmux2.o
diff --git a/src/drivers/i2c/lm63/Config.lb b/src/drivers/i2c/lm63/Config.lb
deleted file mode 100644
index 959c7af..0000000
--- a/src/drivers/i2c/lm63/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-object lm63.o
diff --git a/src/drivers/si/3114/Config.lb b/src/drivers/si/3114/Config.lb
deleted file mode 100644
index a7ebf67..0000000
--- a/src/drivers/si/3114/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver si_sata.o
diff --git a/src/drivers/trident/blade3d/Config.lb b/src/drivers/trident/blade3d/Config.lb
deleted file mode 100644
index 0b2416d..0000000
--- a/src/drivers/trident/blade3d/Config.lb
+++ /dev/null
@@ -1 +0,0 @@
-driver blade3d.o
diff --git a/src/lib/Config.lb b/src/lib/Config.lb
deleted file mode 100644
index 7af325d..0000000
--- a/src/lib/Config.lb
+++ /dev/null
@@ -1,33 +0,0 @@
-uses CONFIG_USE_INIT
-uses CONFIG_USBDEBUG_DIRECT
-
-object clog2.o
-object uart8250.o
-
-if CONFIG_USBDEBUG_DIRECT
-	object usbdebug_direct.o
-end
-
-object memset.o
-object memcpy.o
-object memcmp.o
-object memmove.o
-object malloc.o
-object delay.o
-object fallback_boot.o
-object compute_ip_checksum.o
-object version.o
-object gcc.o
-object cbfs.o
-object lzma.o
-object cbmem.o
-
-# Force version.o to recompile every time
-makedefine .PHONY : version.o
-
-initobject uart8250.o
-initobject memset.o
-initobject memcpy.o
-initobject memcmp.o
-
-
diff --git a/src/mainboard/a-trend/atc-6220/Config.lb b/src/mainboard/a-trend/atc-6220/Config.lb
deleted file mode 100644
index da9f349..0000000
--- a/src/mainboard/a-trend/atc-6220/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/a-trend/atc-6220/Options.lb b/src/mainboard/a-trend/atc-6220/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/a-trend/atc-6220/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/a-trend/atc-6240/Config.lb b/src/mainboard/a-trend/atc-6240/Config.lb
deleted file mode 100644
index 1f8a889..0000000
--- a/src/mainboard/a-trend/atc-6240/Config.lb
+++ /dev/null
@@ -1,142 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83627hf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-            io 0x60 = 0x00
-          end
-          device pnp 3f0.7 on		# Game port / MIDI / GPIO 1
-            io 0x60 = 0x201
-            io 0x62 = 0x330
-            irq 0x70 = 9
-          end
-          device pnp 3f0.8 off		# GPIO 2 / WDT
-          end
-          device pnp 3f0.9 off		# GPIO 3
-          end
-          device pnp 3f0.a off		# ACPI
-          end
-          device pnp 3f0.b off		# HWM (TODO)
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci c.0 on end		# Onboard audio (ES1371)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/a-trend/atc-6240/Options.lb b/src/mainboard/a-trend/atc-6240/Options.lb
deleted file mode 100644
index 7930819..0000000
--- a/src/mainboard/a-trend/atc-6240/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/abit/be6-ii_v2_0/Config.lb b/src/mainboard/abit/be6-ii_v2_0/Config.lb
deleted file mode 100644
index 58193b8..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE, UDMA/33 (part of 82371EB)
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      device pci 13.0 on end		# IDE, UDMA/66 (HPT366 controller)
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/abit/be6-ii_v2_0/Options.lb b/src/mainboard/abit/be6-ii_v2_0/Options.lb
deleted file mode 100644
index c415fd2..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024		# Override this in targets/*/Config.lb.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 9		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
-default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
-
-end
diff --git a/src/mainboard/advantech/pcm-5820/Config.lb b/src/mainboard/advantech/pcm-5820/Config.lb
deleted file mode 100644
index 44ec55de..0000000
--- a/src/mainboard/advantech/pcm-5820/Config.lb
+++ /dev/null
@@ -1,129 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/winbond/w83977f	# SUper I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.4 on		# RTC / On-Now control
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# IR
-            # TODO?
-          end
-          device pnp 3f0.7 on		# GPIO 1
-            # TODO?
-          end
-          device pnp 3f0.8 on		# GPIO 2
-            # TODO?
-          end
-        end
-      end
-      device pci 12.1 on end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio (onboard)
-      device pci 12.4 on end		# VGA
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/advantech/pcm-5820/Options.lb b/src/mainboard/advantech/pcm-5820/Options.lb
deleted file mode 100644
index 684e4dc..0000000
--- a/src/mainboard/advantech/pcm-5820/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2		# Override this in targets/*/Config.lb.
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/amd/db800/Config.lb b/src/mainboard/amd/db800/Config.lb
deleted file mode 100644
index de22906..0000000
--- a/src/mainboard/amd/db800/Config.lb
+++ /dev/null
@@ -1,152 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end				# Northbridge
-		device pci 1.1 on end				# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK
-			register "lpc_serirq_enable" = "0x0000105a"
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0"	# 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "1"	# 0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci d.0 on end			# Ethernet
-			device pci e.0 on end			# Slot1
-			device pci f.0 on			# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off	# Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off	# Parallel port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on	# Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 off end	# Com2
-					device pnp 2e.5 on	# Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off end	# CIR
-					device pnp 2e.7 off end	# GAME_MIDI_GIPO1
-					device pnp 2e.8 off end	# GPIO2
-					device pnp 2e.9 off end	# GPIO3
-					device pnp 2e.a off end	# ACPI
-					device pnp 2e.b off end	# HW Monitor
-				end
-			end
-			device pci f.2 on end			# IDE Controller
-			device pci f.3 on end			# Audio
-			device pci f.4 on end			# OHCI
-			device pci f.5 on end			# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/amd/db800/Options.lb b/src/mainboard/amd/db800/Options.lb
deleted file mode 100644
index 5ec7b1e..0000000
--- a/src/mainboard/amd/db800/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=4
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 32768
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/dbm690t/Config.lb b/src/mainboard/amd/dbm690t/Config.lb
deleted file mode 100644
index fde48a1..0000000
--- a/src/mainboard/amd/dbm690t/Config.lb
+++ /dev/null
@@ -1,258 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_S1G1
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end
-					end # SM
-					device pci 14.1 on end # IDE    0x438c
-					device pci 14.2 on end # HDA    0x4383
-					device pci 14.3 on # LPC	0x438d
-						chip superio/ite/it8712f
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.2 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.4 off end #  EC
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.6 on #  Mouse
-								irq 0x70 = 12
-							end
-							device pnp 2e.7 off #  GPIO, must be closed for unresolved reason.
-							end
-							device pnp 2e.8 off #  MIDI
-								io 0x60 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.9 off #  GAME
-								io 0x60 = 0x220
-							end
-							device pnp 2e.a off end #  CIR
-						end	#superio/ite/it8712f
-					end		#LPC
-					device pci 14.4 on end # PCI 0x4384
-					device pci 14.5 on end # ACI 0x4382
-					device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/dbm690t/Options.lb b/src/mainboard/amd/dbm690t/Options.lb
deleted file mode 100644
index d5d54f9..0000000
--- a/src/mainboard/amd/dbm690t/Options.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="dbm690t"
-default CONFIG_MAINBOARD_VENDOR="amd"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/norwich/Config.lb b/src/mainboard/amd/norwich/Config.lb
deleted file mode 100644
index 5f0dc33..0000000
--- a/src/mainboard/amd/norwich/Config.lb
+++ /dev/null
@@ -1,125 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-#not in serengeti_cheetah mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "1"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci b.0 on end	# Slot 3
-			device pci c.0 on end	# Slot 4
-			device pci d.0 on end	# Slot 1
-			device pci e.0 on end	# Slot 2
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-end
-
diff --git a/src/mainboard/amd/norwich/Options.lb b/src/mainboard/amd/norwich/Options.lb
deleted file mode 100644
index 0ca2026..0000000
--- a/src/mainboard/amd/norwich/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=6
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/pistachio/Config.lb b/src/mainboard/amd/pistachio/Config.lb
deleted file mode 100644
index 1f59668..0000000
--- a/src/mainboard/amd/pistachio/Config.lb
+++ /dev/null
@@ -1,218 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE
-	object get_bus_conf.o
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	object acpi_tables.o
-	object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/acpi/*.asl"
-		action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/acpi/dsdt.asl"
-		action  "mv dsdt.hex dsdt.c"
-	end
-	object ./dsdt.o
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-	end
-
-	if CONFIG_USE_INIT
-		ldscript      /cpu/amd/car/cache_as_ram.lds
-	end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-#The variables belong to mainboard are defined here.
-
-#Define gpp_configuration,	A=0, B=1, C=2, D=3, E=4(default)
-#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7)
-#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3,
-#			1: the system allows a PCIE link to be established on Dev2 or Dev3.
-#Define gfx_dual_slot, 0: single slot, 1: dual slot
-#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable
-#Define gfx_tmds, 0: didn't support TMDS, 1: support
-#Define gfx_compliance, 0: didn't support compliance, 1: support
-#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration
-#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_AM2
-		device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  southbridge, K8 HT Configuration
-				chip southbridge/amd/rs690
-					device pci 0.0 on end # HT  	0x7910
-				#	device pci 0.1 off end # CLK
-					device pci 1.0 on  # Internal Graphics P2P bridge 0x7912
-						device pci 5.0 on end	# Internal Graphics 0x791F
-					end
-					device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913
-					device pci 3.0 off end # PCIE P2P bridge	0x791b
-					device pci 4.0 on end # PCIE P2P bridge 0x7914
-					device pci 5.0 on end # PCIE P2P bridge 0x7915
-					device pci 6.0 on end # PCIE P2P bridge 0x7916
-					device pci 7.0 on end # PCIE P2P bridge 0x7917
-					device pci 8.0 off end # NB/SB Link P2P bridge
-					register "gpp_configuration" = "4"
-					register "port_enable" = "0xfc"
-					register "gfx_dev2_dev3" = "1"
-					register "gfx_dual_slot" = "0"
-					register "gfx_lane_reversal" = "0"
-					register "gfx_tmds" = "0"
-					register "gfx_compliance" = "0"
-					register "gfx_reconfiguration" = "1"
-					register "gfx_link_width" = "0"
-				end
-				chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus
-					device pci 12.0 on end # SATA  0x4380
-					device pci 13.0 on end # USB   0x4387
-					device pci 13.1 on end # USB   0x4388
-					device pci 13.2 on end # USB   0x4389
-					device pci 13.3 on end # USB   0x438a
-					device pci 13.4 on end # USB   0x438b
-					device pci 13.5 on end # USB 2 0x4386
-	 				device pci 14.0 on # SM        0x4385
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 off end
-						end
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 off end
-						end
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 off end
-						end
-					end # SM
-				device pci 14.1 on end # IDE    0x438c
-				device pci 14.2 on end # HDA    0x4383
-				device pci 14.3 on end # LPC	0x438d
-				device pci 14.4 on end # PCI 0x4384
-				device pci 14.5 on end # ACI 0x4382
-				device pci 14.6 on end # MCI 0x438e
-					register "ide0_enable" = "1"
-					register "sata0_enable" = "1"
-					register "hda_viddid" = "0x10ec0882"
-				end	#southbridge/amd/sb600
-			end #  device pci 18.0
-
-			device pci 18.1 on end		# K8 Address Map
-			device pci 18.2 on end		# K8 DRAM Controller and HT Trace Mode
-			device pci 18.3 on end		# K8 Miscellaneous Control
-		end		#northbridge/amd/amdk8
-	end #pci_domain
-end		#northbridge/amd/amdk8/root_complex
-
diff --git a/src/mainboard/amd/pistachio/Options.lb b/src/mainboard/amd/pistachio/Options.lb
deleted file mode 100644
index 922edf5..0000000
--- a/src/mainboard/amd/pistachio/Options.lb
+++ /dev/null
@@ -1,301 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Advanced Micro Devices, Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-##
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VGA_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_VIDEO_MB
-uses CONFIG_GFXUMA
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VGA_ROM_RUN=1
-
-# BTDC: Only one HT device on Herring.
-#HT Unit ID offset
-#default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-default CONFIG_HT_CHAIN_UNITID_BASE=0x0
-
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x8000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="pistachio"
-default CONFIG_MAINBOARD_VENDOR="amd"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-##
-## coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_VIDEO_MB=1
-default CONFIG_GFXUMA=1
-default CONFIG_HAVE_MAINBOARD_RESOURCES=1
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/rumba/Config.lb b/src/mainboard/amd/rumba/Config.lb
deleted file mode 100644
index 9083949..0000000
--- a/src/mainboard/amd/rumba/Config.lb
+++ /dev/null
@@ -1,115 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx2
-	device apic_cluster 0 on
-		chip cpu/amd/model_gx2
-			device apic 0 on end
-		end
-	end
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-			register "lpc_serirq_enable" = "0x80"  # enabled with default timing
-        		device pci d.0 on end	# Realtek 8139 LAN
-        		device pci f.0 on end	# ISA Bridge
-        		device pci f.2 on end	# IDE Controller
-        		device pci f.3 on end 	# Audio
-        		device pci f.4 on end	# OHCI
-			device pci f.4 on end	# UHCI
-      		end
-    	end
-end
-
diff --git a/src/mainboard/amd/rumba/Options.lb b/src/mainboard/amd/rumba/Options.lb
deleted file mode 100644
index e6a9b48..0000000
--- a/src/mainboard/amd/rumba/Options.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/amd/serengeti_cheetah/Config.lb b/src/mainboard/amd/serengeti_cheetah/Config.lb
deleted file mode 100644
index 1e2f1b2..0000000
--- a/src/mainboard/amd/serengeti_cheetah/Config.lb
+++ /dev/null
@@ -1,358 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE 
-	object mptable.o 
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object irq_tables.o 
-end
-
-#if CONFIG_GENERATE_ACPI_TABLES
-#       object acpi_tables.o
-#       object fadt.o
-#       if CONFIG_SB_HT_CHAIN_ON_BUS0
-#               object dsdt_bus0.o
-#       else
-#               object dsdt.o
-#       end
-#       object ssdt.o
-#       if CONFIG_ACPI_SSDTX_NUM
-#                if CONFIG_SB_HT_CHAIN_ON_BUS0
-#                 object ssdt2_bus0.o
-#                else
-#                 object ssdt2.o
-#                end
-#       end
-#end
-
-if CONFIG_GENERATE_ACPI_TABLES
-        object acpi_tables.o
-        object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action  "mv dsdt_lb.hex dsdt.c"
-	end
-        object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-	
-        if CONFIG_ACPI_SSDTX_NUM
-            makerule ssdt2.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
-                        action  "mv pci2.hex ssdt2.c"
-            end
-            object ./ssdt2.o
-            makerule ssdt3.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
-                        action  "mv pci3.hex ssdt3.c"
-            end
-            object ./ssdt3.o
-            makerule ssdt4.c
-                        depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
-                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
-                        action  "mv pci4.hex ssdt4.c"
-            end
-            object ./ssdt4.o
-        end
-end
-
-	if CONFIG_USE_INIT
-		# compile cache_as_ram.c to auto.o
-		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else   
-		#compile cache_as_ram.c to auto.inc 
-		makerule ./cache_as_ram_auto.inc
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-		        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	makerule ./apc_auto.o
-		depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	end
-	ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for amd/serengeti_cheetah 
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_F
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8132
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 off #  Parallel Port
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.2 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.3 off #  Com2
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.5 on #  Keyboard
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-								irq 0x72 = 12
-							end
-                	        			device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-                	        			device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end						
-                	        			device pnp 2e.8 off end #  GPIO2
-                	        			device pnp 2e.9 off end #  GPIO3
-                	        			device pnp 2e.a off end #  ACPI
-                	        			device pnp 2e.b on #  HW Monitor
- 					 			io 0x60 = 0x290
-								irq 0x70 = 5
-                					end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-                                                chip drivers/i2c/i2cmux # pca9556 smbus mux
-                                                        device i2c 18 on #0 pca9516 1
-                                                                chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                        device i2c 18 on #1 pca9516 2
-                                                                chip drivers/generic/generic #dimm 1-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-2-0
-                                                                        device i2c 54 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-2-1
-                                                                        device i2c 55 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-3-0
-                                                                        device i2c 56 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-3-1
-                                                                        device i2c 57 on end
-                                                                end
-                                                        end
-						end
-					end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-                	                register "ide0_enable" = "1"
-                	                register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-                        device pci 18.0 on end
-                        device pci 18.0 on end  
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-                chip northbridge/amd/amdk8
-                        device pci 19.0 on #  northbridge
-                                chip southbridge/amd/amd8151
-                                        # the on/off keyword is mandatory
-                                        device pci 0.0 on end
-                                        device pci 1.0 on end
-                                end
-                        end #  device pci 19.0
-
-                        device pci 19.0 on end
-                        device pci 19.0 on end
-                        device pci 19.1 on end
-                        device pci 19.2 on end
-                        device pci 19.3 on end
-                end
-
-
-	end #pci_domain
-#        chip drivers/generic/debug
-#        	device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
-
diff --git a/src/mainboard/amd/serengeti_cheetah/Options.lb b/src/mainboard/amd/serengeti_cheetah/Options.lb
deleted file mode 100644
index a20289d..0000000
--- a/src/mainboard/amd/serengeti_cheetah/Options.lb
+++ /dev/null
@@ -1,325 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=8
-default CONFIG_MAX_PHYSICAL_CPUS=4
-default CONFIG_LOGICAL_CPUS=1
-
-default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x8
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead. 
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-
-##
-## for rev F training on AP purpose
-##
-default CONFIG_AP_CODE_IN_CAR=1
-default CONFIG_MEM_TRAIN_SEQ=1
-default CONFIG_WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="serengeti_cheetah"
-default CONFIG_MAINBOARD_VENDOR="AMD"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
deleted file mode 100644
index da52d4d..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Config.lb
+++ /dev/null
@@ -1,362 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE
-	object mptable.o
-end
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-if CONFIG_GENERATE_ACPI_TABLES
-	 object acpi_tables.o
-	 object fadt.o
-	makerule dsdt.c
-		depends "$(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action	"iasl -p $(CURDIR)/dsdt_lb -tc $(CONFIG_MAINBOARD)/dx/dsdt_lb.dsl"
-		action	"mv dsdt_lb.hex dsdt.c"
-	end
-	 object ./dsdt.o
-
-	#./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-
-	if CONFIG_ACPI_SSDTX_NUM
-	makerule ssdt2.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci2.asl"
-		action	"iasl -p $(CURDIR)/pci2 -tc $(CONFIG_MAINBOARD)/dx/pci2.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
-		action	"mv pci2.hex ssdt2.c"
-	end
-	object ./ssdt2.o
-	makerule ssdt3.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci3.asl"
-		action	"iasl -p $(CURDIR)/pci3 -tc $(CONFIG_MAINBOARD)/dx/pci3.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
-		action	"mv pci3.hex ssdt3.c"
-	end
-	object ./ssdt3.o
-	makerule ssdt4.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci4.asl"
-		action	"iasl -p $(CURDIR)/pci4 -tc $(CONFIG_MAINBOARD)/dx/pci4.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
-		action	"mv pci4.hex ssdt4.c"
-	end
-	object ./ssdt4.o
-	makerule ssdt5.c
-		depends "$(CONFIG_MAINBOARD)/dx/pci5.asl"
-		action	"iasl -p $(CURDIR)/pci5 -tc $(CONFIG_MAINBOARD)/dx/pci5.asl"
-		action	"perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
-		action	"mv pci5.hex ssdt5.c"
-	end
-	object ./ssdt5.o
-	 end
-end
-
-	if CONFIG_USE_INIT
-		# compile cache_as_ram.c to auto.o
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else
-		#compile cache_as_ram.c to auto.inc
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-	 makerule ./apc_auto.o
-		 depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-		 action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-	 end
-	 ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-	 if CONFIG_USE_INIT
-		 ldscript /cpu/x86/32bit/entry32.lds
-	 end
-
-	 if CONFIG_USE_INIT
-		 ldscript /cpu/amd/car/cache_as_ram.lds
-	 end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-dir /southbridge/amd/amd8151
-
-# sample config for amd/serengeti_cheetah_fam10
-chip northbridge/amd/amdfam10/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_F_1207  #L1 and DDR2
-			 device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdfam10
-			device pci 18.0 on #  northbridge
-				#  devices on link 0, link 0 == LDT 0
-				chip southbridge/amd/amd8132
-					# the on/off keyword is mandatory
-					device pci 0.0 on end
-					device pci 0.1 on end
-					device pci 1.0 on end
-					device pci 1.1 on end
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on end
-						device pci 0.1 on end
-						device pci 0.2 off end
-						device pci 1.0 off end
-					end
-					device pci 1.0 on
-						chip superio/winbond/w83627hf
-							device pnp 2e.0 off #  Floppy
-								io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off #  Parallel Port
-								io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 on #  Com1
-								io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.3 off #  Com2
-								io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.5 on #  Keyboard
-								io 0x60 = 0x60
-								io 0x62 = 0x64
-								irq 0x70 = 1
-								irq 0x72 = 12
-							end
-							device pnp 2e.6 off #  CIR
-								io 0x60 = 0x100
-							end
-							device pnp 2e.7 off #  GAME_MIDI_GIPO1
-								io 0x60 = 0x220
-								io 0x62 = 0x300
-								irq 0x70 = 9
-							end
-							device pnp 2e.8 off end #  GPIO2
-							device pnp 2e.9 off end #  GPIO3
-							device pnp 2e.a off end #  ACPI
-							device pnp 2e.b on #  HW Monitor
-								io 0x60 = 0x290
-								irq 0x70 = 5
-							end
-						end
-					end
-					device pci 1.1 on end
-					device pci 1.2 on end
-					device pci 1.3 on
-						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
-						chip drivers/i2c/i2cmux2 # pca9556 smbus mux
-							device i2c 18 on #0 pca9516 1
-								chip drivers/generic/generic #dimm 0-0-0
-									device i2c 50 on end
-								end
-								chip drivers/generic/generic #dimm 0-0-1
-									device i2c 51 on end
-								end
-								chip drivers/generic/generic #dimm 0-1-0
-									device i2c 52 on end
-								end
-								chip drivers/generic/generic #dimm 0-1-1
-									device i2c 53 on end
-								end
-							end
-							device i2c 18 on #1 pca9516 2
-								chip drivers/generic/generic #dimm 1-0-0
-									device i2c 50 on end
-								end
-								chip drivers/generic/generic #dimm 1-0-1
-									device i2c 51 on end
-								end
-								chip drivers/generic/generic #dimm 1-1-0
-									device i2c 52 on end
-								end
-								chip drivers/generic/generic #dimm 1-1-1
-									device i2c 53 on end
-								end
-							end
-						end
-						end
-					end # acpi
-					device pci 1.5 off end
-					device pci 1.6 off end
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0
-
-			device pci 18.0 on end
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-			device pci 18.4 on end
-#			device pci 00.5 on end
-		end
-	end #pci_domain
-	#for node 32 to node 63
-#	device pci_domain 0 on
-#		chip northbridge/amd/amdfam10
-#			  device pci 00.0 on end#  northbridge
-#			  device pci 00.0 on end
-#			  device pci 00.0 on end
-#			  device pci 00.0 on end
-#			  device pci 00.1 on end
-#			  device pci 00.2 on end
-#			  device pci 00.3 on end
-#			  device pci 00.4 on end
-#			 device pci 00.5 on end
-#		end
-#	end #pci_domain
-
-#	  chip drivers/generic/debug
-#		 device pnp 0.0 off end # chip name
-#		  device pnp 0.1 on end # pci_regs_all
-#		  device pnp 0.2 off end # mem
-#		  device pnp 0.3 off end # cpuid
-#		  device pnp 0.4 off end # smbus_regs_all
-#		  device pnp 0.5 off end # dual core msr
-#		  device pnp 0.6 off end # cache size
-#		  device pnp 0.7 off end # tsc
-#		  device pnp 0.8 off end # hard reset
-#		  device pnp 0.9 off end # mcp55
-#		  device pnp 0.a on end # GH ext table
-#	 end
-
-end
-
-
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb b/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
deleted file mode 100644
index 5a17e34..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/Options.lb
+++ /dev/null
@@ -1,365 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2007 Advanced Micro Devices, Inc.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-#
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_PCI_BUS_SEGN_BITS
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_AMDMCT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_AMD_UCODE_PATCH_FILE
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1024*1024
-
-##
-##
-#FALLBACK_SIZE_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 1024K - 8K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 8k
-default CONFIG_FAILOVER_SIZE=0x02000
-
-#more 1M for pgtbl
-#if there is RAM on node0, we need to set it to 32M, otherwise can not access CAR on node0, and RAM on node1 at same time.
-default CONFIG_RAMTOP=16384*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=1
-## extra SSDT num
-default CONFIG_ACPI_SSDTX_NUM=31
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_PHYSICAL_CPUS=8
-default CONFIG_MAX_CPUS=6 * CONFIG_MAX_PHYSICAL_CPUS
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=1
-default CONFIG_APIC_ID_OFFSET=0x00
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default CONFIG_HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-#it only be 0, 1, 2, 3, 4 and default is 0
-#default CONFIG_PCI_BUS_SEGN_BITS=3
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc4000
-default CONFIG_DCACHE_RAM_SIZE=0x0c000
-#default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x04000
-default CONFIG_USE_INIT=0
-
-#default CONFIG_AP_CODE_IN_CAR=1
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-default CONFIG_AMDMCT = 1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="Cheetah Fam10"
-default CONFIG_MAINBOARD_VENDOR="AMD"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-##
-## Set microcode patch file name
-##
-##	Barcelona rev DR-Ax:  "mc_patch_01000020.h"
-##	Barcelona rev DR-B0, B1, BA: "mc_patch_01000096.h"
-##	Barcelona rev DR-B2, B3: "mc_patch_01000095.h"
-##	Shanghai rev DA-C2: "mc_patch_0100009f.h"
-##
-default CONFIG_AMD_UCODE_PATCH_FILE="mc_patch_01000095.h"
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 768k heap
-##
-default CONFIG_HEAP_SIZE=0xc0000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00200000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable
-## ALERT      2   action must be taken immediately
-## CRIT       3   critical conditions
-## ERR        4   error conditions
-## WARNING    5   warning conditions
-## NOTICE     6   normal but significant condition
-## INFO       7   informational
-## CONFIG_DEBUG      8   debug-level messages
-## SPEW       9   Way too many details
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-default CONFIG_ID_SECTION_OFFSET=0x80
-
-### End Options.lb
-end
diff --git a/src/mainboard/arima/hdama/Config.lb b/src/mainboard/arima/hdama/Config.lb
deleted file mode 100644
index 13e351f..0000000
--- a/src/mainboard/arima/hdama/Config.lb
+++ /dev/null
@@ -1,297 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-if CONFIG_USE_INIT
-
-makerule ./auto.o
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-end
-
-else    
-                
-makerule ./auto.inc
-        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-end
-
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_USE_FALLBACK_IMAGE
-        mainboardinit cpu/x86/16bit/entry16.inc
-        ldscript /cpu/x86/16bit/entry16.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## Setup Cache-As-Ram
-##
-mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if CONFIG_USE_INIT
-initobject auto.o
-else
-mainboardinit ./auto.inc
-end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# config for arima/hdama
-chip northbridge/amd/amdk8/root_complex
-	device apic_cluster 0 on
-		chip cpu/amd/socket_940
-			device apic 0 on end
-		end
-	end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-				#  devices on link 0, link 0 == LDT 0 
-				chip southbridge/amd/amd8131
-					# the on/off keyword is mandatory
-					device pci 0.0 on	# PCIX bridge
-						## On board NIC A
-						#chip drivers/generic/generic
-						#	device pci 3.0 on	
-						#		irq 0 = 0x13
-						#	end
-						#end
-						## On board NIC B
-						#chip drivers/generic/generic
-						#	device pci 4.0 on
-						#		irq 0 = 0x13
-						#	end
-						#end
-						## PCI Slot 3
-						#chip drivers/generic/generic
-						#	device pci 1.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end 
-						## PCI Slot 4
-						#chip drivers/generic/generic
-						#	device pci 2.0 on
-						#		irq 0 = 0x12
-						#		irq 1 = 0x13
-						#		irq 2 = 0x10
-						#		irq 3 = 0x11
-						#	end
-						#end 
-					end
-					device pci 0.1 on end	# IOAPIC
-					device pci 1.0 on 	# PCIX bridge
-						## PCI Slot 1
-						#chip drivers/generic/generic
-						#	device pci 1.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end
-						## PCI Slot 2
-						#chip drivers/generic/generic
-						#	device pci 2.0 on
-						#		irq 0 = 0x12
-						#		irq 1 = 0x13
-						#		irq 2 = 0x10
-						#		irq 3 = 0x11
-						#	end
-						#end 
-					end
-					device pci 1.1 on end	# IOAPIC
-				end
-				chip southbridge/amd/amd8111
-					# this "device pci 0.0" is the parent of the next one
-					# PCI bridge
-					device pci 0.0 on
-						device pci 0.0 on  end	# USB0
-						device pci 0.1 on  end	# USB1
-						device pci 0.2 off end	# USB 2.0
-						device pci 1.0 off end	# LAN
-						device pci 6.0 on end # ATI Rage XL
-						## PCI Slot 5 (correct?)
-						#chip drivers/generic/generic
-						#	device pci 5.0 on
-						#		irq 0 = 0x11
-						#		irq 1 = 0x12
-						#		irq 2 = 0x13
-						#		irq 3 = 0x10
-						#	end
-						#end 
-						## PCI Slot 6 (correct?)
-						#chip drivers/generic/generic
-						#	device pci 4.0 on
-						#		irq 0 = 0x10
-						#		irq 1 = 0x11
-						#		irq 2 = 0x12
-						#		irq 3 = 0x13
-						#	end
-						#end 
-
-					end
-					# LPC bridge
-					device pci 1.0 on
-						chip superio/nsc/pc87360
-							device	pnp 2e.0 off  # Floppy 
-								 io 0x60 = 0x3f0
-								irq 0x70 = 6
-								drq 0x74 = 2
-							end
-							device pnp 2e.1 off  # Parallel Port
-								 io 0x60 = 0x378
-								irq 0x70 = 7
-							end
-							device pnp 2e.2 off # Com 2
-								 io 0x60 = 0x2f8
-								irq 0x70 = 3
-							end
-							device pnp 2e.3 on  # Com 1
-								 io 0x60 = 0x3f8
-								irq 0x70 = 4
-							end
-							device pnp 2e.4 off end # SWC
-							device pnp 2e.5 off end # Mouse
-							device pnp 2e.6 on  # Keyboard
-								 io 0x60 = 0x60
-								 io 0x62 = 0x64
-								irq 0x70 = 1
-							end
-							device pnp 2e.7 off end # GPIO
-							device pnp 2e.8 off end # ACB
-							device pnp 2e.9 off end # FSCM
-							device pnp 2e.a off end # WDT  
-						end
-					end
-					device pci 1.1 on end	# IDE
-					device pci 1.2 on end	# SMBus 2.0
-					device pci 1.3 on 	# System Management
-						chip drivers/generic/generic
-							#phillips pca9545 smbus mux
-							device i2c 70 on 
-								# analog_devices adm1026	
-								chip drivers/generic/generic
-									device i2c 2c on end
-								end
-							end
-							device i2c 70 on end
-							device i2c 70 on end
-							device i2c 70 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-0
-							device i2c 50 on end
-						end
-						chip drivers/generic/generic #dimm 0-0-1
-							device i2c 51 on end
-						end 
-						chip drivers/generic/generic #dimm 0-1-0
-							device i2c 52 on end
-						end 
-						chip drivers/generic/generic #dimm 0-1-1
-							device i2c 53 on end
-						end 
-						chip drivers/generic/generic #dimm 1-0-0
-							device i2c 54 on end 
-						end
-						chip drivers/generic/generic #dimm 1-0-1
-							device i2c 55 on end
-						end 
-						chip drivers/generic/generic #dimm 1-1-0
-							device i2c 56 on end
-						end 
-						chip drivers/generic/generic #dimm 1-1-1
-							device i2c 57 on end
-						end 
-					end
-					device pci 1.5 off end	# AC97 Audio
-					device pci 1.6 on  end	# AC97 Modem
-					register "ide0_enable" = "1"
-					register "ide1_enable" = "1"
-				end
-			end #  device pci 18.0 
-			
-			device pci 18.0 on end # LDT1
-			device pci 18.0 on end # LDT2
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end  # chip northbridge/amd/amdk8
-		chip northbridge/amd/amdk8
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.0 on end
-			device pci 19.1 on end
-			device pci 19.2 on end
-			device pci 19.3 on end
-		end
-	end 
-end
-
diff --git a/src/mainboard/arima/hdama/Options.lb b/src/mainboard/arima/hdama/Options.lb
deleted file mode 100644
index c047282..0000000
--- a/src/mainboard/arima/hdama/Options.lb
+++ /dev/null
@@ -1,242 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## CONFIG_LOGICAL_CPUS enables dual core support
-##
-default CONFIG_LOGICAL_CPUS=1
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
- 
-#VGA
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="HDAMA"
-default CONFIG_MAINBOARD_VENDOR="ARIMA"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/artecgroup/dbe61/Config.lb b/src/mainboard/artecgroup/dbe61/Config.lb
deleted file mode 100644
index e3cc41b..0000000
--- a/src/mainboard/artecgroup/dbe61/Config.lb
+++ /dev/null
@@ -1,124 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-	device pci_domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x2F8"
-			register "com1_irq" = "3"
-			register "com2_enable" = "1"
-			register "com2_address" = "0x3F8"
-			register "com2_irq" = "4"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci b.0 on end	# Slot 3
-			device pci c.0 on end	# Slot 4
-			device pci d.0 on end	# Slot 1
-			device pci e.0 on end	# Slot 2
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-
-end
-
diff --git a/src/mainboard/artecgroup/dbe61/Options.lb b/src/mainboard/artecgroup/dbe61/Options.lb
deleted file mode 100644
index 3aebf74..0000000
--- a/src/mainboard/artecgroup/dbe61/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_PCI_ROM_RUN=0
-default CONFIG_VIDEO_MB=8
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=3
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/artecgroup/dbe61/realmode/Config.lb b/src/mainboard/artecgroup/dbe61/realmode/Config.lb
deleted file mode 100644
index 899843d..0000000
--- a/src/mainboard/artecgroup/dbe61/realmode/Config.lb
+++ /dev/null
@@ -1,2 +0,0 @@
-config chip.h
-driver vgabios.o
diff --git a/src/mainboard/asi/mb_5blgp/Config.lb b/src/mainboard/asi/mb_5blgp/Config.lb
deleted file mode 100644
index 7bd25dc..0000000
--- a/src/mainboard/asi/mb_5blgp/Config.lb
+++ /dev/null
@@ -1,128 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 on end		# Ethernet
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.0 off		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.2 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.4 on		# System wake-up control (SWC)
-            irq 0x60 = 0x500
-          end
-          device pnp 2e.5 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.6 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.7 on		# GPIO
-            irq 0x60 = 0x800
-          end
-          device pnp 2e.8 on		# Fan speed control
-            irq 0x60 = 0x900
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# No connector on this board
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/asi/mb_5blgp/Options.lb b/src/mainboard/asi/mb_5blgp/Options.lb
deleted file mode 100644
index 7865fa3..0000000
--- a/src/mainboard/asi/mb_5blgp/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 3		# Override this in targets/*/Config.lb.
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-
-end
diff --git a/src/mainboard/asi/mb_5blmp/Config.lb b/src/mainboard/asi/mb_5blmp/Config.lb
deleted file mode 100644
index 93ac8e6..0000000
--- a/src/mainboard/asi/mb_5blmp/Config.lb
+++ /dev/null
@@ -1,146 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-##
-## Romcc output
-##
-# makerule ./failover.E
-# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-# 	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-# end
-# 
-# makerule ./failover.inc
-# 	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-# 	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-# end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-# if CONFIG_USE_FALLBACK_IMAGE
-# 	ldscript /arch/i386/lib/failover.lds 
-# 	mainboardinit ./failover.inc
-# end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 off end		# Ethernet (Realtek RTL8139B)
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc87351	# Super I/O
-          device pnp 2e.4 on		# PS/2 keyboard (+ mouse?)
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-            # irq 0x72 = 12
-          end
-          device pnp 2e.a on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.e on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.f off		# Floppy
-            io 0x60 = 0x3f2
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.10 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.12 on		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on  end		# IDE
-      device pci 12.3 on  end		# Audio
-      device pci 12.4 on  end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
-
diff --git a/src/mainboard/asi/mb_5blmp/Options.lb b/src/mainboard/asi/mb_5blmp/Options.lb
deleted file mode 100644
index 8924226..0000000
--- a/src/mainboard/asi/mb_5blmp/Options.lb
+++ /dev/null
@@ -1,163 +0,0 @@
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-# uses CONFIG_CONSOLE_VGA
-# uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE = 256 * 1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-default CONFIG_PIRQ_ROUTE=1
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to export a CMOS option table
-##
-# default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-# default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-# VGA Console
-# default CONFIG_CONSOLE_VGA=1
-# default CONFIG_PCI_ROM_RUN=1
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb
deleted file mode 100644
index 374629c5..0000000
--- a/src/mainboard/asus/a8n_e/Config.lb
+++ /dev/null
@@ -1,241 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-# Needed by irq_tables and mptable and acpi_tables.
-object get_bus_conf.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-	if CONFIG_USE_INIT
-		makerule ./auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/entry16.inc
-		ldscript /cpu/x86/16bit/entry16.lds
-	end
-end
-mainboardinit cpu/x86/32bit/entry32.inc
-	if CONFIG_USE_INIT
-		ldscript /cpu/x86/32bit/entry32.lds
-		ldscript /cpu/amd/car/cache_as_ram.lds
-	end
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit cpu/x86/16bit/reset16.inc
-		ldscript /cpu/x86/16bit/reset16.lds
-	else
-		mainboardinit cpu/x86/32bit/reset32.inc
-		ldscript /cpu/x86/32bit/reset32.lds
-	end
-end
-# Include an ID string (for safe flashing).
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-# ROMSTRAP table for CK804.
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-		mainboardinit southbridge/nvidia/ck804/romstrap.inc
-		ldscript /southbridge/nvidia/ck804/romstrap.lds
-	end
-end
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-if CONFIG_HAVE_FAILOVER_BOOT
-	if CONFIG_USE_FAILOVER_IMAGE
-			ldscript /arch/i386/lib/failover_failover.lds
-	end
-else
-	if CONFIG_USE_FALLBACK_IMAGE
-			ldscript /arch/i386/lib/failover.lds
-	end
-end
-	if CONFIG_USE_INIT
-		initobject auto.o
-	else
-		mainboardinit ./auto.inc
-	end
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# Socket 939 CPU
-      device apic 0 on end			# APIC
-    end
-  end
-
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/nvidia/ck804		# Southbridge
-          device pci 0.0 on end			# HT
-          device pci 1.0 on			# LPC
-            chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.2 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.3 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.4 on		# Environment controller
-                io 0x60 = 0x290
-                io 0x62 = 0x0000
-                irq 0x70 = 0x00
-              end
-              device pnp 2e.5 on		# PS/2 keyboard
-                io 0x60 = 0x60
-                io 0x62 = 0x64
-                irq 0x70 = 1
-                irq 0x71 = 2
-              end
-              device pnp 2e.6 on		# PS/2 mouse
-                irq 0x70 = 12
-                irq 0x71 = 2
-              end
-              device pnp 2e.7 on		# GPIO config
-                io 0x60 = 0x0800
-                # Set GPIO 1 & 2
-                io 0x25 = 0x0000
-                # Set GPIO 3 & 4
-                io 0x27 = 0x2540
-                # GPIO Polarity for Set 3
-                io 0xb2 = 0x2100
-                # GPIO Pin Internal Pull up for Set 3
-                io 0xba = 0x0100
-                # Simple I/O register config
-                io 0xc0 = 0x0000
-                io 0xc2 = 0x2540
-                io 0xc8 = 0x0000
-                io 0xca = 0x0500
-              end
-              device pnp 2e.8 on		# Midi port
-                io 0x60 = 0x300
-                irq 0x70 = 10
-              end
-              device pnp 2e.9 on		# Game port
-                io 0x60 = 0x201
-              end
-              device pnp 2e.a off		# IR (N/A on this board)
-                io 0x60 = 0x310
-                irq 0x70 = 11
-              end
-            end
-          end
-          device pci 1.1 on			# SM 0
-            # chip drivers/generic/generic #dimm 0-0-0
-            #   device i2c 50 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-0-1
-            #   device i2c 51 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-1-0
-            #   device i2c 52 on end
-            # end
-            # chip drivers/generic/generic #dimm 0-1-1
-            #   device i2c 53 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-0-0
-            #   device i2c 54 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-0-1
-            #   device i2c 55 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-1-0
-            #   device i2c 56 on end
-            # end
-            # chip drivers/generic/generic #dimm 1-1-1
-            #   device i2c 57 on end
-            # end
-          end
-          device pci 2.0 on end			# USB 1.1
-          device pci 2.1 on end			# USB 2
-          device pci 4.0 on end			# Onboard audio (ACI)
-          device pci 4.1 off end		# Onboard modem (MCI), N/A
-          device pci 6.0 on end			# IDE
-          device pci 7.0 on end			# SATA 1
-          device pci 8.0 on end			# SATA 0
-          device pci 9.0 on end			# PCI
-          device pci a.0 on end			# NIC
-          device pci b.0 on end			# PCI E 3
-          device pci c.0 on end			# PCI E 2
-          device pci d.0 on end			# PCI E 1
-          device pci e.0 on end			# PCI E 0
-          register "ide0_enable" = "1"
-          register "ide1_enable" = "1"
-          register "sata0_enable" = "1"
-          register "sata1_enable" = "1"
-          # register "mac_eeprom_smbus" = "3"
-          # register "mac_eeprom_addr" = "0x51"
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb
deleted file mode 100644
index a03db4b..0000000
--- a/src/mainboard/asus/a8n_e/Options.lb
+++ /dev/null
@@ -1,168 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
-## (Thanks to LSRA University of Mannheim for their support)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_CONSOLE_BTEXT
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_AP_CODE_IN_CAR
-uses CONFIG_MEM_TRAIN_SEQ
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_PCI_64BIT_PREF_MEM
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_ID_SECTION_OFFSET
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024 - CONFIG_FAILOVER_SIZE
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_FAILOVER_SIZE = 4 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_FAILOVER_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 13
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_OPTION_TABLE = 1
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-# SMP support (only worry about 2 micro processors).
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-# 1G memory hole.
-default CONFIG_HW_MEM_HOLE_SIZEK = 0x100000
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x10
-# Make the SB HT chain on bus 0, default is not (0).
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 2
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-# default CONFIG_CONSOLE_BTEXT = 1		# BTEXT console
-default CONFIG_CONSOLE_VGA = 1			# For VGA console
-default CONFIG_PCI_ROM_RUN = 1			# For VGA console
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xc8000
-default CONFIG_DCACHE_RAM_SIZE = 32 * 1024
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 4 * 1024
-default CONFIG_USE_INIT = 0
-default CONFIG_AP_CODE_IN_CAR = 0
-default CONFIG_MEM_TRAIN_SEQ = 2
-default CONFIG_WAIT_BEFORE_CPUS_INIT = 0
-# default CONFIG_ENABLE_APIC_EXT_ID = 0
-# default CONFIG_APIC_ID_OFFSET = 0x10
-# default CONFIG_LIFT_BSP_APIC_ID = 0
-# default CONFIG_PCI_64BIT_PREF_MEM = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_PART_NUMBER = "A8N-E"
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x815a
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-# Only use the option table in a normal image.
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE)
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR=1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-default CONFIG_ID_SECTION_OFFSET = 0x80
-
-end
diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb
deleted file mode 100644
index 308a1fe..0000000
--- a/src/mainboard/asus/a8v-e_se/Config.lb
+++ /dev/null
@@ -1,190 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_ROM_PAYLOAD = 1
-
-arch i386 end 
-
-driver mainboard.o
-if CONFIG_GENERATE_ACPI_TABLES
-  object acpi_tables.o
-  makerule dsdt.c
-    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "mv dsdt.hex dsdt.c"
-  end
-  object ./dsdt.o
-end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/entry16.inc
-  ldscript /cpu/x86/16bit/entry16.lds
-  mainboardinit southbridge/via/k8t890/romstrap.inc
-  ldscript /southbridge/via/k8t890/romstrap.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/reset16.inc
-  ldscript /cpu/x86/16bit/reset16.lds
-else
-  mainboardinit cpu/x86/32bit/reset32.inc
-  ldscript /cpu/x86/32bit/reset32.lds
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_USE_FALLBACK_IMAGE
-    ldscript /arch/i386/lib/failover.lds
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_939			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0"		# Enable SB functions
-          register "fn_ctrl_hi" = "0xad"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/winbond/w83627ehg	# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-                drq 0x74 = 3
-              end
-              device pnp 2e.2 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.3 off		# Com2 (N/A on this board)
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.5 off		# PS/2 keyboard (off)
-              end
-              device pnp 2e.106 off		# Serial flash
-                io 0x60 = 0x100
-              end
-              device pnp 2e.007 off		# GPIO 1
-              end
-              device pnp 2e.107 on		# Game port
-                io 0x60 = 0x201
-              end
-              device pnp 2e.207 on		# MIDI
-                io 0x62 = 0x330
-                irq 0x70 = 0xa
-              end
-              device pnp 2e.307 off		# GPIO 6
-              end
-              device pnp 2e.8 off		# WDTO_PLED
-              end
-              device pnp 2e.009 on		# GPIO 2 on LDN 9 is in sio_setup
-              end
-              device pnp 2e.109 off		# GPIO 3
-              end
-              device pnp 2e.209 off		# GPIO 4
-              end
-              device pnp 2e.309 on		# GPIO5
-              end
-              device pnp 2e.a off		# ACPI
-              end
-              device pnp 2e.b on		# Hardware monitor
-                io 0x60 = 0x290
-                irq 0x70 = 0
-              end
-            end
-          end
-          device pci 12.0 off end		# VIA LAN (off, other chip used)
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8T890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb
deleted file mode 100644
index 92c51fe..0000000
--- a/src/mainboard/asus/a8v-e_se/Options.lb
+++ /dev/null
@@ -1,165 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-# uses CONFIG_USE_OPTION_TABLE
-# uses CONFIG_RAMTOP
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-# bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0	# FIXME
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-default CONFIG_GENERATE_ACPI_TABLES = 1
-
-# 1G memory hole
-# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
-
-# Opteron K8 1G HT support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-
-# Make the SB HT chain on bus 0, default is not (0).
-# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
-
-# bx_b005+ make the SB HT chain on bus 0.
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
-
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 1		# Needed for VGA.
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xcc000
-default CONFIG_DCACHE_RAM_SIZE = 0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "A8V-E SE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 256 * 1024
-# More 1M for pgtbl.
-# default CONFIG_RAMTOP = 2048*1024
-default CONFIG_RAMBASE = 0x00004000
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR = 1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 8
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-end
diff --git a/src/mainboard/asus/m2v-mx_se/Config.lb b/src/mainboard/asus/m2v-mx_se/Config.lb
deleted file mode 100644
index 908d1b7..0000000
--- a/src/mainboard/asus/m2v-mx_se/Config.lb
+++ /dev/null
@@ -1,167 +0,0 @@
-## 
-## This file is part of the coreboot project.
-## 
-## Copyright (C) 2007 AMD
-## (Written by Yinghai Lu <yinghailu@amd.com> for AMD)
-## Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
-## 
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-## 
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-## 
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-## 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-driver mainboard.o
-if CONFIG_GENERATE_ACPI_TABLES
-  object acpi_tables.o
-  makerule dsdt.c
-    depends "$(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "iasl -p $(CURDIR)/dsdt -tc $(CONFIG_MAINBOARD)/dsdt.asl"
-    action  "mv dsdt.hex dsdt.c"
-  end
-  object ./dsdt.o
-end
-
-  if CONFIG_USE_INIT
-    makerule ./cache_as_ram_auto.o
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-    end
-  else
-    makerule ./cache_as_ram_auto.inc
-      depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-      action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-      action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-      action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-    end
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/entry16.inc
-  ldscript /cpu/x86/16bit/entry16.lds
-  mainboardinit southbridge/via/k8t890/romstrap.inc
-  ldscript /southbridge/via/k8t890/romstrap.lds
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-  if CONFIG_USE_INIT
-    ldscript /cpu/x86/32bit/entry32.lds
-  end
-  if CONFIG_USE_INIT
-    ldscript /cpu/amd/car/cache_as_ram.lds
-  end
-
-if CONFIG_USE_FALLBACK_IMAGE
-  mainboardinit cpu/x86/16bit/reset16.inc
-  ldscript /cpu/x86/16bit/reset16.lds
-else
-  mainboardinit cpu/x86/32bit/reset32.inc
-  ldscript /cpu/x86/32bit/reset32.lds
-end
-
-  mainboardinit cpu/amd/car/cache_as_ram.inc
-
-if CONFIG_USE_FALLBACK_IMAGE
-    ldscript /arch/i386/lib/failover.lds
-end
-
-  if CONFIG_USE_INIT
-    initobject cache_as_ram_auto.o
-  else
-    mainboardinit ./cache_as_ram_auto.inc
-  end
-
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex		# Root complex
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/amd/socket_AM2			# CPU
-      device apic 0 on end			# APIC
-    end
-  end
-  device pci_domain 0 on			# PCI domain
-    chip northbridge/amd/amdk8			# mc0
-      device pci 18.0 on			# Northbridge
-        # Devices on link 0, link 0 == LDT 0
-        chip southbridge/via/vt8237r		# Southbridge
-          register "ide0_enable" = "1"		# Enable IDE channel 0
-          register "ide1_enable" = "1"		# Enable IDE channel 1
-          register "ide0_80pin_cable" = "1"	# 80pin cable on IDE channel 0
-          register "ide1_80pin_cable" = "1"	# 80pin cable on IDE channel 1
-          register "fn_ctrl_lo" = "0xc0"	# Enable SB functions
-          register "fn_ctrl_hi" = "0x1d"	# Enable SB functions
-          device pci 0.0 on end			# HT
-          device pci f.1 on end			# IDE
-          device pci 11.0 on			# LPC
-            chip drivers/generic/generic	# DIMM 0-0-0
-              device i2c 50 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-0-1
-              device i2c 51 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-0
-              device i2c 52 on end
-            end
-            chip drivers/generic/generic	# DIMM 0-1-1
-              device i2c 53 on end
-            end
-            chip superio/ite/it8712f		# Super I/O
-              device pnp 2e.0 on		# Floppy
-                io 0x60 = 0x3f0
-                irq 0x70 = 6
-                drq 0x74 = 2
-              end
-              device pnp 2e.1 on		# Com1
-                io 0x60 = 0x3f8
-                irq 0x70 = 4
-              end
-              device pnp 2e.2 off		# Com2
-                io 0x60 = 0x2f8
-                irq 0x70 = 3
-              end
-              device pnp 2e.3 on		# Parallel port
-                io 0x60 = 0x378
-                irq 0x70 = 7
-              end
-              device pnp 2e.4 on		# Environment controller
-                io 0x60 = 0x290
-                io 0x62 = 0x230
-                irq 0x70 = 0x00
-              end
-              device pnp 2e.5 off end		# PS/2 keyboard
-              device pnp 2e.6 off end		# PS/2 mouse
-              device pnp 2e.7 off end		# GPIO config
-              device pnp 2e.8 off end		# Midi port
-              device pnp 2e.9 off end		# Game port
-              device pnp 2e.a off end		# IR
-	     end
-	   end
-          device pci 12.0 on end		# VIA LAN
-          device pci 13.0 on end		# br
-          device pci 13.1 on end		# br2 need to have it here to discover it
-        end
-        chip southbridge/via/k8t890		# "Southbridge" K8M890
-        end
-      end
-      device pci 18.1 on end
-      device pci 18.2 on end
-      device pci 18.3 on end
-    end
-  end
-end
diff --git a/src/mainboard/asus/m2v-mx_se/Options.lb b/src/mainboard/asus/m2v-mx_se/Options.lb
deleted file mode 100644
index eaa7168..0000000
--- a/src/mainboard/asus/m2v-mx_se/Options.lb
+++ /dev/null
@@ -1,174 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007, 2009 Rudolf Marek <r.marek@assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License v2 as published by
-## the Free Software Foundation.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_RAMTOP
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_MAINBOARD_RESOURCES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_HAVE_LOW_TABLES
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_VGA
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-# bx_b001- uses K8_HW_MEM_HOLE_SIZEK
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-# bx_b001- uses K8_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-# bx_b005+
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_USE_PRINTK_IN_CAR
-
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_HAVE_HARD_RESET = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 0
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_OPTION_TABLE = 1	# FIXME
-# Move the default coreboot CMOS range off of AMD RTC registers.
-default CONFIG_LB_CKS_RANGE_START = 49
-default CONFIG_LB_CKS_RANGE_END = 122
-default CONFIG_LB_CKS_LOC = 123
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_MAX_PHYSICAL_CPUS = 1
-default CONFIG_LOGICAL_CPUS = 1
-default CONFIG_GENERATE_ACPI_TABLES = 1
-default CONFIG_HAVE_MAINBOARD_RESOURCES = 1
-default CONFIG_HAVE_LOW_TABLES = 0
-default CONFIG_HAVE_ACPI_RESUME = 1
-
-# 1G memory hole
-# bx_b001- default K8_HW_MEM_HOLE_SIZEK = 0x100000
-
-# Opteron K8 1G HT support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT = 1
-
-# HT Unit ID offset, default is 1, the typical one.
-default CONFIG_HT_CHAIN_UNITID_BASE = 0x0
-
-# Real SB Unit ID, default is 0x20, mean don't touch it at last.
-# default CONFIG_HT_CHAIN_END_UNITID_BASE = 0x0
-
-# Make the SB HT chain on bus 0, default is not (0).
-# bx_b001- default K8_SB_HT_CHAIN_ON_BUS0 = 2
-
-# bx_b005+ make the SB HT chain on bus 0.
-default CONFIG_SB_HT_CHAIN_ON_BUS0 = 1
-
-# Only offset for SB chain?, default is yes(1).
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0
-
-default CONFIG_VGA = 1
-default CONFIG_CONSOLE_VGA = 1		# Needed for VGA.
-default CONFIG_PCI_ROM_RUN = 0		# Needed for VGA.
-default CONFIG_USE_DCACHE_RAM = 1
-default CONFIG_DCACHE_RAM_BASE = 0xcc000
-default CONFIG_DCACHE_RAM_SIZE = 0x4000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE = 0x01000
-default CONFIG_USE_INIT = 0
-default CONFIG_ENABLE_APIC_EXT_ID = 0
-default CONFIG_APIC_ID_OFFSET = 0x10
-default CONFIG_LIFT_BSP_APIC_ID = 0
-default CONFIG_IOAPIC = 1
-default CONFIG_MAINBOARD_VENDOR = "ASUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "M2V-MX SE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1043
-# default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID = 0x1234	# FIXME
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 256 * 1024
-# More 1M for pgtbl.
-default CONFIG_RAMTOP = 32768*1024
-# to 1MB
-default CONFIG_RAMBASE = 0x1F00000
-default CONFIG_USE_OPTION_TABLE = 0
-# default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_ROM_PAYLOAD = 1
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_GDB_STUB = 0
-default CONFIG_USE_PRINTK_IN_CAR=1
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL = "MAINBOARD_POWER_ON"
-
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-end
diff --git a/src/mainboard/asus/mew-am/Config.lb b/src/mainboard/asus/mew-am/Config.lb
deleted file mode 100644
index af6423c..0000000
--- a/src/mainboard/asus/mew-am/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	# Note: The -mcpu=p2 is important, or else... 'too few registers'.
-	action	"../romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-# TODO: On-board graphics.
-chip northbridge/intel/i82810		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/socket_PGA370	# CPU
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Graphics Memory Controller Hub (GMCH)
-    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
-    chip southbridge/intel/i82801xx	# Southbridge
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end		# PCI bridge
-      device pci 1f.0 on		# ISA bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 2e.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 2e.4 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.7 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 2e.9 on		# Game port
-            io 0x60 = 0x201
-          end
-          device pnp 2e.a on		# Power-management events (PME)
-            io 0x60 = 0x600
-          end
-          device pnp 2e.b on		# MIDI port (MPU-401)
-            io 0x60 = 0x330
-            irq 0x70 = 5
-          end
-        end
-      end
-      device pci 1f.1 on end		# IDE
-      device pci 1f.2 on end		# USB
-      device pci 1f.3 on end		# SMbus
-      device pci 1f.5 off end		# AC'97 audio (N/A, uses CS4280 chip)
-      device pci 1f.6 off end		# AC'97 modem (N/A)
-    end
-  end
-end
diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb
deleted file mode 100644
index c62bf48..0000000
--- a/src/mainboard/asus/mew-am/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 512 * 1024		# Override this in targets/*/Config.lb.
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9	# Override this in targets/*/Config.lb.
-default CONFIG_CONSOLE_VGA = 1		# Override this in targets/*/Config.lb.
-default CONFIG_PCI_ROM_RUN = 1		# Override this in targets/*/Config.lb.
-
-end
diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb
deleted file mode 100644
index 3cd4db2..0000000
--- a/src/mainboard/asus/mew-vm/Config.lb
+++ /dev/null
@@ -1,147 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i82810
-	device pci_domain 0 on 
-		device pci 0.0 on end # Host bridge
-		device pci 1.0 on # Onboard Video
-			#	device pci 1.0 on end
-		end
-		chip southbridge/intel/i82801xx # Southbridge
-      			register "ide0_enable" = "1"
-      			register "ide1_enable" = "1"
-
-			device pci 1e.0 on # PCI Bridge
-				#	device pci 1.0 on end
-			end
-			device pci 1f.0 on  # ISA/LPC? Bridge
-				chip superio/smsc/lpc47b272
-					device pnp 2e.0 off # Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.3 off # Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.4 on # Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.5 off # Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.7 on # Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1 # Keyboard interrupt
-						irq 0x72 = 12 # Mouse interrupt
-					end
-					device pnp 2e.a off end # ACPI
-				end
-			end
-			device pci 1f.1 on end # IDE
-			device pci 1f.2 on end # USB
-			device pci 1f.3 on end # SMBus
-			device pci 1f.5 off end # AC'97, no header on MEW-VM
-			device pci 1f.6 off end # AC'97 Modem (MC'97)
-		end
-	end
-	chip cpu/intel/socket_PGA370
-	end
-end
-
diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb
deleted file mode 100644
index 50f0b54..0000000
--- a/src/mainboard/asus/mew-vm/Options.lb
+++ /dev/null
@@ -1,154 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 512*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE = 0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET = 0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 11
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE = 0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-
-default CONFIG_UDELAY_TSC=1
-
-end
diff --git a/src/mainboard/asus/p2b-d/Config.lb b/src/mainboard/asus/p2b-d/Config.lb
deleted file mode 100644
index 1170d4c..0000000
--- a/src/mainboard/asus/p2b-d/Config.lb
+++ /dev/null
@@ -1,134 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 1 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-d/Options.lb b/src/mainboard/asus/p2b-d/Options.lb
deleted file mode 100644
index 2ccd3a9..0000000
--- a/src/mainboard/asus/p2b-d/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_IOAPIC = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-end
diff --git a/src/mainboard/asus/p2b-ds/Config.lb b/src/mainboard/asus/p2b-ds/Config.lb
deleted file mode 100644
index 4307c39..0000000
--- a/src/mainboard/asus/p2b-ds/Config.lb
+++ /dev/null
@@ -1,135 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 1 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      device pci 6.0 on end		# Onboard SCSI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "1"
-      register "ide0_drive1_udma33_enable" = "1"
-      register "ide1_drive0_udma33_enable" = "1"
-      register "ide1_drive1_udma33_enable" = "1"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-ds/Options.lb b/src/mainboard/asus/p2b-ds/Options.lb
deleted file mode 100644
index 45214cf..0000000
--- a/src/mainboard/asus/p2b-ds/Options.lb
+++ /dev/null
@@ -1,104 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_SMP
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_SMP = 1
-default CONFIG_MAX_CPUS = 2
-default CONFIG_IOAPIC = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p2b-f/Config.lb b/src/mainboard/asus/p2b-f/Config.lb
deleted file mode 100644
index 4be4b44..0000000
--- a/src/mainboard/asus/p2b-f/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/asus/p2b-f/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p2b/Config.lb b/src/mainboard/asus/p2b/Config.lb
deleted file mode 100644
index 559694d..0000000
--- a/src/mainboard/asus/p2b/Config.lb
+++ /dev/null
@@ -1,132 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.9 on		# GPIO 3
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb
deleted file mode 100644
index 0d1bb91..0000000
--- a/src/mainboard/asus/p2b/Options.lb
+++ /dev/null
@@ -1,98 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/asus/p3b-f/Config.lb b/src/mainboard/asus/p3b-f/Config.lb
deleted file mode 100644
index 628c413..0000000
--- a/src/mainboard/asus/p3b-f/Config.lb
+++ /dev/null
@@ -1,133 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-# TODO
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 4.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 4.1 on	end		# IDE
-      device pci 4.2 on	end		# USB
-      device pci 4.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb
deleted file mode 100644
index 1320c26..0000000
--- a/src/mainboard/asus/p3b-f/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 8		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/axus/tc320/Config.lb b/src/mainboard/axus/tc320/Config.lb
deleted file mode 100644
index e802587..0000000
--- a/src/mainboard/axus/tc320/Config.lb
+++ /dev/null
@@ -1,126 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 off		# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe800
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 off end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      # register "ide0_enable" = "1"
-      # register "ide1_enable" = "1"
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/axus/tc320/Options.lb b/src/mainboard/axus/tc320/Options.lb
deleted file mode 100644
index b0fd16e..0000000
--- a/src/mainboard/axus/tc320/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_MAINBOARD_VENDOR = "AXUS"
-default CONFIG_MAINBOARD_PART_NUMBER = "TC320"
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-end
diff --git a/src/mainboard/azza/pt-6ibd/Config.lb b/src/mainboard/azza/pt-6ibd/Config.lb
deleted file mode 100644
index b4f2224..0000000
--- a/src/mainboard/azza/pt-6ibd/Config.lb
+++ /dev/null
@@ -1,131 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/winbond/w83977tf	# Super I/O (FIXME: It's W83977EF!)
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.2 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.3 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.6 on		# Consumer IR
-          end
-          device pnp 3f0.7 on		# GPIO 1
-          end
-          device pnp 3f0.8 on		# GPIO 2
-          end
-          device pnp 3f0.a on		# ACPI
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/azza/pt-6ibd/Options.lb b/src/mainboard/azza/pt-6ibd/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/azza/pt-6ibd/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/bcom/winnet100/Config.lb b/src/mainboard/bcom/winnet100/Config.lb
deleted file mode 100644
index ccd4fb1..0000000
--- a/src/mainboard/bcom/winnet100/Config.lb
+++ /dev/null
@@ -1,129 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1		# Northbridge
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    chip southbridge/amd/cs5530		# Southbridge
-      device pci 0f.0 on end		# Ethernet (onboard)
-      device pci 12.0 on		# ISA bridge
-        chip superio/nsc/pc97317	# Super I/O
-          device pnp 2e.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 2e.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 2e.2 on		# RTC, Advanced power control (APC)
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 2e.3 off		# Floppy (N/A on this board)
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 2e.5 on		# COM2 (used for smartcard reader)
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.7 on		# GPIO
-            io 0x60 = 0xe0
-          end
-          device pnp 2e.8 on		# Power management
-            io 0x60 = 0xe8
-          end
-        end
-      end
-      device pci 12.1 off end		# SMI
-      device pci 12.2 on end		# IDE
-      device pci 12.3 on end		# Audio
-      device pci 12.4 on end		# VGA (onboard)
-      device pci 13.0 on end		# USB
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "0"	# Not available/needed on this board
-    end
-  end
-  chip cpu/amd/model_gx1		# CPU
-  end
-end
diff --git a/src/mainboard/bcom/winnet100/Options.lb b/src/mainboard/bcom/winnet100/Options.lb
deleted file mode 100644
index d241356..0000000
--- a/src/mainboard/bcom/winnet100/Options.lb
+++ /dev/null
@@ -1,103 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_SPLASH_GRAPHIC
-uses CONFIG_GX1_VIDEO
-uses CONFIG_GX1_VIDEOMODE
-uses CONFIG_PIRQ_ROUTE
-
-## Enable VGA with a splash screen (only 640x480 to run on most monitors).
-## We want to support up to 1024x768@16 so we need 2MiB video memory.
-## Note: Higher resolutions might need faster SDRAM speed.
-default CONFIG_GX1_VIDEO = 1
-default CONFIG_GX1_VIDEOMODE = 0
-default CONFIG_SPLASH_GRAPHIC = 1
-default CONFIG_VIDEO_MB = 2
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_MAINBOARD_VENDOR = "BCOM"
-default CONFIG_MAINBOARD_PART_NUMBER = "WinNET100"
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 2	# Soldered NIC, internal USB, no real slots
-default CONFIG_PIRQ_ROUTE = 1
-default CONFIG_HAVE_OPTION_TABLE = 0
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc "
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3		# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 6
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 6
-
-end
diff --git a/src/mainboard/bcom/winnetp680/Config.lb b/src/mainboard/bcom/winnetp680/Config.lb
deleted file mode 100644
index ed03650..0000000
--- a/src/mainboard/bcom/winnetp680/Config.lb
+++ /dev/null
@@ -1,138 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_ACPI_TABLES
-	object fadt.o
-	object dsdt.o
-	object acpi_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-dir /pc80
-config chip.h
-
-chip northbridge/via/cn700			# Northbridge
-  device pci_domain 0 on			# PCI domain
-    device pci 0.0 on end			# AGP Bridge
-    device pci 0.1 on end			# Error Reporting
-    device pci 0.2 on end			# Host Bus Control
-    device pci 0.3 on end			# Memory Controller
-    device pci 0.4 on end			# Power Management
-    device pci 0.7 on end			# V-Link Controller
-    device pci 1.0 on end			# PCI Bridge
-    chip southbridge/via/vt8237r		# Southbridge
-      # Enable both IDE channels.
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      # Both cables are 40pin.
-      register "ide0_80pin_cable" = "0"
-      register "ide1_80pin_cable" = "0"
-      register "fn_ctrl_lo" = "0x80"
-      register "fn_ctrl_hi" = "0x1d"
-      device pci f.0 on end			# IDE
-      device pci 10.0 on end			# UHCI
-      device pci 10.1 on end			# UHCI
-      device pci 10.2 on end			# UHCI
-      device pci 10.3 on end			# UHCI
-      device pci 10.4 on end			# EHCI
-      device pci 11.0 on			# Southbridge LPC
-        chip superio/winbond/w83697hf		# Super I/O
-          device pnp 2e.0 off			# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 2e.1 on			# Parallel Port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 3
-          end
-          device pnp 2e.2 on			# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 2e.3 on			# COM2
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 2e.6 off end		# Consumer IR
-          device pnp 2e.7 off end		# Game port, GPIO 1
-          device pnp 2e.8 off end		# MIDI port, GPIO 5
-          device pnp 2e.9 off end		# GPIO 2-4
-          device pnp 2e.a off end		# ACPI
-          device pnp 2e.b on			# HWM
-            io 0x60 = 0x290
-          end
-        end
-      end
-      device pci 11.5 on end			# AC'97 audio
-      device pci 12.0 on end			# Ethernet
-    end
-  end
-  device apic_cluster 0 on			# APIC cluster
-    chip cpu/via/model_c7			# VIA C7
-      device apic 0 on end			# APIC
-    end
-  end
-end
diff --git a/src/mainboard/bcom/winnetp680/Options.lb b/src/mainboard/bcom/winnetp680/Options.lb
deleted file mode 100644
index 99bd7f49..0000000
--- a/src/mainboard/bcom/winnetp680/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008 VIA Technologies, Inc.
-## (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_VIDEO_MB
-uses CONFIG_SMP
-uses CONFIG_IOAPIC
-
-default CONFIG_ROM_SIZE = 512 * 1024
-default CONFIG_SMP = 1
-default CONFIG_IOAPIC = 1
-default CONFIG_VIDEO_MB = 32
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_PCI_ROM_RUN = 0
-default CONFIG_CONSOLE_VGA = 0
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 10
-default CONFIG_GENERATE_ACPI_TABLES = 0
-default CONFIG_HAVE_OPTION_TABLE = 1
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_USE_FALLBACK_IMAGE = 1
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32 -fno-stack-protector"
-default HOSTCC = "gcc"
-
-end
diff --git a/src/mainboard/biostar/m6tba/Config.lb b/src/mainboard/biostar/m6tba/Config.lb
deleted file mode 100644
index 20edbc9..0000000
--- a/src/mainboard/biostar/m6tba/Config.lb
+++ /dev/null
@@ -1,126 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/smsc/smscsuperio	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.4 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.7 on		# PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1		# PS/2 keyboard interrupt
-            irq 0x72 = 12		# PS/2 mouse interrupt
-          end
-          device pnp 3f0.8 on		# Aux I/O
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/biostar/m6tba/Options.lb b/src/mainboard/biostar/m6tba/Options.lb
deleted file mode 100644
index 6884393..0000000
--- a/src/mainboard/biostar/m6tba/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 7		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/broadcom/blast/Config.lb b/src/mainboard/broadcom/blast/Config.lb
deleted file mode 100644
index 238596d..0000000
--- a/src/mainboard/broadcom/blast/Config.lb
+++ /dev/null
@@ -1,235 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-arch i386 end 
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE 
-	object get_bus_conf.o
-	object irq_tables.o 
-end
-
-	if CONFIG_USE_INIT
-
-		makerule ./cache_as_ram_auto.o
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-
-	else    
-                
-		makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript      /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	       ldscript /arch/i386/lib/failover.lds
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files 
-##
-config chip.h
-
-# sample config for broadcom/blast 
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_940
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8
-			device pci 18.0 on #  northbridge 
-                              #  devices on link 0
-                                chip southbridge/broadcom/bcm5780 # HT2000
-                                        device pci 0.0 on end   # PXB 1 0x0130
-                                        device pci 1.0 on       # PXB 2 0x0130
-                                                device pci 4.0 on end # GB E 0x1668 vid = 0x14e4
-                                                device pci 4.1 on end # GB E 0x1669 vid = 0x14e4
-                                        end
-                                        device pci 2.0 on end # PCI E 1  #0x0132
-                                        device pci 3.0 on end # PCI E 2
-                                        device pci 4.0 on end # PCI E 3
-                                        device pci 5.0 on end # PCI E 4
-                                end
-                                chip southbridge/broadcom/bcm5785 # HT1000
-                                        device pci 0.0 on  # HT PXB  0x0036
-                                                device pci d.0 on end # PPBX 0x0104
-                                                device pci e.0 on end # SATA 0x024a
-                                        end
-                                        device pci 1.0 on # Legacy  pci main  0x0205
-                                                chip drivers/i2c/i2cmux2 # pca9554 smbus mux
-                                                        device i2c 71 on end #0 pca9554 0
-							device i2c 71 on end #0 pca9554 1
-							device i2c 71 on end #0 pca9554 2
-							device i2c 71 on end #0 pca9554 3
-							device i2c 71 on end #0 pca9554 4
-							device i2c 71 on end #0 pca9554 5
-                                                        device i2c 71 on #0 pca9554 6
-                                                                chip drivers/generic/generic #dimm 0-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 0-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                        device i2c 71 on #1 pca9554 7
-                                                                chip drivers/generic/generic #dimm 1-0-0
-                                                                        device i2c 50 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-0-1
-                                                                        device i2c 51 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-0
-                                                                        device i2c 52 on end
-                                                                end
-                                                                chip drivers/generic/generic #dimm 1-1-1
-                                                                        device i2c 53 on end
-                                                                end
-                                                        end
-                                                end
-
-					end
-                                        device pci 1.1 on end # IDE        0x0214
-                                        device pci 1.2 on     # LPC        0x0234
-                                                chip superio/nsc/pc87417
-                                                        device  pnp 2e.0 off  # Floppy
-                                                                 io 0x60 = 0x3f0
-                                                                irq 0x70 = 6
-                                                                drq 0x74 = 2
-                                                        end
-                                                        device pnp 2e.1 off  # Parallel Port
-                                                                 io 0x60 = 0x378
-                                                                irq 0x70 = 7
-                                                        end
-                                                        device pnp 2e.2 off # Com 2
-                                                                 io 0x60 = 0x2f8
-                                                                irq 0x70 = 3
-                                                        end
-                                                        device pnp 2e.3 on  # Com 1
-                                                                 io 0x60 = 0x3f8
-                                                                irq 0x70 = 4
-                                                        end
-                                                        device pnp 2e.4 off end # SWC
-                                                        device pnp 2e.5 off end # Mouse
-                                                        device pnp 2e.6 on  # Keyboard
-                                                                 io 0x60 = 0x60
-                                                                 io 0x62 = 0x64
-                                                                irq 0x70 = 1
-                                                        end
-                                                        device pnp 2e.7 off end # GPIO
-                                                        device pnp 2e.f off end # XBUS
-                                                        device pnp 2e.10 on #RTC
-								 io 0x60 = 0x70
-								 io 0x62 = 0x72
-							end 
-                                                end
-                                        end
-                                        device pci 1.3 on end # WDTimer    0x0238
-                                        device pci 1.4 on end # XIOAPIC0   0x0235
-                                        device pci 1.5 on end # XIOAPIC1
-                                        device pci 1.6 on end # XIOAPIC2
-                                        device pci 2.0 on end # USB        0x0223
-                                        device pci 2.1 on end # USB
-                                        device pci 2.2 on end # USB
-                                        device pci 4.0 on end # it is in bcm5785_0 bus
-                                end
-			end #  device pci 18.0
-
-                        device pci 18.0 on end
-                        device pci 18.0 on end  
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end
-
-
-	end #pci_domain
-#        chip drivers/generic/debug
-#                device pnp 0.0 off end # chip name
-#                device pnp 0.1 on end # pci_regs_all
-#                device pnp 0.2 off end # mem
-#                device pnp 0.3 off end # cpuid
-#                device pnp 0.4 off end # smbus_regs_all
-#                device pnp 0.5 off end # dual core msr
-#                device pnp 0.6 off end # cache size
-#                device pnp 0.7 off end # tsc
-#       end
-
-end
-
diff --git a/src/mainboard/broadcom/blast/Options.lb b/src/mainboard/broadcom/blast/Options.lb
deleted file mode 100644
index 208a6c7..0000000
--- a/src/mainboard/broadcom/blast/Options.lb
+++ /dev/null
@@ -1,260 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-#1G memory hole
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-
-#VGA Console
-#default CONFIG_CONSOLE_VGA=1
-#default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset
-default CONFIG_HT_CHAIN_UNITID_BASE=0x6
-
-#real SB Unit ID
-default CONFIG_HT_CHAIN_END_UNITID_BASE=0x1
-
-#make the SB HT chain on bus 0
-default CONFIG_SB_HT_CHAIN_ON_BUS0=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xcf000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="blast"
-default CONFIG_MAINBOARD_VENDOR="Broadcom"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3050
-
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-## 
-default CONFIG_GDB_STUB=0
-
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
deleted file mode 100644
index 49f1585..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Config.lb
+++ /dev/null
@@ -1,136 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    device pci a.0 on end		# NIC (onboard)
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 14.0 on		# ISA bridge
-        # chip superio/nsc/pc97307	# Super I/O
-        chip superio/nsc/pc97317	# Super I/O (FIXME: Should be PC97307!)
-          device pnp 15c.0 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 15c.1 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 15c.2 on		# RTC, APC
-            io 0x60 = 0x70
-            irq 0x70 = 8
-          end
-          device pnp 15c.3 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 15c.4 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 15c.5 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 15c.6 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 15c.7 on		# GPIO 1
-          end
-          device pnp 15c.8 on		# Power management
-          end
-        end
-      end
-      device pci 14.1 on end		# IDE
-      device pci 14.2 on end		# USB
-      device pci 14.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb b/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
deleted file mode 100644
index dd8ab02..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 5		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/dell/s1850/Config.lb b/src/mainboard/dell/s1850/Config.lb
deleted file mode 100644
index cc0edc6..0000000
--- a/src/mainboard/dell/s1850/Config.lb
+++ /dev/null
@@ -1,174 +0,0 @@
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-if CONFIG_HAVE_HARD_RESET object reset.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-	action "../romcc -fno-simplify-phi -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-	action "../romcc -fno-simplify-phi -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -fno-simplify-phi -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc -fno-simplify-phi -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/intel/e7520 # mch
-	device pci_domain 0 on 
-		chip southbridge/intel/i82801er # i82801er
-			# USB ports
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end 
-			device pci 1d.3 on end
-			device pci 1d.7 on end
-		
-			# -> Bridge
-			device pci 1e.0 on end
-		
-			# -> ISA
-			device pci 1f.0 on 
-				chip superio/nsc/pc8374
-					device pnp 2e.0 off end
-					device pnp 2e.1 off end
-					device pnp 2e.2 off end
-					device pnp 2e.3 on 
-						 io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.4 off end
-					device pnp 2e.5 off end
-					device pnp 2e.6 off end
-					device pnp 2e.7 off end
-					device pnp 2e.8 off end
-				end
-			end
-			# -> IDE
-			device pci 1f.1 on end
-			# -> SATA 
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-
-			register "pirq_a_d" = "0x8e8b8f80"
-			register "pirq_e_h" = "0x80808080"
-		end
-		device pci 00.0 on end 
-		device pci 00.1 on end
-		device pci 01.0 on end 
-		device pci 02.0 on 
-			chip southbridge/intel/pxhd # pxhd1
-				# Bus bridges and ioapics usually bus 1
-				device pci 0.0 on 
-				# On board gig e1000
-					chip drivers/generic/generic 
-        		        	        device pci 03.0 on end
-        		        	        device pci 03.1 on end
-        		        	end
-				end
-				device pci 0.1 on end
-				device pci 0.2 on end
-				device pci 0.3 on end
-			end
-		end
-		device pci 04.0 on end
-		device pci 06.0 on end
-	end
-	device apic_cluster 0 on
-		chip cpu/intel/socket_mPGA604 # cpu 0
-			device apic 0 on end
-		end
-		chip cpu/intel/socket_mPGA604 # cpu 1
-			device apic 6 on end
-		end
-	end
-	register "intrline" = "0x00070100"
-end
-
diff --git a/src/mainboard/dell/s1850/Options.lb b/src/mainboard/dell/s1850/Options.lb
deleted file mode 100644
index fb65f8d..0000000
--- a/src/mainboard/dell/s1850/Options.lb
+++ /dev/null
@@ -1,228 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_RAMBASE
-uses CONFIG_GDB_STUB
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_BTEXT
-uses CC
-uses HOSTCC
-uses CONFIG_CROSS_COMPILE
-uses CONFIG_OBJCOPY
-
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=1048576
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## Delay timer options
-## Use timer2
-## 
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_LOGICAL_CPUS=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="X6DHR"
-default CONFIG_MAINBOARD_VENDOR=     "Supermicro"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x15D9
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x5580
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 64 * 1024
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD=1
-
-
-###
-### Defaults of options that you may want to override in the target config file
-### 
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-#default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-##
-## Don't enable the btext console
-##
-default  CONFIG_CONSOLE_BTEXT=0
-
-
-### End Options.lb
-end
diff --git a/src/mainboard/digitallogic/adl855pc/Config.lb b/src/mainboard/digitallogic/adl855pc/Config.lb
deleted file mode 100644
index c203231..0000000
--- a/src/mainboard/digitallogic/adl855pc/Config.lb
+++ /dev/null
@@ -1,159 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=p3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/x86/sse_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse_disable.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-## This does not look right but it is a literal conversion of the
-## old version of this file.
-chip northbridge/intel/i855pm
-	device pci_domain 0 on 
-		device pci 0.0 on end
-		device pci 1.0 on end
-		chip southbridge/intel/i82801dbm
-#			pci 11.0 on end
-#			pci 11.1 on end
-#			pci 11.2 on end
-#			pci 11.3 on end
-#			pci 11.4 on end
-#			pci 11.5 on end
-#			pci 11.6 on end
-#			pci 12.0 on end
-			register "enable_usb" = "0"
-			register "enable_native_ide" = "0"
-			register "enable_usb" = "0"
-			register "enable_native_ide" = "0"
-			chip superio/winbond/w83627hf # link 1
-                	        device pnp 2e.0 on      #  Floppy
-                	                 io 0x60 = 0x3f0
-                	                irq 0x70 = 6
-                	                drq 0x74 = 2
-				end
-                	        device pnp 2e.1 off     #  Parallel Port
-                	                 io 0x60 = 0x378
-                	                irq 0x70 = 7
-				end
-                	        device pnp 2e.2 on      #  Com1
-                	                 io 0x60 = 0x3f8
-                	                irq 0x70 = 4
-				end
-                	        device pnp 2e.3 off     #  Com2
-                	                io 0x60 = 0x2f8
-                	                irq 0x70 = 3
-				end
-                	        device pnp 2e.5 on      #  Keyboard
-                	                 io 0x60 = 0x60
-                	                 io 0x62 = 0x64
-                	                irq 0x70 = 1
-					irq 0x72 = 12
-				end
-                	        device pnp 2e.6 off end #  CIR
-                	        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
-                	        device pnp 2e.8 off end #  GPIO2
-                	        device pnp 2e.9 off end #  GPIO3
-                	        device pnp 2e.a off end #  ACPI
-                	        device pnp 2e.b on      #  HW Monitor
- 					 io 0x60 = 0x290
-				end
-				register "com1" = "{1}"
-			#	register "com1" = "{1, 0, 0x3f8, 4}"
-			#	register "lpt" = "{1}"
-                	end
-		end
-	end
-	device apic_cluster 0 on 
-		chip cpu/intel/socket_mPGA479M
-			device apic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/digitallogic/adl855pc/Options.lb b/src/mainboard/digitallogic/adl855pc/Options.lb
deleted file mode 100644
index 5c7ee6e..0000000
--- a/src/mainboard/digitallogic/adl855pc/Options.lb
+++ /dev/null
@@ -1,107 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_UDELAY_IO
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 1024*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## use io based udelay function
-##
-default CONFIG_UDELAY_IO=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-end
diff --git a/src/mainboard/digitallogic/msm586seg/Config.lb b/src/mainboard/digitallogic/msm586seg/Config.lb
deleted file mode 100644
index dbd3e64..0000000
--- a/src/mainboard/digitallogic/msm586seg/Config.lb
+++ /dev/null
@@ -1,111 +0,0 @@
-default CONFIG_ROM_SIZE = 512 * 1024 
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 32 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-
-# VGA console
-if CONFIG_CONSOLE_VGA
-	default CONFIG_PCI_ROM_RUN=1
-end
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-dir /devices
-config chip.h
-
-chip cpu/amd/sc520
-	device pci_domain 0 on 
-		device pci 0.0 on end
-		device pci 12.0 on end # enet
-		device pci 14.0 on end # 69000
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-
-end
diff --git a/src/mainboard/digitallogic/msm586seg/Options.lb b/src/mainboard/digitallogic/msm586seg/Options.lb
deleted file mode 100644
index 1bd5cae..0000000
--- a/src/mainboard/digitallogic/msm586seg/Options.lb
+++ /dev/null
@@ -1,121 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_USE_INIT
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-uses CONFIG_CONSOLE_SERIAL8250
-
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-# VGA support
-uses CONFIG_CONSOLE_VGA
-#uses CONFIG_LEGACY_VGABIOS
-#uses VGABIOS_START
-uses CONFIG_PCI_ROM_RUN
-
-
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-end
diff --git a/src/mainboard/digitallogic/msm800sev/Config.lb b/src/mainboard/digitallogic/msm800sev/Config.lb
deleted file mode 100644
index 5965cc1..0000000
--- a/src/mainboard/digitallogic/msm800sev/Config.lb
+++ /dev/null
@@ -1,170 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-
-	#compile cache_as_ram.c to auto.inc
-	makerule ./cache_as_ram_auto.inc
-			depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-			action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-			action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-			action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-	end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-#	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-
-	mainboardinit cpu/amd/model_lx/cache_as_ram.inc
-	mainboardinit ./cache_as_ram_auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/lx
-  	device pci_domain 0 on 
-    		device pci 1.0 on end
-		device pci 1.1 on end
-      		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			# How to get these? Boot linux and do this:
-			# rdmsr 0x51400025
-			register "lpc_serirq_enable" = "0x0000105a"
-			# rdmsr 0x5140004e -- polairy is high 16 bits of low 32 bits
-			register "lpc_serirq_polarity" = "0x0000EFA5"
-			# mode is high 10 bits (determined from code)
-			register "lpc_serirq_mode" = "1"
-			# Don't yet know how to find this.
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "0"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-        			device pci f.0 on	# ISA Bridge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 off #  Floppy
-						io 0x60 = 0x3f0
-						irq 0x70 = 6
-						drq 0x74 = 2
-					end
-					device pnp 2e.1 off #  Parallel Port
-						io 0x60 = 0x378
-						irq 0x70 = 7
-					end
-					device pnp 2e.2 on #  Com1
-						io 0x60 = 0x3f8
-						irq 0x70 = 4
-					end
-					device pnp 2e.3 on #  Com2
-						io 0x60 = 0x2f8
-						irq 0x70 = 3
-					end
-					device pnp 2e.5 on #  Keyboard
-						io 0x60 = 0x60
-						io 0x62 = 0x64
-						irq 0x70 = 1
-						irq 0x72 = 12
-					end
-					device pnp 2e.6 off #  CIR
-						io 0x60 = 0x100
-					end
-					device pnp 2e.7 off #  GAME_MIDI_GIPO1
-						io 0x60 = 0x220
-						io 0x62 = 0x300
-						irq 0x70 = 9
-					end						
-					device pnp 2e.8 off end #  GPIO2
-					device pnp 2e.9 off end #  GPIO3
-					device pnp 2e.a off end #  ACPI
-					device pnp 2e.b on #  HW Monitor
-						io 0x60 = 0x290
-						irq 0x70 = 5
-					end
-				end
-			end
-			device pci f.1 on end	# Flash controller
-			device pci f.2 on end	# IDE controller
-        			device pci f.3 on end 	# Audio
-        			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-      		end
-	end
-
-	# APIC cluster is late CPU init.
-	device apic_cluster 0 on
-		chip cpu/amd/model_lx
-			device apic 0 on end
-		end
-	end
-
-end
-
diff --git a/src/mainboard/digitallogic/msm800sev/Options.lb b/src/mainboard/digitallogic/msm800sev/Options.lb
deleted file mode 100644
index 88e2a1f..0000000
--- a/src/mainboard/digitallogic/msm800sev/Options.lb
+++ /dev/null
@@ -1,180 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_VIDEO_MB
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_PRINTK_IN_CAR
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_VIDEO_MB=8
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=9
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 32768
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-end
diff --git a/src/mainboard/eaglelion/5bcm/Config.lb b/src/mainboard/eaglelion/5bcm/Config.lb
deleted file mode 100644
index 64e833f..0000000
--- a/src/mainboard/eaglelion/5bcm/Config.lb
+++ /dev/null
@@ -1,150 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit cpu/amd/model_gx1/cpu_setup.inc
-mainboardinit cpu/amd/model_gx1/gx_setup.inc
-mainboardinit ./auto.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/gx1
-  device pci_domain 0 on 
-    device pci 0.0 on end
-      chip southbridge/amd/cs5530
-        device pci 12.0 on
-          chip superio/nsc/pc97317
-            device pnp 2e.0 on		# Keyboard
-               io 0x60 = 0x60
-               io 0x62 = 0x64
-              irq 0x70 = 1
-            end
-            device pnp 2e.1 on		# Mouse
-              irq 0x70 = 12
-            end
-            device pnp 2e.2 on		# RTC
-               io 0x60 = 0x70
-              irq 0x70 = 8
-            end
-            device pnp 2e.3 off		# FDC
-            end
-            device pnp 2e.4 on		# Parallel Port
-               io 0x60 = 0x378
-              irq 0x70 = 7
-            end
-            device pnp 2e.5 on		# COM2
-               io 0x60 = 0x2f8
-              irq 0x70 = 3
-            end
-            device pnp 2e.6 on		# COM1
-               io 0x60 = 0x3f8
-              irq 0x70 = 4
-            end
-            device pnp 2e.7 on		# GPIO
-               io 0x60 = 0xe0
-            end
-            device pnp 2e.8 on		# Power Management
-               io 0x60 = 0xe800
-            end
-            register "com1" = "{115200}"
-            register "com2" = "{38400}"
-          end
-        device pci 12.1 off end		# SMI
-        device pci 12.2 on  end		# IDE
-        device pci 12.3 off end 	# Audio
-        device pci 12.4 off end		# VGA
-      end
-    end
-  end
-
-  chip cpu/amd/model_gx1
-  end
-
-end
-
diff --git a/src/mainboard/eaglelion/5bcm/Options.lb b/src/mainboard/eaglelion/5bcm/Options.lb
deleted file mode 100644
index fb2bfae..0000000
--- a/src/mainboard/eaglelion/5bcm/Options.lb
+++ /dev/null
@@ -1,164 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_VIDEO_MB
-uses CONFIG_PIRQ_ROUTE
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=2
-default CONFIG_PIRQ_ROUTE=1
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=0
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-#default CONFIG_TTYS0_BAUD=57600
-#default CONFIG_TTYS0_BAUD=38400
-#default CONFIG_TTYS0_BAUD=19200
-#default CONFIG_TTYS0_BAUD=9600
-#default CONFIG_TTYS0_BAUD=4800
-#default CONFIG_TTYS0_BAUD=2400
-#default CONFIG_TTYS0_BAUD=1200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-##
-### Select the coreboot loglevel
-##
-## EMERG      1   system is unusable               
-## ALERT      2   action must be taken immediately 
-## CRIT       3   critical conditions              
-## ERR        4   error conditions                 
-## WARNING    5   warning conditions               
-## NOTICE     6   normal but significant condition 
-## INFO       7   informational                    
-## CONFIG_DEBUG      8   debug-level messages             
-## SPEW       9   Way too many details             
-
-## Request this level of debugging output
-default  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-default CONFIG_VIDEO_MB = 0
-
-end
diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb
deleted file mode 100644
index 7357648..0000000
--- a/src/mainboard/emulation/qemu-x86/Config.lb
+++ /dev/null
@@ -1,131 +0,0 @@
-## we don't use CONFIG_USE_DCACHE_RAM by default
-default CONFIG_USE_DCACHE_RAM=0
-##
-## Compute the location and size of where this firmware image
-## (coreboot plus bootloader) will live in the boot rom chip.
-##
-default CONFIG_ROM_SIZE = 256 * 1024 
-default CONFIG_ROM_SECTION_SIZE   = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_ROM_SECTION_OFFSET = CONFIG_ROM_SIZE - CONFIG_ROM_SECTION_SIZE
-
-##
-## Compute where this copy of coreboot will start in the boot rom
-##
-default CONFIG_ROMBASE      = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1)
-
-##
-## Compute a range of ROM that can cached to speed up coreboot,
-## execution speed.
-##
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE
-##
-default CONFIG_XIP_ROM_SIZE=32*1024
-default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-
-## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. 
-## That way, later, we can simply yank them if we wish. 
-## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. 
-## we do not use failover yet in this case. This is a work in progress. 
-if CONFIG_USE_DCACHE_RAM
-	##
-	##
-	mainboardinit arch/i386/init/entry.S
-	mainboardinit arch/i386/init/car.S
-	ldscript  /arch/i386/init/ldscript.ld
-
-	## The main code for the rom section is called rom.c
-	initobject rom.o
-else
-	##
-	## Romcc output
-	##
-	makerule ./failover.E
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" 
-		action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./failover.inc
-		depends "$(CONFIG_MAINBOARD)/failover.c ../romcc"
-		action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@"
-	end
-	
-	makerule ./auto.E 
-		depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-		action	"../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	makerule ./auto.inc 
-		depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-		action	"../romcc    -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-	end
-	
-	##
-	## Build our 16 bit and 32 bit coreboot entry code
-	##
-	mainboardinit cpu/x86/16bit/entry16.inc
-	mainboardinit cpu/x86/32bit/entry32.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-	ldscript /cpu/x86/32bit/entry32.lds
-
-	##
-	## Build our reset vector (This is where coreboot is entered)
-	##
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-	
-	### Should this be in the northbridge code?
-	mainboardinit arch/i386/lib/cpu_reset.inc
-
-	##
-	## Setup RAM
-	##
-	mainboardinit cpu/x86/fpu_enable.inc
-	mainboardinit ./auto.inc
-	
-	## the id string will be in cbfs. We will expect flashrom to parse cbfs for the idstring in future. 
-	##
-	## Include an id string (For safe flashing)
-	##
-	mainboardinit arch/i386/lib/id.inc
-	ldscript /arch/i386/lib/id.lds
-	
-##
-## end of CONFIG_USE_DCACHE_RAM bits. 
-##
-end
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip cpu/emulation/qemu-x86
-	device pci_domain 0 on 
-		device pci 0.0 on end
-
-		chip southbridge/intel/i82371eb # southbridge
-			device pci 01.0 on end
-			device pci 01.1 on end
-			register "ide0_enable" = "1"
-			register "ide1_enable" = "1"
-		end
-
-#		register "com1" = "{1}"
-#		register "com1" = "{1, 0, 0x3f8, 4}"
-	end
-end
diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb
deleted file mode 100644
index e067128..0000000
--- a/src/mainboard/emulation/qemu-x86/Options.lb
+++ /dev/null
@@ -1,140 +0,0 @@
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_COMPRESS
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_WRITE_HIGH_TABLES
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE
-
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_USE_INIT
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_UDELAY_IO
-default CONFIG_UDELAY_IO=1
-
-default CONFIG_CONSOLE_SERIAL8250=1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=6
-
-default CONFIG_WRITE_HIGH_TABLES=1
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Option ROM init
-##
-default CONFIG_PCI_ROM_RUN=1
-default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## known-good settings for qemu
-default CONFIG_DCACHE_RAM_BASE=0x8f000
-default CONFIG_DCACHE_RAM_SIZE=0x1000
-
-
-
-
-end
diff --git a/src/mainboard/gigabyte/ga-6bxc/Config.lb b/src/mainboard/gigabyte/ga-6bxc/Config.lb
deleted file mode 100644
index 663f58e..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/Config.lb
+++ /dev/null
@@ -1,130 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 128 * 1024
-include /config/nofailovercalculation.lb
-default CONFIG_XIP_ROM_BASE = 0xffffffff - CONFIG_XIP_ROM_SIZE + 1
-
-arch i386 end
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE
-	object irq_tables.o
-end
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -E -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc -O2 -mcpu=p2 --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-makerule ./auto.E
-	# depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends	"$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -E -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
-	# depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	depends "$(CONFIG_MAINBOARD)/auto.c ../romcc"
-	action	"../romcc -O2 -mcpu=p2 -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-end
-mainboardinit arch/i386/lib/cpu_reset.inc
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds
-	mainboardinit ./failover.inc
-end
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-dir /pc80
-config chip.h
-
-chip northbridge/intel/i440bx		# Northbridge
-  device apic_cluster 0 on		# APIC cluster
-    chip cpu/intel/slot_2		# CPU (FIXME: It's slot 1, actually)
-      device apic 0 on end		# APIC
-    end
-  end
-  device pci_domain 0 on		# PCI domain
-    device pci 0.0 on end		# Host bridge
-    device pci 1.0 on end		# PCI/AGP bridge
-    chip southbridge/intel/i82371eb	# Southbridge
-      device pci 7.0 on			# ISA bridge
-        chip superio/ite/it8671f	# Super I/O
-          device pnp 3f0.0 on		# Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 3f0.1 on		# COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 3f0.2 on		# COM2 / IR
-            io 0x60 = 0x2f8
-            irq 0x70 = 3
-          end
-          device pnp 3f0.3 on		# Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-          end
-          device pnp 3f0.4 on		# APC
-          end
-          device pnp 3f0.5 on		# PS/2 keyboard
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1
-          end
-          device pnp 3f0.6 on		# PS/2 mouse
-            irq 0x70 = 12
-          end
-          device pnp 3f0.7 on		# GPIO
-          end
-        end
-      end
-      device pci 7.1 on	end		# IDE
-      device pci 7.2 on	end		# USB
-      device pci 7.3 on end		# ACPI
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-      register "ide_legacy_enable" = "1"
-      # Enable UDMA/33 for higher speed if your IDE device(s) support it.
-      register "ide0_drive0_udma33_enable" = "0"
-      register "ide0_drive1_udma33_enable" = "0"
-      register "ide1_drive0_udma33_enable" = "0"
-      register "ide1_drive1_udma33_enable" = "0"
-    end
-  end
-end
diff --git a/src/mainboard/gigabyte/ga-6bxc/Options.lb b/src/mainboard/gigabyte/ga-6bxc/Options.lb
deleted file mode 100644
index 8189979..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/Options.lb
+++ /dev/null
@@ -1,97 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-
-default CONFIG_ROM_SIZE = 256 * 1024
-default CONFIG_HAVE_FALLBACK_BOOT = 1
-default CONFIG_GENERATE_MP_TABLE = 0
-default CONFIG_HAVE_HARD_RESET = 0
-default CONFIG_UDELAY_TSC = 1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 = 1
-default CONFIG_GENERATE_PIRQ_TABLE = 1
-default CONFIG_IRQ_SLOT_COUNT = 6		# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_VENDOR = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_MAINBOARD_PART_NUMBER = "N/A"	# Override this in targets/*/Config.lb.
-default CONFIG_ROM_IMAGE_SIZE = 36 * 1024
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-default CONFIG_STACK_SIZE = 8 * 1024
-default CONFIG_HEAP_SIZE = 16 * 1024
-default CONFIG_HAVE_OPTION_TABLE = 0
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-default CONFIG_RAMBASE = 0x00004000
-default CONFIG_ROM_PAYLOAD = 1
-default CONFIG_CROSS_COMPILE = ""
-default CC = "$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC = "gcc"
-default CONFIG_CONSOLE_SERIAL8250 = 1
-default CONFIG_TTYS0_BAUD = 115200
-default CONFIG_TTYS0_BASE = 0x3f8
-default CONFIG_TTYS0_LCS = 0x3			# 8n1
-default CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-default CONFIG_CONSOLE_VGA = 1
-default CONFIG_PCI_ROM_RUN = 1
-
-end
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb b/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
deleted file mode 100644
index 6cca586..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Config.lb
+++ /dev/null
@@ -1,270 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/failovercalculation.lb
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if CONFIG_GENERATE_MP_TABLE object mptable.o end
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-	if CONFIG_USE_INIT
-		makerule ./cache_as_ram_auto.o
-		        depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-        		action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		end
-	else
-		makerule ./cache_as_ram_auto.inc
-        		depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
-		        action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_CPU_OPT) $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
-		        action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
-        		action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
-		end
-	end
-
-if CONFIG_USE_FAILOVER_IMAGE
-else
-    if CONFIG_AP_CODE_IN_CAR
-        makerule ./apc_auto.o
-                depends "$(CONFIG_MAINBOARD)/apc_auto.c option_table.h"
-                action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/apc_auto.c -o $@"
-        end
-        ldscript /arch/i386/init/ldscript_apc.lb
-    end
-end
-
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/entry16.inc
-	ldscript /cpu/x86/16bit/entry16.lds
-    end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/x86/32bit/entry32.lds
-        end
-
-        if CONFIG_USE_INIT
-                ldscript /cpu/amd/car/cache_as_ram.lds
-        end
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit cpu/x86/16bit/reset16.inc
-	ldscript /cpu/x86/16bit/reset16.lds
-    else
-	mainboardinit cpu/x86/32bit/reset32.inc
-	ldscript /cpu/x86/32bit/reset32.lds
-    end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-##
-## ROMSTRAP table for MCP55
-##
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-	mainboardinit southbridge/sis/sis966/romstrap.inc
-	ldscript /southbridge/sis/sis966/romstrap.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-	mainboardinit southbridge/sis/sis966/romstrap.inc
-	ldscript /southbridge/sis/sis966/romstrap.lds
-    end
-end
-
-	##
-	## Setup Cache-As-Ram
-	##
-	mainboardinit cpu/amd/car/cache_as_ram.inc
-
-###
-### This is the early phase of coreboot startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_HAVE_FAILOVER_BOOT
-    if CONFIG_USE_FAILOVER_IMAGE
-		ldscript /arch/i386/lib/failover_failover.lds
-    end
-else
-    if CONFIG_USE_FALLBACK_IMAGE
-		ldscript /arch/i386/lib/failover.lds
-    end
-end
-
-##
-## Setup RAM
-##
-	if CONFIG_USE_INIT
-		initobject cache_as_ram_auto.o
-	else
-		mainboardinit ./cache_as_ram_auto.inc
-	end
-
-##
-## Include the secondary Configuration files
-##
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
-        device apic_cluster 0 on
-                chip cpu/amd/socket_AM2
-                        device apic 0 on end
-                end
-        end
-	device pci_domain 0 on
-		chip northbridge/amd/amdk8 #mc0
-			device pci 18.0 on
-				#  devices on link 0, link 0 == LDT 0
-			        chip southbridge/sis/sis966
-					device pci 0.0 on end   # Northbridge
-					device pci 1.0 on		# AGP bridge
-						device pci 0.0 on end
-					end
-                			device pci 2.0 on # LPC
-						chip superio/ite/it8716f
-							device pnp 2e.0 off #  Floppy (N/A)
-                	                 			io 0x60 = 0x3f0
-                	                			irq 0x70 = 6
-                	                			drq 0x74 = 2
-							end
-                	        			device pnp 2e.1 on #  Com1
-                	                 			io 0x60 = 0x3f8
-                	                			irq 0x70 = 4
-							end
-                	        			device pnp 2e.2 off #  Com2 (N/A)
-                	                 			io 0x60 = 0x2f8
-                	                			irq 0x70 = 3
-							end
-                	        			device pnp 2e.3 off #  Parallel port (N/A)
-                	                 			io 0x60 = 0x378
-                	                			irq 0x70 = 7
-							end
-                	        			device pnp 2e.4 on #  EC
-                	                 			io 0x60 = 0x290
-                	                 			io 0x62 = 0x230
-                	                			irq 0x70 = 9
-							end
-							device pnp 2e.5 off #  PS/2 keyboard (N/A)
-                	                 			io 0x60 = 0x60
-                	                 			io 0x62 = 0x64
-                	                			irq 0x70 = 1
-							end
-							device pnp 2e.6 off #  Mouse (N/A)
-                	                			irq 0x70 = 12
-							end
-                	        			device pnp 2e.8 off #  MIDI (N/A)
-								io 0x60 = 0x300
-								irq 0x70 = 10
-							end
-                	        			device pnp 2e.9 off #  GAME (N/A)
-								io 0x60 = 0x220
-							end
-                	        			device pnp 2e.a off end #  CIR (N/A)
-						end
-					end
-
-                                        device pci 2.5 off end # IDE (SiS5513)
-                                        device pci 2.6 off end # Modem (SiS7013)
-                                        device pci 2.7 off end # Audio (SiS7012)
-                                        device pci 3.0 on end # USB (SiS7001,USB1.1)
-                                        device pci 3.1 on end # USB (SiS7001,USB1.1)
-                                        device pci 3.3 on end # USB (SiS7002,USB2.0)
-                                        device pci 4.0 on end # NIC (SiS191)
-                                        device pci 5.0 on end # SATA (SiS1183,Native Mode)
-                                        device pci 6.0 on end # PCI-e x1
-                                        device pci 7.0 on end # PCI-e x1
-                                        device pci a.0 off end
-                                        device pci b.0 off end
-                                        device pci c.0 off end
-                                        device pci d.0 off end
-                                        device pci e.0 off end
-                                        device pci f.0 off end # HD Audio (SiS7502)
-
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
-                                        register "sata0_enable" = "1"
-                                        register "sata1_enable" = "1"
-				end
-			end #  device pci 18.0
-			device pci 18.0 on end # Link 1
-			device pci 18.0 on end
-			device pci 18.1 on end
-			device pci 18.2 on end
-			device pci 18.3 on end
-		end # mc0
-
-	end # PCI domain
-
-#       chip drivers/generic/debug
-#               device pnp 0.0 off end # chip name
-#               device pnp 0.1 on end # pci_regs_all
-#               device pnp 0.2 off end # mem
-#               device pnp 0.3 off end # cpuid
-#               device pnp 0.4 off end # smbus_regs_all
-#               device pnp 0.5 off end # dual core msr
-#               device pnp 0.6 off end # cache size
-#               device pnp 0.7 off end # tsc
-#               device pnp 0.8 off end # io
-#               device pnp 0.9 off end # io
-#       end
-end #root_complex
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb b/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
deleted file mode 100644
index 6cbef12..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/Options.lb
+++ /dev/null
@@ -1,354 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007 AMD
-## Written by Yinghai Lu <yinghailu@amd.com> for AMD.
-## Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
-## Written by Morgan Tsai <my_tsai@sis.com> for SiS.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
-##
-
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_GENERATE_ACPI_TABLES
-uses CONFIG_HAVE_ACPI_RESUME
-uses CONFIG_ACPI_SSDTX_NUM
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_USE_FAILOVER_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_FAILOVER_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_FAILOVER_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_LB_CKS_RANGE_START
-uses CONFIG_LB_CKS_RANGE_END
-uses CONFIG_LB_CKS_LOC
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_RAMBASE
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_USBDEBUG_DIRECT
-uses CONFIG_PCI_ROM_RUN
-uses CONFIG_HW_MEM_HOLE_SIZEK
-uses CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC
-uses CONFIG_K8_HT_FREQ_1G_SUPPORT
-
-uses CONFIG_HT_CHAIN_UNITID_BASE
-uses CONFIG_HT_CHAIN_END_UNITID_BASE
-uses CONFIG_SB_HT_CHAIN_ON_BUS0
-uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses CONFIG_USE_DCACHE_RAM
-uses CONFIG_DCACHE_RAM_BASE
-uses CONFIG_DCACHE_RAM_SIZE
-uses CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses CONFIG_SERIAL_CPU_INIT
-
-uses CONFIG_ENABLE_APIC_EXT_ID
-uses CONFIG_APIC_ID_OFFSET
-uses CONFIG_LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_RAMTOP
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses CONFIG_MEM_TRAIN_SEQ
-
-uses CONFIG_WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-uses CONFIG_ID_SECTION_OFFSET
-
-###
-### Build options
-###
-
-##
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-##
-default CONFIG_ROM_SIZE=524288
-#default CONFIG_ROM_SIZE=0x100000
-
-##
-## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-
-#FALLBACK: 256K-4K
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-#FAILOVER: 4K
-default CONFIG_FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_RAMTOP=2048*1024
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-default CONFIG_HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-## ACPI tables will be included
-default CONFIG_GENERATE_ACPI_TABLES=0
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-##
-## Move the default coreboot cmos range off of AMD RTC registers
-##
-default CONFIG_LB_CKS_RANGE_START=49
-default CONFIG_LB_CKS_RANGE_END=122
-default CONFIG_LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=1
-default CONFIG_LOGICAL_CPUS=1
-
-#default CONFIG_SERIAL_CPU_INIT=0
-
-default CONFIG_ENABLE_APIC_EXT_ID=0
-default CONFIG_APIC_ID_OFFSET=0x10
-default CONFIG_LIFT_BSP_APIC_ID=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x200000
-#1G
-default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
-#512M
-#default CONFIG_HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default CONFIG_HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default CONFIG_K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#default CONFIG_USBDEBUG_DIRECT=0
-
-#HT Unit ID offset, default is 1, the typical one, 0 mean only one HT device
-default CONFIG_HT_CHAIN_UNITID_BASE=0
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-#default CONFIG_HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default CONFIG_SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default CONFIG_USE_DCACHE_RAM=1
-default CONFIG_DCACHE_RAM_BASE=0xc8000
-default CONFIG_DCACHE_RAM_SIZE=0x08000
-default CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-default CONFIG_AP_CODE_IN_CAR=0
-default CONFIG_MEM_TRAIN_SEQ=2
-default CONFIG_WAIT_BEFORE_CPUS_INIT=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default CONFIG_MAINBOARD_PART_NUMBER="ga_2761gxdk"
-default CONFIG_MAINBOARD_VENDOR="GIGABYTE"
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1039
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536 - CONFIG_FAILOVER_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default CONFIG_HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default CONFIG_USE_OPTION_TABLE = (!CONFIG_USE_FALLBACK_IMAGE) && (!CONFIG_USE_FAILOVER_IMAGE )
-
-##
-## Coreboot C code runs at this location in RAM
-##
-default CONFIG_RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_PAYLOAD = 1
-
-#default CONFIG_COMPRESSED_PAYLOAD_NRV2B = 1
-
-###
-### Default