| chip soc/intel/meteorlake |
| |
| # GPE configuration |
| register "pmc_gpe0_dw0" = "GPP_B" |
| register "pmc_gpe0_dw1" = "GPP_D" |
| register "pmc_gpe0_dw2" = "GPP_E" |
| |
| # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f |
| register "gen1_dec" = "0x00fc0801" |
| register "gen2_dec" = "0x000c0201" |
| # EC memory map range is 0x900-0x9ff |
| register "gen3_dec" = "0x00fc0901" |
| |
| register "serial_io_uart_mode" = "{ |
| [PchSerialIoIndexUART0] = PchSerialIoPci, |
| [PchSerialIoIndexUART1] = PchSerialIoDisabled, |
| [PchSerialIoIndexUART2] = PchSerialIoDisabled, |
| }" |
| |
| register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C0 |
| register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C1 |
| register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C2 |
| register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC0)" # USB2_C3 |
| register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 |
| register "usb2_ports[5]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector |
| register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN / MCF |
| register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # MCF / M.2 WWAN |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN |
| |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A1 / M.2 WWAN |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2_Type-A0 / USB Flex Connector |
| |
| register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" |
| register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" |
| |
| device domain 0 on |
| device ref igpu on end |
| device ref heci1 on end |
| device ref tbt_pcie_rp0 on end |
| device ref tbt_pcie_rp1 on end |
| device ref tbt_pcie_rp2 on end |
| device ref tbt_pcie_rp3 on end |
| device ref tcss_xhci on end |
| device ref tcss_dma0 on end |
| device ref tcss_dma1 on end |
| device ref pcie_rp10 on |
| # Enable SSD Gen4 PCIE 10 using CLK 8 |
| register "pcie_rp[PCIE_RP(10)]" = "{ |
| .clk_src = 8, |
| .clk_req = 8, |
| .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, |
| }" |
| end # PCIE10 SSD Gen4 |
| device ref pcie_rp11 on |
| # Enable SSD Gen4 PCIE 11 using CLK 7 |
| register "pcie_rp[PCIE_RP(11)]" = "{ |
| .clk_src = 7, |
| .clk_req = 7, |
| .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR, |
| }" |
| end # PCIE11 SSD Gen4 |
| device ref xhci on end |
| device ref i2c0 on end |
| device ref i2c1 on end |
| device ref i2c2 on end |
| device ref i2c3 on end |
| device ref i2c4 on end |
| device ref i2c5 on end |
| device ref shared_sram on end |
| device ref uart0 on end |
| device ref smbus on end |
| end |
| end |