blob: 9f37526806e1eb7df87471753906cfd09d3e03ac [file] [log] [blame]
## SPDX-License-Identifier: GPL-2.0-only
chip northbridge/intel/sandybridge
# IGD Displays
register "gfx.ndid" = "3"
register "gfx.did" = "{ 0x80000400, 0x80000300, 0x80000100, }"
# Enable Panel as eDP and configure power delays
register "gpu_panel_port_select" = "PANEL_PORT_DP_A"
register "gpu_panel_power_cycle_delay" = "6" # 500ms
register "gpu_panel_power_up_delay" = "2000" # 200ms
register "gpu_panel_power_down_delay" = "500" # 50ms
register "gpu_panel_power_backlight_on_delay" = "1" # 100us as recommended by PRM
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
# Set backlight PWM values for eDP
register "gpu_cpu_backlight" = "0x0000001a"
register "gpu_pch_backlight" = "0x002e0000"
register "usb3.mode" = "3"
register "usb3.hs_port_switch_mask" = "0xf"
register "usb3.preboot_support" = "1"
register "usb3.xhci_streams" = "1"
register "spd_addresses" = "{0x50, 0, 0x52, 0}"
register "ec_present" = "1"
register "max_mem_clock_mhz" = "800"
chip cpu/intel/model_206ax
device cpu_cluster 0 on end
register "acpi_c2" = "CPU_ACPI_C6"
register "acpi_c3" = "CPU_ACPI_DISABLED"
end
device domain 0 on
device ref host_bridge on end # host bridge
device ref igd on end # vga controller
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# Enable both SATA ports 0, 1
register "sata_port_map" = "0x03"
# Set max SATA speed to 6.0 Gb/s (should be the default, anyway)
register "sata_interface_speed_support" = "0x3"
# Route GPI7 (EC SCI) as SCI
register "gpi7_routing" = "2"
# Enable GPE17 (GPI7) and TCO SCI
register "gpe0_en" = "0x00800040"
# Disable root port coalescing
register "pcie_port_coalesce" = "false"
register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
register "xhci_overcurrent_mapping" = "0x00080401"
register "xhci_switchable_ports" = "0x0f"
register "superspeed_capable_ports" = "0x0f"
register "usb_port_config" = "{
{ 1, 0, 0 }, /* P00: 1st USB3 (OC #0) */
{ 1, 0, 4 }, /* P01: 2nd USB3 (OC #4) */
{ 1, 1, 1 }, /* P02: 1st Multibay USB3 (OC #1) */
{ 1, 1, 2 }, /* P03: 2nd Multibay USB3 (OC #2) */
{ 1, 0, 8 }, /* P04: MiniPCIe 1 USB2 (no OC) */
{ 1, 0, 8 }, /* P05: MiniPCIe 2 USB2 (no OC) */
{ 1, 0, 8 }, /* P06: MiniPCIe 3 USB2 (no OC) */
{ 1, 0, 8 }, /* P07: GPS USB2 (no OC) */
{ 1, 0, 8 }, /* P08: MiniPCIe 4 USB2 (no OC) */
{ 1, 0, 3 }, /* P09: Express Card USB2 (OC #3) */
{ 1, 0, 8 }, /* P10: SD card reader USB2 (no OC) */
{ 1, 0, 8 }, /* P11: Sensors Hub? USB2 (no OC) */
{ 1, 0, 8 }, /* P12: Touch Screen USB2 (no OC) */
{ 1, 0, 5 }, /* P13: reserved? USB2 (OC #5) */
}"
register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005"
device ref xhci on end # USB 3.0 Controller
device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
device ref me_kt off end # Management Engine KT
device ref gbe on end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on # High Definition Audio
subsystemid 0x1a86 0x4352
end
# Disabling 1c.0 might break IRQ settings as it enables port coalescing
device ref pcie_rp1 on end # PCIe Port #1
device ref pcie_rp2 on end # PCIe Port #2
device ref pcie_rp3 off end # PCIe Port #3
device ref pcie_rp4 on end # PCIe Port #4
device ref pcie_rp5 on end # PCIe Port #5
device ref pcie_rp6 off end # PCIe Port #6
device ref pcie_rp7 on end # PCIe Port #7
device ref pcie_rp8 on end # PCIe Port #8
device ref ehci1 on end # USB2 EHCI #1
device ref pci_bridge off end # PCI bridge
device ref lpc on # LPC bridge
chip ec/roda/it8518
# 60h/64h KBC
device pnp ff.0 on # dummy address
end
end
end # LPC bridge
device ref sata1 on end # SATA Controller 1
device ref smbus on end # SMBus
device ref sata2 off end # SATA Controller 2
device ref thermal off end # Thermal
end
end
end