| chip soc/intel/baytrail |
| |
| # SATA port enable mask (2 ports) |
| register "sata_port_map" = "0x1" |
| register "sata_ahci" = "0x1" |
| register "ide_legacy_combined" = "0x0" |
| |
| # Route USB ports to XHCI |
| register "usb_route_to_xhci" = "1" |
| |
| # USB Port Disable Mask |
| register "usb2_port_disable_mask" = "0x0" |
| register "usb3_port_disable_mask" = "0x0" |
| |
| # USB PHY settings |
| # TODO: These values are from Baytrail and need tuned for Rambi board |
| register "usb2_per_port_lane0" = "0x00049a09" |
| register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" |
| register "usb2_per_port_lane1" = "0x00049a09" |
| register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" |
| register "usb2_per_port_lane2" = "0x00049209" |
| register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" |
| register "usb2_per_port_lane3" = "0x00049a09" |
| register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" |
| |
| device cpu_cluster 0 on |
| device lapic 0 on end |
| end |
| device domain 0 on |
| device pci 00.0 on end # SoC router |
| device pci 02.0 on end # GFX |
| device pci 11.0 off end # SDIO |
| device pci 12.0 on end # SD |
| device pci 13.0 on end # SATA |
| device pci 14.0 on end # XHCI |
| device pci 15.0 on end # LPE |
| device pci 17.0 on end # MMC |
| device pci 18.0 on end # SIO_DMA1 |
| device pci 18.1 on end # I2C1 |
| device pci 18.2 on end # I2C2 |
| device pci 18.3 off end # I2C3 |
| device pci 18.4 off end # I2C4 |
| device pci 18.5 on end # I2C5 |
| device pci 18.6 on end # I2C6 |
| device pci 18.7 off end # I2C7 |
| device pci 1a.0 on end # TXE |
| device pci 1b.0 on end # HDA |
| device pci 1c.0 on end # PCIE_PORT1 |
| device pci 1c.1 on end # PCIE_PORT2 |
| device pci 1c.2 off end # PCIE_PORT3 |
| device pci 1c.3 off end # PCIE_PORT4 |
| device pci 1d.0 on end # EHCI |
| device pci 1e.0 on end # SIO_DMA2 |
| device pci 1e.1 off end # PWM1 |
| device pci 1e.2 off end # PWM2 |
| device pci 1e.3 off end # HSUART1 |
| device pci 1e.4 on end # HSUART2 |
| device pci 1e.5 on end # SPI |
| device pci 1f.0 on |
| chip ec/google/chromeec |
| # We only have one init function that |
| # we need to call to initialize the |
| # keyboard part of the EC. |
| device pnp ff.1 on # dummy address |
| end |
| end |
| end # LPC Bridge |
| device pci 1f.3 off end # SMBus |
| end |
| end |