| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| |
| config SOUTHBRIDGE_INTEL_IBEXPEAK |
| bool |
| |
| if SOUTHBRIDGE_INTEL_IBEXPEAK |
| |
| config SOUTH_BRIDGE_OPTIONS # dummy |
| def_bool y |
| select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
| select IOAPIC |
| select HAVE_SMI_HANDLER |
| select USE_WATCHDOG_ON_BOOT |
| select PCIEXP_ASPM |
| select PCIEXP_COMMON_CLOCK |
| select SOUTHBRIDGE_INTEL_COMMON_FINALIZE |
| select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ |
| select SOUTHBRIDGE_INTEL_COMMON_SMBUS |
| select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9 |
| select SOUTHBRIDGE_INTEL_COMMON_SMM |
| select SOUTHBRIDGE_INTEL_COMMON_PMCLIB |
| select SOUTHBRIDGE_INTEL_COMMON_PMBASE |
| select SOUTHBRIDGE_INTEL_COMMON_RTC |
| select SOUTHBRIDGE_INTEL_COMMON_RESET |
| select HAVE_USBDEBUG_OPTIONS |
| select COMMON_FADT |
| select INTEL_DESCRIPTOR_MODE_CAPABLE |
| select SOUTHBRIDGE_INTEL_COMMON_GPIO |
| select HAVE_INTEL_CHIPSET_LOCKDOWN |
| select HAVE_POWER_STATE_AFTER_FAILURE |
| select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE |
| select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG |
| select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG |
| |
| config EHCI_BAR |
| hex |
| default 0xfef00000 |
| |
| config DRAM_RESET_GATE_GPIO |
| int |
| default 60 |
| |
| config SERIRQ_CONTINUOUS_MODE |
| bool |
| default n |
| help |
| If you set this option to y, the serial IRQ machine will be |
| operated in continuous mode. |
| |
| config HPET_MIN_TICKS |
| hex |
| default 0x80 |
| |
| endif |