src/southbridge/intel/i82801jx/Kconfig

##
## This file is part of the coreboot project.
##
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
## GNU General Public License for more details.
##

config SOUTHBRIDGE_INTEL_I82801JX
	bool
	select SOUTHBRIDGE_INTEL_COMMON_SMBUS
	select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
	select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ
	select SOUTHBRIDGE_INTEL_COMMON_PMCLIB
	select SOUTHBRIDGE_INTEL_COMMON_PMBASE
	select SOUTHBRIDGE_INTEL_COMMON_RTC
	select SOUTHBRIDGE_INTEL_COMMON_RESET
	select IOAPIC
	select USE_WATCHDOG_ON_BOOT
	select HAVE_SMI_HANDLER
	select HAVE_USBDEBUG_OPTIONS
	select SOUTHBRIDGE_INTEL_COMMON_GPIO
	select INTEL_DESCRIPTOR_MODE_CAPABLE
	select COMMON_FADT
	select SOUTHBRIDGE_INTEL_COMMON_SMM
	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
	select HAVE_POWER_STATE_AFTER_FAILURE
	select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE
	select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
	select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG

if SOUTHBRIDGE_INTEL_I82801JX

config EHCI_BAR
	hex
	default 0xfef00000

## Some enterprise variants may require an IFD
config INTEL_DESCRIPTOR_MODE_REQUIRED
	bool
	default n

config HPET_MIN_TICKS
	hex
	default 0x80
endif