| FLASH 16M { |
| WP_RO@0x0 0x480000 { |
| SI_DESC@0x0 0x1000 |
| IFWI@0x1000 0x27f000 |
| RO_VPD@0x280000 0x4000 |
| RO_SECTION@0x284000 0x1fc000 { |
| FMAP@0x0 0x800 |
| COREBOOT(CBFS)@0x1000 0x1bb000 |
| RO_UNUSED@0x1bc000 0x40000 |
| } |
| } |
| MISC_RW@0x480000 0x30000 { |
| UNIFIED_MRC_CACHE@0x0 0x21000 { |
| RECOVERY_MRC_CACHE@0x0 0x10000 |
| RW_MRC_CACHE@0x10000 0x10000 |
| RW_VAR_MRC_CACHE@0x20000 0x1000 |
| } |
| RW_ELOG@0x21000 0x3000 |
| RW_SHARED@0x24000 0x4000 { |
| SHARED_DATA@0x0 0x2000 |
| VBLOCK_DEV@0x2000 0x2000 |
| } |
| RW_VPD@0x28000 0x2000 |
| RW_NVRAM@0x2a000 0x6000 |
| } |
| RW_LEGACY(CBFS)@0xd30000 0x200000 |
| BIOS_UNUSABLE@0xf30000 0x4f000 |
| DEVICE_EXTENSION@0xf7f000 0x80000 |
| # Currently, it is required that the BIOS region be a multiple of 8KiB. |
| # This is required so that the recovery mechanism can find SIGN_CSE |
| # region aligned to 4K at the center of BIOS region. Since the |
| # descriptor at the beginning uses 4K and BIOS starts at an offset of |
| # 4K, a hole of 4K is created towards the end of the flash to compensate |
| # for the size requirement of BIOS region. |
| # FIT tool thus creates descriptor with following regions: |
| # Descriptor --> 0 to 4K |
| # BIOS --> 4K to 0xf7f000 |
| # Device ext --> 0xf7f000 to 0xfff000 |
| UNUSED_HOLE@0xfff000 0x1000 |
| } |