| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2016 Intel Corporation. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <arch/byteorder.h> |
| #include <cbfs.h> |
| #include <console/console.h> |
| #include <fsp/api.h> |
| #include <gpio.h> |
| #include "gpio.h" |
| #include <soc/romstage.h> |
| #include <soc/gpio.h> |
| #include "spd/spd.h" |
| #include <string.h> |
| |
| void mainboard_memory_init_params(FSPM_UPD *mupd) |
| { |
| FSP_M_CONFIG *mem_cfg; |
| mem_cfg = &mupd->FspmConfig; |
| |
| mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0); |
| mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0); |
| mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); |
| mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); |
| |
| mem_cfg->DqPinsInterleaved = 0; |
| mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data(); |
| if (mainboard_has_dual_channel_mem()) |
| mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; |
| mem_cfg->MemorySpdDataLen = SPD_LEN; |
| } |