commit a342f3937e7ce159fd170ab8cd26ba799a3bc9e4
author Elyes HAOUAS <ehaouas@noos.fr> Wed Oct 17 10:56:26 2018 +0200
committer Patrick Georgi <pgeorgi@google.com> Tue Oct 23 15:52:09 2018 +0000
tree 4bd4540ba11286f465272c1fbee62dbf5f9789f8
parent 9856892297ad997f586a1b4dd0a494f3764a0ce2

src: Remove unneeded whitespace

Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/southbridge/intel/bd82x6x/early_usb.c

diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
index 8df4a00..d4ff783 100644
--- a/src/southbridge/intel/bd82x6x/early_usb.c
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -35,7 +35,7 @@
 	/* Activate PMBAR.  */
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
 
 	/* Unlock registers.  */
 	outw(inw(DEFAULT_PMBASE | UPRWC) | UPRWC_WR_EN,

src/southbridge/intel/fsp_bd82x6x/early_init.c

diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c
index f9f3134..1e281aa 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_init.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c
@@ -142,7 +142,7 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
 
 	printk(BIOS_DEBUG, " done.\n");
 

src/southbridge/intel/fsp_i89xx/early_init.c

diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c
index 7ce3c7f..af79925 100644
--- a/src/southbridge/intel/fsp_i89xx/early_init.c
+++ b/src/southbridge/intel/fsp_i89xx/early_init.c
@@ -29,7 +29,7 @@
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */, 0x80); /* Enable ACPI BAR */
 
 	printk(BIOS_DEBUG, " done.\n");
 

src/southbridge/intel/fsp_i89xx/romstage.c

diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c
index 268ea66..863ff6a 100644
--- a/src/southbridge/intel/fsp_i89xx/romstage.c
+++ b/src/southbridge/intel/fsp_i89xx/romstage.c
@@ -172,7 +172,7 @@
 	/* For reference print FSP version */
 	uint32_t version = MCHBAR32(0x5034);
 	printk(BIOS_DEBUG, "FSP Version %d.%d.%d Build %d\n",
-			version >> 24 , (version >> 16) & 0xff,
+			version >> 24, (version >> 16) & 0xff,
 			(version >> 8) & 0xff, version & 0xff);
 	printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (uint32_t)status);
 

src/southbridge/intel/i82371eb/smbus.c

diff --git a/src/southbridge/intel/i82371eb/smbus.c b/src/southbridge/intel/i82371eb/smbus.c
index 3477c52..5b95c57 100644
--- a/src/southbridge/intel/i82371eb/smbus.c
+++ b/src/southbridge/intel/i82371eb/smbus.c
@@ -68,7 +68,7 @@
 	 * power-on default is 0x7fffbfffh */
 	if (gpo) {
 		/* only 8bit access allowed */
-		outb( gpo        & 0xff, DEFAULT_PMBASE + GPO0);
+		outb(gpo        & 0xff, DEFAULT_PMBASE + GPO0);
 		outb((gpo >>  8) & 0xff, DEFAULT_PMBASE + GPO1);
 		outb((gpo >> 16) & 0xff, DEFAULT_PMBASE + GPO2);
 		outb((gpo >> 24) & 0xff, DEFAULT_PMBASE + GPO3);