| commit | a2389ef3162be930e576af68e613d54ef4884cd4 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Sat Dec 03 13:27:54 2022 +0100 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Tue Dec 06 19:45:05 2022 +0000 |
| tree | 5f2684244fd5351099fdd8367d4d36276f13357a | |
| parent | 421f1ee294e2a68872474869bbeb151cb36c94c8 [diff] |
nb/intel/x4x: Use read32p() Change-Id: Ia974da56090b8f9de03c29cda62bc1fb9ef3a082 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 80375a7..71a0609 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c
@@ -21,7 +21,7 @@ void bootblock_early_northbridge_init(void) { /* Disable LaGrande Technology (LT) */ - read32((void *)TPM_BASE_ADDRESS); + read32p(TPM_BASE_ADDRESS); const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);