diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c
index 80375a7..71a0609 100644
--- a/src/northbridge/intel/x4x/bootblock.c
+++ b/src/northbridge/intel/x4x/bootblock.c
@@ -21,7 +21,7 @@
 void bootblock_early_northbridge_init(void)
 {
 	/* Disable LaGrande Technology (LT) */
-	read32((void *)TPM_BASE_ADDRESS);
+	read32p(TPM_BASE_ADDRESS);
 
 	const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
 	pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32);