| chip soc/intel/meteorlake |
| |
| register "serial_io_i2c_mode" = "{ |
| [PchSerialIoIndexI2C0] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C1] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C2] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C3] = PchSerialIoDisabled, |
| [PchSerialIoIndexI2C4] = PchSerialIoPci, |
| [PchSerialIoIndexI2C5] = PchSerialIoDisabled, |
| }" |
| |
| # Intel Common SoC Config |
| #+-------------------+---------------------------+ |
| #| Field | Value | |
| #+-------------------+---------------------------+ |
| #| I2C4 | cr50 TPM. Early init is | |
| #| | required to set up a BAR | |
| #| | for TPM communication | |
| #+-------------------+---------------------------+ |
| register "common_soc_config" = "{ |
| .i2c[4] = { |
| .early_init = 1, |
| .speed = I2C_SPEED_FAST, |
| .rise_time_ns = 600, |
| .fall_time_ns = 400, |
| .data_hold_time_ns = 50, |
| }, |
| }" |
| |
| device domain 0 on |
| device ref pcie_rp11 on |
| # Enable SSD Card PCIE 11 using clk 7 |
| register "pcie_rp[PCH_RP(11)]" = "{ |
| .clk_src = 7, |
| .clk_req = 7, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end # PCIE11 SSD card |
| device ref i2c4 on |
| chip drivers/i2c/tpm |
| register "hid" = ""GOOG0005"" |
| register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E03_IRQ)" |
| device i2c 50 on end |
| end |
| end |
| device ref soc_espi on |
| chip ec/google/chromeec |
| device pnp 0c09.0 on end |
| end |
| end |
| end |
| end |