commit 9e94dbfcd089db31b2201381f9d83a89cdea86b9
author Kyösti Mälkki <kyosti.malkki@gmail.com> Thu Jan 08 20:03:18 2015 +0200
committer Kyösti Mälkki <kyosti.malkki@gmail.com> Tue Mar 10 23:42:10 2015 +0100
tree f73b282c8e37e29966f6a86419ceead0f6e5f39a
parent a63719407fc5fad17eebe0e5086511a511466353

ACPI: Get S3 resume state from romstage_handoff

There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.

Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>

src/soc/intel/baytrail/ramstage.c

diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 96229307..9e429ab 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -27,8 +27,8 @@
 #include <device/device.h>
 #include <device/pci_def.h>
 #include <device/pci_ops.h>
-#include <romstage_handoff.h>
 #include <stdlib.h>
+#include <string.h>
 
 #include <baytrail/gpio.h>
 #include <baytrail/lpc.h>
@@ -130,13 +130,6 @@
 	attrs->bclk_khz = bus_freq_khz();
 }
 
-static inline void set_acpi_sleep_type(int val)
-{
-#if CONFIG_HAVE_ACPI_RESUME
-	acpi_slp_type = val;
-#endif
-}
-
 /* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
 static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
 {
@@ -166,22 +159,15 @@
 static void s3_resume_prepare(void)
 {
 	global_nvs_t *gnvs;
-	struct romstage_handoff *romstage_handoff;
 
 	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
-
-	romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
-	if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
-		if (gnvs != NULL) {
-			memset(gnvs, 0, sizeof(global_nvs_t));
-		}
-		set_acpi_sleep_type(0);
+	if (gnvs == NULL)
 		return;
-	}
 
-	set_acpi_sleep_type(3);
-
-	s3_save_acpi_wake_source(gnvs);
+	if (!acpi_is_wakeup_s3())
+		memset(gnvs, 0, sizeof(global_nvs_t));
+	else
+		s3_save_acpi_wake_source(gnvs);
 }
 
 void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)

src/soc/intel/baytrail/southcluster.c

diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index d0569b4..c392447 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -29,7 +29,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <pc80/mc146818rtc.h>
-#include <romstage_handoff.h>
 #include <drivers/uart/uart8250reg.h>
 
 #include <baytrail/iomap.h>
@@ -215,7 +214,7 @@
 			read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
 	}
 
-	if (acpi_slp_type == 3)
+	if (acpi_is_wakeup_s3())
 		com1_configure_resume(dev);
 }
 

src/soc/intel/baytrail/xhci.c

diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 8d076c2..19339e4 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -184,7 +184,7 @@
 	/* Route ports to XHCI controller */
 	reg_script_run_on_dev(dev, xhci_route_all_script);
 
-	if (acpi_slp_type == 3)
+	if (acpi_is_wakeup_s3())
 		return;
 
 	/* Reset enabled USB3 ports */
@@ -222,7 +222,7 @@
 	};
 
 	/* Initialize XHCI controller for boot or resume path */
-	if (acpi_slp_type == 3)
+	if (acpi_is_wakeup_s3())
 		reg_script_run_on_dev(dev, xhci_init_resume_script);
 	else
 		reg_script_run_on_dev(dev, xhci_init_boot_script);