ACPI: Get S3 resume state from romstage_handoff
There is nothing platform specific in retrieving S3 resume state from
romstage_handoff structure. Boards without EARLY_CBMEM_INIT update
acpi_slp_type from ACPI power-management block or scratchpad registers.
Change-Id: Ifc3755f891a0810473b3216c1fec8e45908fc1ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8188
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c
index 96229307..9e429ab 100644
--- a/src/soc/intel/baytrail/ramstage.c
+++ b/src/soc/intel/baytrail/ramstage.c
@@ -27,8 +27,8 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <romstage_handoff.h>
#include <stdlib.h>
+#include <string.h>
#include <baytrail/gpio.h>
#include <baytrail/lpc.h>
@@ -130,13 +130,6 @@
attrs->bclk_khz = bus_freq_khz();
}
-static inline void set_acpi_sleep_type(int val)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = val;
-#endif
-}
-
/* Save bit index for first enabled event in PM1_STS for \_SB._SWS */
static void s3_save_acpi_wake_source(global_nvs_t *gnvs)
{
@@ -166,22 +159,15 @@
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
- struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
-
- romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
- if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
- if (gnvs != NULL) {
- memset(gnvs, 0, sizeof(global_nvs_t));
- }
- set_acpi_sleep_type(0);
+ if (gnvs == NULL)
return;
- }
- set_acpi_sleep_type(3);
-
- s3_save_acpi_wake_source(gnvs);
+ if (!acpi_is_wakeup_s3())
+ memset(gnvs, 0, sizeof(global_nvs_t));
+ else
+ s3_save_acpi_wake_source(gnvs);
}
void baytrail_init_pre_device(struct soc_intel_baytrail_config *config)
diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c
index d0569b4..c392447 100644
--- a/src/soc/intel/baytrail/southcluster.c
+++ b/src/soc/intel/baytrail/southcluster.c
@@ -29,7 +29,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <pc80/mc146818rtc.h>
-#include <romstage_handoff.h>
#include <drivers/uart/uart8250reg.h>
#include <baytrail/iomap.h>
@@ -215,7 +214,7 @@
read32(gen_pmcon1) & ~DIS_SLP_X_STRCH_SUS_UP);
}
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
com1_configure_resume(dev);
}
diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c
index 8d076c2..19339e4 100644
--- a/src/soc/intel/baytrail/xhci.c
+++ b/src/soc/intel/baytrail/xhci.c
@@ -184,7 +184,7 @@
/* Route ports to XHCI controller */
reg_script_run_on_dev(dev, xhci_route_all_script);
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
return;
/* Reset enabled USB3 ports */
@@ -222,7 +222,7 @@
};
/* Initialize XHCI controller for boot or resume path */
- if (acpi_slp_type == 3)
+ if (acpi_is_wakeup_s3())
reg_script_run_on_dev(dev, xhci_init_resume_script);
else
reg_script_run_on_dev(dev, xhci_init_boot_script);
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index 53cc4b8..b8eff27 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -394,7 +394,7 @@
static void pch_set_acpi_mode(void)
{
#if CONFIG_HAVE_SMI_HANDLER
- if (acpi_slp_type != 3) {
+ if (!acpi_is_wakeup_s3()) {
printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
outb(APM_CNT_ACPI_DISABLE, APM_CNT);
printk(BIOS_DEBUG, "done.\n");
@@ -551,7 +551,7 @@
/* Allocate ACPI NVS in CBMEM */
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
- if (acpi_slp_type != 3 && gnvs)
+ if (!acpi_is_wakeup_s3() && gnvs)
memset(gnvs, 0, sizeof(global_nvs_t));
}
diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c
index 9ec1d44..2a0ce66 100644
--- a/src/soc/intel/broadwell/me.c
+++ b/src/soc/intel/broadwell/me.c
@@ -830,13 +830,11 @@
static void intel_me_enable(device_t dev)
{
-#if CONFIG_HAVE_ACPI_RESUME
/* Avoid talking to the device in S3 path */
- if (acpi_slp_type == 3) {
+ if (acpi_is_wakeup_s3()) {
dev->enabled = 0;
pch_disable_devfn(dev);
}
-#endif
}
static struct device_operations device_ops = {
diff --git a/src/soc/intel/broadwell/ramstage.c b/src/soc/intel/broadwell/ramstage.c
index 0563064..2097f2f 100644
--- a/src/soc/intel/broadwell/ramstage.c
+++ b/src/soc/intel/broadwell/ramstage.c
@@ -21,8 +21,8 @@
#include <cbmem.h>
#include <console/console.h>
#include <device/device.h>
-#include <romstage_handoff.h>
#include <stdlib.h>
+#include <string.h>
#include <broadwell/nvs.h>
#include <broadwell/pm.h>
#include <broadwell/ramstage.h>
@@ -54,31 +54,18 @@
gnvs->pm1i);
}
-static inline void set_acpi_sleep_type(int val)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = val;
-#endif
-}
-
static void s3_resume_prepare(void)
{
- global_nvs_t *gnvs;
- struct romstage_handoff *romstage_handoff;
+ global_nvs_t *gnvs;
- gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
+ if (gnvs == NULL)
+ return;
- romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
- if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
- if (gnvs != NULL) {
- memset(gnvs, 0, sizeof(global_nvs_t));
- }
- set_acpi_sleep_type(0);
- return;
- }
-
- set_acpi_sleep_type(3);
- s3_save_acpi_wake_source(gnvs);
+ if (!acpi_is_wakeup_s3())
+ memset(gnvs, 0, sizeof(global_nvs_t));
+ else
+ s3_save_acpi_wake_source(gnvs);
}
void broadwell_init_pre_device(void *chip_info)
diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c
index a745101..d66d036 100644
--- a/src/soc/intel/broadwell/refcode.c
+++ b/src/soc/intel/broadwell/refcode.c
@@ -30,15 +30,6 @@
#include <broadwell/pei_wrapper.h>
#include <broadwell/ramstage.h>
-static inline int is_s3_resume(void)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- return acpi_slp_type == 3;
-#else
- return 0;
-#endif
-}
-
static inline struct ramstage_cache *next_cache(struct ramstage_cache *c)
{
return (struct ramstage_cache *)&c->program[c->size];
@@ -136,7 +127,7 @@
};
int ret;
- if (is_s3_resume()) {
+ if (acpi_is_wakeup_s3()) {
return load_refcode_from_cache();
}
diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c
index 74c43f2..ac021fb 100644
--- a/src/soc/intel/broadwell/systemagent.c
+++ b/src/soc/intel/broadwell/systemagent.c
@@ -29,7 +29,6 @@
#include <stdlib.h>
#include <string.h>
#include <cbmem.h>
-#include <romstage_handoff.h>
#include <vendorcode/google/chromeos/chromeos.h>
#include <broadwell/cpu.h>
#include <broadwell/iomap.h>
@@ -412,27 +411,6 @@
set_power_limits(28);
}
-static void systemagent_enable(device_t dev)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- struct romstage_handoff *handoff;
-
- handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
-
- if (handoff == NULL) {
- printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
- acpi_slp_type = 0;
- } else if (handoff->s3_resume) {
- printk(BIOS_DEBUG, "S3 Resume.\n");
- acpi_slp_type = 3;
- } else {
- printk(BIOS_DEBUG, "Normal boot.\n");
- acpi_slp_type = 0;
- }
-#endif
-}
-
-
unsigned long acpi_fill_slit(unsigned long current)
{
// Not implemented
@@ -451,7 +429,6 @@
.set_resources = &pci_dev_set_resources,
.enable_resources = &pci_dev_enable_resources,
.init = &systemagent_init,
- .enable = &systemagent_enable,
.ops_pci = &broadwell_pci_ops,
};
diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c
index 814b16e..ad1db33 100644
--- a/src/soc/intel/fsp_baytrail/ramstage.c
+++ b/src/soc/intel/fsp_baytrail/ramstage.c
@@ -19,6 +19,7 @@
#include <arch/cpu.h>
#include <arch/acpi.h>
+#include <cbmem.h>
#include <console/console.h>
#include <cpu/intel/microcode.h>
#include <cpu/x86/cr.h>
@@ -26,8 +27,8 @@
#include <device/device.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
-#include <romstage_handoff.h>
#include <stdlib.h>
+#include <string.h>
#include <baytrail/gpio.h>
#include <baytrail/lpc.h>
@@ -125,31 +126,16 @@
attrs->bclk_khz = bus_freq_khz();
}
-
-static inline void set_acpi_sleep_type(int val)
-{
-#if CONFIG_HAVE_ACPI_RESUME
- acpi_slp_type = val;
-#endif
-}
-
static void s3_resume_prepare(void)
{
global_nvs_t *gnvs;
- struct romstage_handoff *romstage_handoff;
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t));
-
- romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO);
- if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) {
- if (gnvs != NULL) {
- memset(gnvs, 0, sizeof(global_nvs_t));
- }
- set_acpi_sleep_type(0);
+ if (gnvs == NULL)
return;
- }
- set_acpi_sleep_type(3);
+ if (!acpi_is_wakeup_s3())
+ memset(gnvs, 0, sizeof(global_nvs_t));
}
void baytrail_init_pre_device(void)
diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c
index ec2f94f..d515286 100644
--- a/src/soc/intel/fsp_baytrail/southcluster.c
+++ b/src/soc/intel/fsp_baytrail/southcluster.c
@@ -33,7 +33,6 @@
#include <pc80/i8254.h>
#include <pc80/i8259.h>
#include <pc80/isa-dma.h>
-#include <romstage_handoff.h>
#include <baytrail/baytrail.h>
#include <baytrail/iomap.h>