mb/lenovo/x220: Add x1 as a variant
ThinkPad X1 ( https://www.thinkwiki.org/wiki/Category:X1 ) is nearly a
clone of X220, with additional USB3 controller on pci-e (as i7 variant
of x220), and a powered ESATA port wired to ata4 (Linux' annotation).
Documentation added.
Tested:
- CPU i5-2520M
- Slotted DIMM 8GiB
- Camera
- Mini pci-e on wlan slot
- Msata on wwan slot
- On board SDHCI connected to pci-e
- USB3 controller connected to pci-e
- NVRAM options for North and South bridges
- S3
- TPM1 on LPC
- Linux 4.9.110-3 within Debian GNU/Linux stable, loaded from
SeaBIOS, or Linux payload (Heads)
Not tested:
- Fingerprint reader on USB2
- Onboard USB2 interfaces (wlan slot, wwan slot)
Change-Id: Ibbc45f22c63b77ac95c188db825d0d7e2b03d2d1
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 4e2b742..93ee828 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -48,12 +48,15 @@
## Lenovo
+- [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md)
- [T4xx common](lenovo/t4xx_series.md)
+- [X2xx common](lenovo/x2xx_series.md)
### Sandy Bridge series
- [T420](lenovo/t420.md)
- [T420 / T520 / X220 / T420s / W520 common](lenovo/xx20_series.md)
+- [x1](lenovo/x1.md)
### Ivy Bridge series
diff --git a/Documentation/mainboard/lenovo/t4xx_series.md b/Documentation/mainboard/lenovo/t4xx_series.md
index 3ca7047..88b503e 100644
--- a/Documentation/mainboard/lenovo/t4xx_series.md
+++ b/Documentation/mainboard/lenovo/t4xx_series.md
@@ -3,6 +3,8 @@
A skilled engineer takes around 40 minutes to disassemble, flash and reassemble
the whole device.
+Read their [Hardware Maintenance Manual](thinkpad_hmm.md) for detailed steps.
+
## Steps to access the flash IC
* Unplug the main battery
diff --git a/Documentation/mainboard/lenovo/thinkpad_hmm.md b/Documentation/mainboard/lenovo/thinkpad_hmm.md
new file mode 100644
index 0000000..2283832
--- /dev/null
+++ b/Documentation/mainboard/lenovo/thinkpad_hmm.md
@@ -0,0 +1,6 @@
+# Obtain Hardware Maintenance Manual of ThinkPads
+
+You are suggested obtain the "Hardware Maintenance Manual" for your corresponding
+model as a guidance. Some can be found from [Hardware Specifications of ThinkWiki].
+
+[Hardware Specifications of ThinkWiki]: https://www.thinkwiki.org/wiki/Hardware_Specifications
diff --git a/Documentation/mainboard/lenovo/x1.md b/Documentation/mainboard/lenovo/x1.md
new file mode 100644
index 0000000..cb9248a
--- /dev/null
+++ b/Documentation/mainboard/lenovo/x1.md
@@ -0,0 +1,24 @@
+# Lenovo X1
+
+## Flashing instructions
+
+
+
+You have to remove the keyboard in order to access the flash IC (the chip
+inside the red circle on the picture above), as it is under the wider
+cable (already detached from MB in the picture) connecting the keyboard
+to the mainboard.
+
+The flash IC can be a SOIC-8 one or a WSON-8 one, and may be covered with
+a piece of insulation tape.
+
+For more details have a look at [T420 / T520 / X220 / T420s / W520 common] and
+
+```eval_rst
+:doc:`../../flash_tutorial/ext_power`
+```
+
+Steps to access the flash IC are described here [X2xx series].
+
+[X2xx series]: x2xx_series.md
+[T420 / T520 / X220 / T420s / W520 common]: xx20_series.md
diff --git a/Documentation/mainboard/lenovo/x1_flash_ic.jpg b/Documentation/mainboard/lenovo/x1_flash_ic.jpg
new file mode 100644
index 0000000..6d0b9f7
--- /dev/null
+++ b/Documentation/mainboard/lenovo/x1_flash_ic.jpg
Binary files differ
diff --git a/Documentation/mainboard/lenovo/x2xx_series.md b/Documentation/mainboard/lenovo/x2xx_series.md
new file mode 100644
index 0000000..424fc37
--- /dev/null
+++ b/Documentation/mainboard/lenovo/x2xx_series.md
@@ -0,0 +1,12 @@
+# Lenovo x2xx series disassembly instructions
+
+Removing the keyboard and palmrest would allow you to access the flash chip.
+
+Read their [Hardware Maintenance Manual](thinkpad_hmm.md) for detailed steps.
+
+## Steps to access the flash IC
+
+* Unplug the main battery
+* Remove the keyboard
+* Remove the palmrest
+
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index 0f7cbe7..f8f7055 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -29,9 +29,21 @@
string
default lenovo/x220
+config VARIANT_DIR
+ string
+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default "x1" if BOARD_LENOVO_X1
+
+
config MAINBOARD_PART_NUMBER
string
- default "ThinkPad X220"
+ default "ThinkPad X220" if BOARD_LENOVO_X220
+ default "ThinkPad X220i" if BOARD_LENOVO_X220I
+ default "ThinkPad X1" if BOARD_LENOVO_X1
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
config MAX_CPUS
int
@@ -48,6 +60,7 @@
config VGA_BIOS_FILE
string
default "pci8086,0116.rom" if BOARD_LENOVO_X220I
+ # FIXME: x1 with i3 cpu may also use "pci8086,0116.rom"
default "pci8086,0126.rom"
config VGA_BIOS_ID
@@ -61,6 +74,7 @@
config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
hex
- default 0x21db
+ default 0x21db if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default 0x21e8 if BOARD_LENOVO_X1
-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
index 0f9d3fc..988ac4f 100644
--- a/src/mainboard/lenovo/x220/Kconfig.name
+++ b/src/mainboard/lenovo/x220/Kconfig.name
@@ -3,3 +3,6 @@
config BOARD_LENOVO_X220I
bool "ThinkPad X220i"
+
+config BOARD_LENOVO_X1
+ bool "ThinkPad X1"
diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc
index 2dab950..2c52c21 100644
--- a/src/mainboard/lenovo/x220/Makefile.inc
+++ b/src/mainboard/lenovo/x220/Makefile.inc
@@ -14,6 +14,7 @@
##
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
-romstage-y += gpio.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+romstage-y += variants/$(VARIANT_DIR)/romstage.c
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb
index 969ae38..2a1507c 100644
--- a/src/mainboard/lenovo/x220/devicetree.cb
+++ b/src/mainboard/lenovo/x220/devicetree.cb
@@ -159,8 +159,6 @@
register "event7_enable" = "0x81"
register "event8_enable" = "0x7b"
register "event9_enable" = "0xff"
- register "eventa_enable" = "0x01"
- register "eventb_enable" = "0xf0"
register "eventc_enable" = "0xff"
register "eventd_enable" = "0xff"
register "evente_enable" = "0x0d"
diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c
index 3429aad..62b887e 100644
--- a/src/mainboard/lenovo/x220/romstage.c
+++ b/src/mainboard/lenovo/x220/romstage.c
@@ -98,23 +98,6 @@
*pei_data = pei_data_template;
}
-const struct southbridge_usb_port mainboard_usb_ports[] = {
- { 1, 0, 0 },
- { 1, 1, 1 },
- { 1, 1, 3 },
- { 1, 1, 3 },
- { 1, 1, -1 },
- { 1, 1, -1 },
- { 1, 0, 2 },
- { 1, 0, 2 },
- { 1, 1, 6 },
- { 1, 1, 5 },
- { 1, 1, 6 },
- { 1, 1, 6 },
- { 1, 1, 7 },
- { 1, 1, 6 },
-};
-
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
{
read_spd (&spd[0], 0x50, id_only);
diff --git a/src/mainboard/lenovo/x220/variants/x1/data.vbt b/src/mainboard/lenovo/x220/variants/x1/data.vbt
new file mode 100644
index 0000000..63350f1
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/x220/variants/x1/gpio.c b/src/mainboard/lenovo/x220/variants/x1/gpio.c
new file mode 100644
index 0000000..023f3f3
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/gpio.c
@@ -0,0 +1,221 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2014 Vladimir Serbinenko
+ * Copyright (C) 2018 Bill Xie
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio8 = GPIO_LEVEL_HIGH,
+ .gpio10 = GPIO_LEVEL_HIGH,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio24 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio6 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_GPIO,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_NATIVE,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio42 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
new file mode 100644
index 0000000..54f6485
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb
@@ -0,0 +1,85 @@
+chip northbridge/intel/sandybridge
+
+ register "gpu_dp_b_hotplug" = "0x04"
+ register "gpu_dp_c_hotplug" = "0x04"
+ register "gpu_dp_d_hotplug" = "0x04"
+ register "gpu_panel_power_cycle_delay" = "3"
+ register "gpu_panel_power_up_delay" = "250" # T1+T2: 25ms
+ register "gpu_panel_power_down_delay" = "250" # T5+T6: 35ms
+ register "gpu_panel_power_backlight_on_delay" = "2500" # T3: 250ms
+ register "gpu_panel_power_backlight_off_delay" = "2500" # T4: 250ms
+
+ register "gpu_cpu_backlight" = "0x1312"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device domain 0 on
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21e8
+ end # host bridge
+ device pci 02.0 on
+ subsystemid 0x17aa 0x21e8
+ end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ # Enable SATA ports 0 (HDD bay) & 2 (msata) & 3 (esatap)
+ register "sata_port_map" = "0x1d"
+ # X1 does not have ExpressCard slot
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
+
+ device pci 1a.0 on
+ subsystemid 0x17aa 0x21e8
+ end # USB2 EHCI #2
+ device pci 1b.0 on
+ subsystemid 0x17aa 0x21e8
+ end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #2 (wlan)
+ device pci 1c.2 off end # PCIe Port #3
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 on
+ subsystemid 0x17aa 0x21e8
+ chip drivers/ricoh/rce822 # Ricoh cardreader
+ device pci 00.0 on
+ subsystemid 0x17aa 0x21e8
+ end
+ end
+ end # PCIe Port #5 (SD)
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 on
+ subsystemid 0x17aa 0x21e8
+ end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on
+ subsystemid 0x17aa 0x21e8
+ end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ subsystemid 0x17aa 0x21e8
+ chip ec/lenovo/h8
+ register "config2" = "0xe0"
+ register "config3" = "0xc0"
+
+ register "beepmask0" = "0xfe"
+ register "beepmask1" = "0x96"
+
+ register "event5_enable" = "0x3c"
+ register "evente_enable" = "0x3d"
+
+ # BDC detection is broken on this board:
+ register "has_bdc_detection" = "0"
+ end
+ end # LPC bridge
+ device pci 1f.2 on
+ subsystemid 0x17aa 0x21e8
+ end # SATA Controller 1
+ device pci 1f.3 on
+ subsystemid 0x17aa 0x21e8
+ end # SMBus
+ device pci 1f.6 on
+ subsystemid 0x17aa 0x21e8
+ end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x220/variants/x1/romstage.c b/src/mainboard/lenovo/x220/variants/x1/romstage.c
new file mode 100644
index 0000000..a1932cc
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x1/romstage.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 0, 0, 3 },
+ { 0, 0, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 0, 7 },
+ { 1, 1, 7 },
+ { 1, 1, 7 },
+ { 1, 0, 7 },
+};
diff --git a/src/mainboard/lenovo/x220/data.vbt b/src/mainboard/lenovo/x220/variants/x220/data.vbt
similarity index 100%
rename from src/mainboard/lenovo/x220/data.vbt
rename to src/mainboard/lenovo/x220/variants/x220/data.vbt
Binary files differ
diff --git a/src/mainboard/lenovo/x220/gpio.c b/src/mainboard/lenovo/x220/variants/x220/gpio.c
similarity index 100%
rename from src/mainboard/lenovo/x220/gpio.c
rename to src/mainboard/lenovo/x220/variants/x220/gpio.c
diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
new file mode 100644
index 0000000..604eadf
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb
@@ -0,0 +1,12 @@
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ device pci 1f.0 on #LPC bridge
+ chip ec/lenovo/h8
+ register "eventa_enable" = "0x01"
+ register "eventb_enable" = "0xf0"
+ end
+ end # LPC bridge
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/x220/variants/x220/romstage.c b/src/mainboard/lenovo/x220/variants/x220/romstage.c
new file mode 100644
index 0000000..88a9396
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x220/romstage.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ * Copyright (C) 2014 Vladimir Serbinenko
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, -1 },
+ { 1, 1, -1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 1, 6 },
+ { 1, 1, 5 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+};
