| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; either version 2 of the License, or |
| * (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <stdint.h> |
| #include <stdlib.h> |
| #include <device/pci_def.h> |
| #include <arch/io.h> |
| #include <device/pnp_def.h> |
| #include <arch/hlt.h> |
| #include <console/console.h> |
| #include "cpu/x86/bist.h" |
| #include "cpu/x86/msr.h" |
| #include <cpu/amd/lxdef.h> |
| #include <cpu/amd/geode_post_code.h> |
| #include "southbridge/amd/cs5536/cs5536.h" |
| #include <spd.h> |
| |
| #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| |
| #include "southbridge/amd/cs5536/cs5536_early_smbus.c" |
| #include "southbridge/amd/cs5536/cs5536_early_setup.c" |
| #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| |
| static inline int spd_read_byte(unsigned int device, unsigned int address) |
| { |
| return smbus_read_byte(device, address); |
| } |
| |
| #define ManualConf 1 /* Do automatic strapped PLL config */ |
| //#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ |
| //#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ |
| #define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ |
| //0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 |
| /* Hold Count - how long we will sit in reset */ |
| #define PLLMSRlo 0x00DE6000 |
| |
| #include "northbridge/amd/lx/raminit.h" |
| #include "northbridge/amd/lx/pll_reset.c" |
| #include "northbridge/amd/lx/raminit.c" |
| #include "lib/generic_sdram.c" |
| #include "cpu/amd/model_lx/cpureginit.c" |
| #include "cpu/amd/model_lx/syspreinit.c" |
| #include "cpu/amd/model_lx/msrinit.c" |
| |
| static void mb_gpio_init(void) |
| { |
| /* Early mainboard specific GPIO setup. */ |
| } |
| |
| void main(unsigned long bist) |
| { |
| post_code(0x01); |
| |
| static const struct mem_controller memctrl[] = { |
| {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} |
| }; |
| |
| SystemPreInit(); |
| msr_init(); |
| |
| cs5536_early_setup(); |
| |
| /* Note: must do this AFTER the early_setup! It is counting on some |
| * early MSR setup for CS5536. |
| */ |
| w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| mb_gpio_init(); |
| uart_init(); |
| console_init(); |
| |
| /* Halt if there was a built in self test failure */ |
| report_bist_failure(bist); |
| |
| pll_reset(ManualConf); |
| |
| cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED); |
| |
| sdram_initialize(1, memctrl); |
| |
| /* ram_check(0, 640 * 1024); */ |
| |
| /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ |
| return; |
| } |
| |