| commit | 9a83eae71ef838037024f5316b0e745bc2810cd5 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Sat Dec 03 13:31:38 2022 +0100 |
| committer | Felix Held <felix-coreboot@felixheld.de> | Tue Dec 06 19:45:59 2022 +0000 |
| tree | 5debbd100bba57c99e76782319c0217364c8de29 | |
| parent | a2389ef3162be930e576af68e613d54ef4884cd4 [diff] [blame] |
nb/intel/haswell: Use {read,write}32p()
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 4980f9b..ce14915 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c
@@ -47,7 +47,7 @@ if (CONFIG(INTEL_TXT)) { printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n"); - intel_txt_log_acm_error(read32((void *)TXT_ERROR)); + intel_txt_log_acm_error(read32p(TXT_ERROR)); intel_txt_log_spad();