nb/intel/haswell: Use {read,write}32p()
Change-Id: Ibbefa3d57b17a6a8eb0831eeadf6d629e2765567
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 13c2dcd..e47deb5 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -169,14 +169,14 @@
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
- reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS));
- write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS), reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
+ reg32 = read32p(GFXVT_BASE_ADDRESS + ARCHDIS);
+ write32p(GFXVT_BASE_ADDRESS + ARCHDIS, reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
/* Clear SPCAPCTRL */
- reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL;
+ reg32 = read32p(VTVC0_BASE_ADDRESS + ARCHDIS) & ~SPCAPCTRL;
/* Set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy config registers */
- write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS),
+ write32p(VTVC0_BASE_ADDRESS + ARCHDIS,
reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
}
diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c
index 4980f9b..ce14915 100644
--- a/src/northbridge/intel/haswell/romstage.c
+++ b/src/northbridge/intel/haswell/romstage.c
@@ -47,7 +47,7 @@
if (CONFIG(INTEL_TXT)) {
printk(BIOS_DEBUG, "Check TXT_ERROR register after MRC\n");
- intel_txt_log_acm_error(read32((void *)TXT_ERROR));
+ intel_txt_log_acm_error(read32p(TXT_ERROR));
intel_txt_log_spad();