| chip northbridge/intel/haswell | |
| register "panel_cfg" = "{ | |
| .up_delay_ms = 200, | |
| .down_delay_ms = 50, | |
| .cycle_delay_ms = 500, | |
| .backlight_on_delay_ms = 1, | |
| .backlight_off_delay_ms = 200, | |
| .backlight_pwm_hz = 200, | |
| }" | |
| device domain 0 on | |
| chip southbridge/intel/lynxpoint | |
| register "sata_devslp_disable" = "0x1" | |
| # DTLE DATA / EDGE values | |
| register "sata_port0_gen3_dtle" = "0x5" | |
| register "sata_port1_gen3_dtle" = "0x5" | |
| # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP | |
| register "icc_clock_disable" = "0x013c0000" | |
| end | |
| end | |
| end |