skylake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Skylake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built and tested on nami system
Change-Id: Idc82f3d2f805b92fb3005d2f49098e55cb142e45
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb
index e453aa4..b610904 100644
--- a/src/mainboard/51nb/x210/devicetree.cb
+++ b/src/mainboard/51nb/x210/devicetree.cb
@@ -118,10 +118,11 @@
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (left)
# PL1 override 25W
- register "tdp_pl1_override" = "25"
-
# PL2 override 44W
- register "tdp_pl2_override" = "44"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 25,
+ .tdp_pl2_override = 44,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb
index 9ff8ceb..254eff8 100644
--- a/src/mainboard/asrock/h110m/devicetree.cb
+++ b/src/mainboard/asrock/h110m/devicetree.cb
@@ -247,7 +247,9 @@
register "PcieRpHotPlug[6]" = "1"
# PL2 override 91W
- register "tdp_pl2_override" = "91"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 91,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 564b45d..3b1f22c 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -250,8 +250,10 @@
register "speed_shift_enable" = "1"
register "dptf_enable" = "1"
- register "tdp_pl1_override" = "7"
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 15,
+ }"
register "tcc_offset" = "10"
device cpu_cluster 0 on
diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c
index 6627c47..c86be82 100644
--- a/src/mainboard/google/fizz/mainboard.c
+++ b/src/mainboard/google/fizz/mainboard.c
@@ -9,6 +9,7 @@
#include <ec/ec.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
+#include <intelblocks/power_limit.h>
#include <variant/gpio.h>
#include <smbios.h>
#include <soc/gpio.h>
@@ -99,7 +100,7 @@
* | n (U22) | 29 | .9n | .9n | x(43) |
* +-------------+-----+---------+---------+-------+
*/
-static void mainboard_set_power_limits(config_t *conf)
+static void mainboard_set_power_limits(struct soc_power_limits_config *conf)
{
enum usb_chg_type type;
u32 watts;
@@ -215,9 +216,11 @@
static void mainboard_enable(struct device *dev)
{
+ struct soc_power_limits_config *soc_conf;
config_t *conf = config_of_soc();
- mainboard_set_power_limits(conf);
+ soc_conf = &conf->power_limits_config;
+ mainboard_set_power_limits(soc_conf);
dev->ops->init = mainboard_init;
dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
index f02acce..b8455fe 100644
--- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb
@@ -325,8 +325,10 @@
}"
register "speed_shift_enable" = "1"
- register "tdp_psyspl2" = "90"
- register "psys_pmax" = "120"
+ register "power_limits_config" = "{
+ .tdp_psyspl2 = 90,
+ .psys_pmax = 120,
+ }"
register "tcc_offset" = "6" # TCC of 94C
device cpu_cluster 0 on
diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb
index f978240..bfa260e 100644
--- a/src/mainboard/google/fizz/variants/karma/overridetree.cb
+++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb
@@ -17,7 +17,9 @@
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Side
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Card reader
- register "psys_pmax" = "151"
+ register "power_limits_config" = "{
+ .psys_pmax = 151,
+ }"
device domain 0 on
device pci 14.0 on
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 4e85e21..f7be80d 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -99,7 +99,9 @@
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/google/glados/variants/caroline/overridetree.cb b/src/mainboard/google/glados/variants/caroline/overridetree.cb
index ce36480..7bee2e2 100644
--- a/src/mainboard/google/glados/variants/caroline/overridetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/overridetree.cb
@@ -25,7 +25,9 @@
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Empty
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/cave/overridetree.cb b/src/mainboard/google/glados/variants/cave/overridetree.cb
index ae32b3d..9aeb78a 100644
--- a/src/mainboard/google/glados/variants/cave/overridetree.cb
+++ b/src/mainboard/google/glados/variants/cave/overridetree.cb
@@ -18,7 +18,9 @@
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Type-A Port 2
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/chell/overridetree.cb b/src/mainboard/google/glados/variants/chell/overridetree.cb
index c6ccd20..ad3ae39 100644
--- a/src/mainboard/google/glados/variants/chell/overridetree.cb
+++ b/src/mainboard/google/glados/variants/chell/overridetree.cb
@@ -16,7 +16,9 @@
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/glados/variants/glados/overridetree.cb b/src/mainboard/google/glados/variants/glados/overridetree.cb
index 1bc69ab..c510e92 100644
--- a/src/mainboard/google/glados/variants/glados/overridetree.cb
+++ b/src/mainboard/google/glados/variants/glados/overridetree.cb
@@ -18,7 +18,9 @@
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 2
# PL2 override 15W
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ }"
# Send an extra VR mailbox command for the supported MPS IMVP8 model
register "SendVrMbxCmd" = "1"
diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
index b7ab523..ce943c4 100644
--- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb
@@ -70,9 +70,11 @@
register "PmTimerDisabled" = "1"
register "speed_shift_enable" = "1"
- register "tdp_pl1_override" = "7"
- register "tdp_pl2_override" = "15"
- register "psys_pmax" = "45"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 15,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10"
register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/mainboard/google/poppy/variants/atlas/mainboard.c b/src/mainboard/google/poppy/variants/atlas/mainboard.c
index 7974a28..ea7ee8f 100644
--- a/src/mainboard/google/poppy/variants/atlas/mainboard.c
+++ b/src/mainboard/google/poppy/variants/atlas/mainboard.c
@@ -5,6 +5,7 @@
#include <device/device.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <intelblocks/power_limit.h>
#define PL2_AML 18
#define PL2_KBL 15
@@ -25,8 +26,10 @@
/* Override dev tree settings per board */
void variant_devtree_update(void)
{
+ struct soc_power_limits_config *soc_conf;
config_t *cfg = config_of_soc();
+ soc_conf = &cfg->power_limits_config;
/* Update PL2 based on CPU */
- cfg->tdp_pl2_override = get_pl2();
+ soc_conf->tdp_pl2_override = get_pl2();
}
diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
index 7772534..0f3cc04 100644
--- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb
@@ -267,9 +267,11 @@
}"
register "speed_shift_enable" = "1"
- register "psys_pmax" = "45"
# PL2 override 15W for KBL-Y
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb
index e4d148c..4fa41c5 100644
--- a/src/mainboard/google/poppy/variants/nami/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb
@@ -288,7 +288,9 @@
register "speed_shift_enable" = "1"
register "tcc_offset" = "3" # TCC of 97C
- register "psys_pmax" = "101"
+ register "power_limits_config" = "{
+ .psys_pmax = 101,
+ }"
device cpu_cluster 0 on
device lapic 0 on end
diff --git a/src/mainboard/google/poppy/variants/nami/mainboard.c b/src/mainboard/google/poppy/variants/nami/mainboard.c
index 648e0d0..8d5d0c4 100644
--- a/src/mainboard/google/poppy/variants/nami/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nami/mainboard.c
@@ -10,6 +10,7 @@
#include <drivers/intel/gma/opregion.h>
#include <ec/google/chromeec/ec.h>
#include <intelblocks/mp_init.h>
+#include <intelblocks/power_limit.h>
#include <smbios.h>
#include <soc/ramstage.h>
#include <string.h>
@@ -279,8 +280,11 @@
break;
}
+ struct soc_power_limits_config *soc_conf;
+ soc_conf = &cfg->power_limits_config;
+
/* Update PL2 based on SKU. */
- cfg->tdp_pl2_override = get_pl2(pl2_id);
+ soc_conf->tdp_pl2_override = get_pl2(pl2_id);
/* Overwrite settings for different projects based on OEM ID*/
oem_index = find_sku_mapping(read_oem_id());
diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
index c3404bf..c55562d 100644
--- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb
@@ -288,9 +288,11 @@
}"
register "speed_shift_enable" = "1"
- register "psys_pmax" = "45"
# PL2 override 15W for KBL-Y
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
index 96fcc39..8819350 100644
--- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb
@@ -66,9 +66,11 @@
# Set speed_shift_enable to 1 to enable P-States, and 0 to disable
register "speed_shift_enable" = "1"
- register "tdp_pl1_override" = "7"
- register "tdp_pl2_override" = "18"
- register "psys_pmax" = "45"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 7,
+ .tdp_pl2_override = 18,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10"
register "pirqa_routing" = "PCH_IRQ11"
diff --git a/src/mainboard/google/poppy/variants/nocturne/mainboard.c b/src/mainboard/google/poppy/variants/nocturne/mainboard.c
index 8d72144..1482b34 100644
--- a/src/mainboard/google/poppy/variants/nocturne/mainboard.c
+++ b/src/mainboard/google/poppy/variants/nocturne/mainboard.c
@@ -5,6 +5,7 @@
#include <device/device.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
+#include <intelblocks/power_limit.h>
/* PL2 limit in watts for AML and KBL */
#define PL2_AML 18
@@ -26,8 +27,10 @@
/* Override dev tree settings per board */
void variant_devtree_update(void)
{
+ struct soc_power_limits_config *soc_conf;
config_t *cfg = config_of_soc();
+ soc_conf = &cfg->power_limits_config;
/* Update PL2 based on CPU */
- cfg->tdp_pl2_override = get_pl2();
+ soc_conf->tdp_pl2_override = get_pl2();
}
diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
index 6557870..de7023d 100644
--- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb
@@ -246,9 +246,11 @@
}"
register "speed_shift_enable" = "1"
- register "psys_pmax" = "45"
# PL2 override 18W for AML-Y
- register "tdp_pl2_override" = "18"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 18,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
index 146d8d2..8c22ade 100644
--- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb
+++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb
@@ -268,9 +268,11 @@
}"
register "speed_shift_enable" = "1"
- register "psys_pmax" = "45"
# PL2 override 15W for KBL-Y
- register "tdp_pl2_override" = "15"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 15,
+ .psys_pmax = 45,
+ }"
register "tcc_offset" = "10" # TCC of 90C
# Use default SD card detect GPIO configuration
diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index 436a4ed..fa50283 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -111,7 +111,9 @@
}"
# PL2 override 60W
- register "tdp_pl2_override" = "60"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 60,
+ }"
# Power Limit Related
register "PowerLimit4" = "0"
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 46d7929..91abfe6 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -156,7 +156,9 @@
}"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Use default SD card detect GPIO configuration
#register "sdcard_cd_gpio_default" = "GPP_D10"
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index ab30614..acd197b 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -166,7 +166,9 @@
}"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index f4ccb1b..4811a41 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -213,7 +213,9 @@
}"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb
index f54b877..95874bb 100644
--- a/src/mainboard/libretrend/lt1000/devicetree.cb
+++ b/src/mainboard/libretrend/lt1000/devicetree.cb
@@ -171,7 +171,9 @@
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # F_USB3 header
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb
index 854f5db..a439e02 100644
--- a/src/mainboard/purism/librem_skl/devicetree.cb
+++ b/src/mainboard/purism/librem_skl/devicetree.cb
@@ -168,7 +168,9 @@
register "PcieRpEnable[8]" = "1"
# PL2 override 25W
- register "tdp_pl2_override" = "25"
+ register "power_limits_config" = "{
+ .tdp_pl2_override = 25,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"
diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
index b55ef41..7d54d33 100644
--- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
+++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb
@@ -170,10 +170,11 @@
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC1)" # TODO Unknown. Maybe USBC?
# PL1 override 25W
- register "tdp_pl1_override" = "25"
-
# PL2 override 44W
- register "tdp_pl2_override" = "44"
+ register "power_limits_config" = "{
+ .tdp_pl1_override = 25,
+ .tdp_pl2_override = 44,
+ }"
# Send an extra VR mailbox command for the PS4 exit issue
register "SendVrMbxCmd" = "2"