soc/amd/genoa: Enable uart
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Change-Id: I1529657f30b6e228c2e3cd7e0438255522381367
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76507
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig
index b4caa56..af4056a 100644
--- a/src/soc/amd/genoa/Kconfig
+++ b/src/soc/amd/genoa/Kconfig
@@ -19,6 +19,7 @@
select SOC_AMD_COMMON_BLOCK_PCI_MMCONF
select SOC_AMD_COMMON_BLOCK_SMI
select SOC_AMD_COMMON_BLOCK_TSC
+ select SOC_AMD_COMMON_BLOCK_UART
select SOC_AMD_COMMON_BLOCK_USE_ESPI
select X86_CUSTOM_BOOTMEDIA
diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc
index a35146c..ef8f349 100644
--- a/src/soc/amd/genoa/Makefile.inc
+++ b/src/soc/amd/genoa/Makefile.inc
@@ -5,6 +5,7 @@
all-y += reset.c
all-y += config.c
all-y += gpio.c
+all-y += uart.c
bootblock-y += early_fch.c
bootblock-y += aoac.c
diff --git a/src/soc/amd/genoa/early_fch.c b/src/soc/amd/genoa/early_fch.c
index 8de43e2..e134f49 100644
--- a/src/soc/amd/genoa/early_fch.c
+++ b/src/soc/amd/genoa/early_fch.c
@@ -7,6 +7,7 @@
#include <amdblocks/pmlib.h>
#include <amdblocks/uart.h>
#include <soc/southbridge.h>
+#include <soc/uart.h>
/* Before console init */
void fch_pre_init(void)
@@ -14,6 +15,14 @@
fch_enable_cf9_io();
enable_aoac_devices();
+ /*
+ * On reset Range_0 defaults to enabled. We want to start with a clean
+ * slate to not have things unexpectedly enabled.
+ */
+ clear_uart_legacy_config();
+
+ if (CONFIG(AMD_SOC_CONSOLE_UART))
+ set_uart_config(CONFIG_UART_FOR_CONSOLE);
configure_espi_with_mb_hook();
}
diff --git a/src/soc/amd/genoa/include/soc/uart.h b/src/soc/amd/genoa/include/soc/uart.h
new file mode 100644
index 0000000..ae8f118
--- /dev/null
+++ b/src/soc/amd/genoa/include/soc/uart.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef AMD_GENOA_UART_H
+#define AMD_GENOA_UART_H
+
+#include <types.h>
+
+void clear_uart_legacy_config(void); /* disable legacy I/O decode for FCH UART */
+
+#endif /* AMD_GENOA_UART_H */
diff --git a/src/soc/amd/genoa/uart.c b/src/soc/amd/genoa/uart.c
new file mode 100644
index 0000000..df8c54f
--- /dev/null
+++ b/src/soc/amd/genoa/uart.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/mmio.h>
+#include <amdblocks/gpio.h>
+#include <amdblocks/uart.h>
+#include <commonlib/helpers.h>
+#include <soc/aoac_defs.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/southbridge.h>
+#include <soc/uart.h>
+#include <types.h>
+
+static const struct soc_uart_ctrlr_info uart_info[] = {
+ [0] = { APU_UART0_BASE, FCH_AOAC_DEV_UART0, "FUR0", {
+ PAD_NF(GPIO_136, UART0_RXD, PULL_NONE),
+ PAD_NF(GPIO_138, UART0_TXD, PULL_NONE),
+ } },
+ [1] = { APU_UART1_BASE, FCH_AOAC_DEV_UART1, "FUR1", {
+ PAD_NF(GPIO_141, UART1_RXD, PULL_NONE),
+ PAD_NF(GPIO_142, UART1_TXD, PULL_NONE),
+ } },
+ [2] = { APU_UART2_BASE, FCH_AOAC_DEV_UART2, "FUR2", {
+ PAD_NF(GPIO_137, UART2_RXD, PULL_NONE),
+ PAD_NF(GPIO_135, UART2_TXD, PULL_NONE),
+ } },
+};
+
+const struct soc_uart_ctrlr_info *soc_get_uart_ctrlr_info(size_t *num_ctrlrs)
+{
+ *num_ctrlrs = ARRAY_SIZE(uart_info);
+ return uart_info;
+}
+
+void clear_uart_legacy_config(void)
+{
+ write16((void *)FCH_LEGACY_UART_DECODE, 0);
+}