| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright 2015 Google Inc |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include <memlayout.h> |
| #include <arch/header.ld> |
| |
| SECTIONS |
| { |
| /* |
| * It would be good to lay down RAMSTAGE, ROMSTAGE, etc consecutively |
| * like other architectures/chipsets it's not possible because of |
| * the linking games played during romstage creation by trying |
| * to find the final landing place in CBFS for XIP. Therefore, |
| * conditionalize with macros. |
| */ |
| #if ENV_RAMSTAGE |
| RAMSTAGE(CONFIG_RAMBASE, CONFIG_RAMTOP - CONFIG_RAMBASE) |
| |
| #elif ENV_ROMSTAGE |
| /* The 1M size is not allocated. It's just for basic size checking. |
| * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ |
| ROMSTAGE(32M, 1M) |
| |
| /* Pull in the cache-as-ram rules. */ |
| #include "car.ld" |
| #elif ENV_VERSTAGE |
| /* The 1M size is not allocated. It's just for basic size checking. |
| * Link at 32MiB address and rely on cbfstool to relocate to XIP. */ |
| VERSTAGE(32M, 1M) |
| |
| /* Pull in the cache-as-ram rules. */ |
| #include "car.ld" |
| #endif |
| } |