commit 950d48fe6bee3b3d39f4b2e610489f56fc7fd6c7
author Jonathan Neuschäfer <j.neuschaefer@gmx.net> Wed Oct 12 00:18:00 2016 +0200
committer Ronald G. Minnich <rminnich@gmail.com> Sat Oct 15 00:34:51 2016 +0200
tree 47aaf5fc596c016e9b3cae149059ad10384a45da
parent 3401f5a20c6918adbe97b7e9df7d5bf25583163f

MAINTAINERS/RISCV: Cover mb/emulation/spike-riscv

Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16988
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

MAINTAINERS

diff --git a/MAINTAINERS b/MAINTAINERS
index 750fcff..16cdc4b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -124,7 +124,7 @@
 S:	Maintained
 F:	src/arch/riscv/
 F:	src/soc/ucb/
-F:	src/mainboard/emulation/qemu-riscv/
+F:	src/mainboard/emulation/*-riscv/
 
 POWER8 ARCHITECTURE
 M:	Ronald Minnich <rminnich@gmail.com>