src/southbridge/intel/i82801gx/early_init.c

/*
 * This file is part of the coreboot project.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; version 2 of the License.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <stdint.h>
#include <device/pci_ops.h>
#include "i82801gx.h"
#include "chip.h"

void i82801gx_lpc_setup(void)
{
	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
	const struct device *dev = pcidev_on_root(0x1f, 0);
	const struct southbridge_intel_i82801gx_config *config;

	/* Configure serial IRQs.*/
	pci_write_config8(d31f0, SERIRQ_CNTL, 0xd0);
	/*
	 * Enable some common LPC IO ranges:
	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
	 * - 0x3f0-0x3f5/0x3f7 FDD
	 * - 0x378-0x37f and 0x778-0x77f LPT
	 * - 0x2f8-0x2ff COMB
	 * - 0x3f8-0x3ff COMA
	 * - 0x208-0x20f GAMEH
	 * - 0x200-0x207 GAMEL
	 */
	pci_write_config16(d31f0, LPC_IO_DEC, 0x0010);
	pci_write_config16(d31f0, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN
			   | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN
			   | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
			   | COMB_LPC_EN | COMA_LPC_EN);

	/* Set up generic decode ranges */
	if (!dev || !dev->chip_info)
		return;
	config = dev->chip_info;

	pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
	pci_write_config32(d31f0, GEN2_DEC, config->gen2_dec);
	pci_write_config32(d31f0, GEN3_DEC, config->gen3_dec);
	pci_write_config32(d31f0, GEN4_DEC, config->gen4_dec);
}

void i82801gx_setup_bars(void)
{
	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
	pci_write_config32(d31f0, RCBA, (uint32_t)DEFAULT_RCBA | 1);
	pci_write_config32(d31f0, PMBASE, DEFAULT_PMBASE | 1);
	pci_write_config8(d31f0, ACPI_CNTL, ACPI_EN);

	pci_write_config32(d31f0, GPIOBASE, DEFAULT_GPIOBASE | 1);
	pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
}