| # |
| # This file is part of the coreboot project. |
| # |
| # Copyright (C) 2011 Advanced Micro Devices, Inc. |
| # |
| # This program is free software; you can redistribute it and/or modify |
| # it under the terms of the GNU General Public License as published by |
| # the Free Software Foundation; version 2 of the License. |
| # |
| # This program is distributed in the hope that it will be useful, |
| # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| # GNU General Public License for more details. |
| # |
| # You should have received a copy of the GNU General Public License |
| # along with this program; if not, write to the Free Software |
| # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| # |
| chip northbridge/amd/agesa_wrapper/family14/root_complex |
| device lapic_cluster 0 on |
| chip cpu/amd/agesa_wrapper/family14 |
| device lapic 0 on end |
| end |
| end |
| device pci_domain 0 on |
| subsystemid 0x1022 0x1510 inherit |
| chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex |
| # device pci 18.0 on # northbridge |
| chip northbridge/amd/agesa_wrapper/family14 # PCI side of HT root complex |
| device pci 0.0 on end # Root Complex |
| device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 |
| device pci 1.1 on end # Internal Multimedia |
| device pci 4.0 on end # PCIE P2P bridge 0x9604 |
| device pci 5.0 off end # PCIE P2P bridge 0x9605 |
| device pci 6.0 off end # PCIE P2P bridge 0x9606 |
| device pci 7.0 off end # PCIE P2P bridge 0x9607 |
| device pci 8.0 off end # NB/SB Link P2P bridge |
| end # agesa_wrapper northbridge |
| |
| chip southbridge/amd/cimx_wrapper/sb800 # it is under NB/SB Link, but on the same pri bus |
| device pci 11.0 on end # SATA |
| device pci 12.0 on end # USB |
| device pci 12.1 on end # USB |
| device pci 12.2 on end # USB |
| device pci 13.0 on end # USB |
| device pci 13.1 on end # USB |
| device pci 13.2 on end # USB |
| device pci 14.0 on # SM |
| chip drivers/generic/generic #dimm 0-0-0 |
| device i2c 50 on end |
| end |
| chip drivers/generic/generic #dimm 0-0-1 |
| device i2c 51 on end |
| end |
| end # SM |
| device pci 14.1 on end # IDE 0x439c |
| device pci 14.2 on end # HDA 0x4383 |
| device pci 14.3 on # LPC 0x439d |
| chip superio/fintek/f81865f |
| device pnp 4e.0 off # Floppy |
| io 0x60 = 0x3f0 |
| irq 0x70 = 6 |
| drq 0x74 = 2 |
| end |
| device pnp 4e.3 off end # Parallel Port |
| device pnp 4e.4 off end # Hardware Monitor |
| device pnp 4e.5 on # Keyboard |
| io 0x60 = 0x60 |
| io 0x62 = 0x64 |
| irq 0x70 = 1 |
| end |
| device pnp 4e.6 off end # GPIO |
| device pnp 4e.a off end # PME |
| device pnp 4e.10 on # COM1 |
| io 0x60 = 0x3f8 |
| irq 0x70 = 4 |
| end |
| device pnp 4e.11 off # COM2 |
| io 0x60 = 0x2f8 |
| irq 0x70 = 3 |
| end |
| end # f81865f |
| end #LPC |
| device pci 14.4 on end # PCI 0x4384 |
| device pci 14.5 on end # USB 2 |
| device pci 15.0 on end # PCIe PortA |
| device pci 15.1 on end # PCIe PortB |
| device pci 15.2 on end # PCIe PortC |
| device pci 15.3 on end # PCIe PortD |
| register "gpp_configuration" = "4" #1:1:1:1 |
| register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE |
| end #southbridge/amd/cimx_wrapper/sb800 |
| # end # device pci 18.0 |
| # These seem unnecessary |
| device pci 18.0 on end |
| #device pci 18.0 on end |
| device pci 18.1 on end |
| device pci 18.2 on end |
| device pci 18.3 on end |
| device pci 18.4 on end |
| device pci 18.5 on end |
| device pci 18.6 on end |
| device pci 18.7 on end |
| end #chip northbridge/amd/agesa_wrapper/family14 # CPU side of HT root complex |
| end #pci_domain |
| end #northbridge/amd/agesa_wrapper/family14/root_complex |
| |