soc/intel: Replace uses of dev_find_slot()
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 6208c9c..cec706f 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -186,7 +186,7 @@
static unsigned long soc_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -219,7 +219,7 @@
* get the info and hide it again when done.
*/
p2sb_unhide();
- struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+ struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF);
uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF);
p2sb_hide();
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index e9030dc..1d5e6d9 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -256,7 +256,7 @@
int i;
unsigned int inc = PCI_DEVFN(0, 1);
- func0 = dev_find_slot(0, devfn0);
+ func0 = pcidev_path_on_root(devfn0);
if (func0 == NULL)
return;
@@ -272,7 +272,7 @@
* as that port was move to func0.
*/
for (i = 1; i < num_funcs; i++, devfn += inc) {
- struct device *dev = dev_find_slot(0, devfn);
+ struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL)
continue;
@@ -760,7 +760,7 @@
apl_fsp_silicon_init_params_cb(cfg, silconfig);
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_XDCI);
+ dev = pcidev_path_on_root(PCH_DEVFN_XDCI);
if (!xdci_can_enable())
dev->enabled = 0;
silconfig->UsbOtg = dev->enabled;
diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h
index 335a485..a334f63 100644
--- a/src/soc/intel/apollolake/include/soc/pci_devs.h
+++ b/src/soc/intel/apollolake/include/soc/pci_devs.h
@@ -22,8 +22,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c
index 6058e34..3436364 100644
--- a/src/soc/intel/apollolake/memmap.c
+++ b/src/soc/intel/apollolake/memmap.c
@@ -35,7 +35,7 @@
if (!CONFIG(SOC_INTEL_GLK))
return tolum;
- dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ dev = pcidev_path_on_root(PCH_DEVFN_LPC);
assert(dev != NULL);
config = dev->chip_info;
diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c
index 22f5309..1bf3202 100644
--- a/src/soc/intel/apollolake/pmutil.c
+++ b/src/soc/intel/apollolake/pmutil.c
@@ -149,7 +149,7 @@
DEVTREE_CONST struct soc_intel_apollolake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c
index 5d65a00..72a566a 100644
--- a/src/soc/intel/apollolake/romstage.c
+++ b/src/soc/intel/apollolake/romstage.c
@@ -100,7 +100,7 @@
/* Thermal throttle activation offset */
static void configure_thermal_target(void)
{
- const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+ const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev) {
printk(BIOS_ERR, "Could not find SOC devicetree config\n");
return;
@@ -320,7 +320,7 @@
{
#if CONFIG(SOC_INTEL_GLK)
/* Only for GLK */
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -350,7 +350,7 @@
static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
#if CONFIG(SOC_INTEL_GLK)
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
if (!dev)
return;
diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index e51c9bf..25867c5 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -580,7 +580,7 @@
static unsigned long acpi_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;
diff --git a/src/soc/intel/broadwell/include/soc/pci_devs.h b/src/soc/intel/broadwell/include/soc/pci_devs.h
index 03456ca..522e3eb 100644
--- a/src/soc/intel/broadwell/include/soc/pci_devs.h
+++ b/src/soc/intel/broadwell/include/soc/pci_devs.h
@@ -25,8 +25,8 @@
#else
#include <device/device.h>
#include <device/pci_def.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#endif
/* System Agent Devices */
diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c
index ef97a1e..ea2726b 100644
--- a/src/soc/intel/broadwell/romstage/pch.c
+++ b/src/soc/intel/broadwell/romstage/pch.c
@@ -79,7 +79,7 @@
const struct device *dev;
const config_t *config;
- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
if (!dev || !dev->chip_info)
return;
config = dev->chip_info;
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index ff9da45..26c2847 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -293,7 +293,7 @@
static unsigned long soc_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -306,7 +306,7 @@
acpi_dmar_drhd_fixup(tmp, current);
}
- struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
+ struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 783ebb7..a58a97c 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -51,7 +51,7 @@
{
struct device *dev;
- dev = dev_find_slot(0, serial_io_dev[dev_offset]);
+ dev = pcidev_path_on_root(serial_io_dev[dev_offset]);
if (!dev || !dev->enabled)
return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled);
@@ -178,7 +178,7 @@
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
- dev = dev_find_slot(0, PCH_DEVFN_SATA);
+ dev = pcidev_path_on_root(PCH_DEVFN_SATA);
if (!dev)
params->SataEnable = 0;
else {
@@ -192,7 +192,7 @@
}
/* Lan */
- dev = dev_find_slot(0, PCH_DEVFN_GBE);
+ dev = pcidev_path_on_root(PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else {
@@ -275,7 +275,7 @@
}
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {
if (!xdci_can_enable())
dev->enabled = 0;
@@ -287,7 +287,7 @@
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
/* Enable CNVi Wifi if enabled in device tree */
- dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
+ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);
#if CONFIG(SOC_INTEL_COMETLAKE)
if (dev)
params->CnviMode = dev->enabled;
@@ -314,7 +314,7 @@
sizeof(config->PcieRpHotPlug));
/* eMMC and SD */
- dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+ dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
@@ -329,7 +329,7 @@
}
}
- dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
if (!dev) {
params->ScsSdCardEnabled = 0;
} else {
@@ -338,7 +338,7 @@
CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
}
- dev = dev_find_slot(0, PCH_DEVFN_UFS);
+ dev = pcidev_path_on_root(PCH_DEVFN_UFS);
if (!dev)
params->ScsUfsEnabled = 0;
else
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 2c932da..46bc1bf 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -24,8 +24,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 3cae54f..355c36b 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -219,7 +219,7 @@
uintptr_t dram_base;
const struct device *dev;
- dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+ dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0);
if (!dev)
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - IGD device not found!");
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index ab36c70..9997d16 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -177,7 +177,7 @@
DEVTREE_CONST struct soc_intel_cannonlake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index a1e3d76..eb71f5d 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -30,7 +30,7 @@
{
unsigned int i;
uint32_t mask = 0;
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
/* Set IGD stolen size to 64MB. */
m_cfg->IgdDvmt50PreAlloc = 2;
@@ -85,7 +85,7 @@
m_cfg->PchIshEnable = dev->enabled;
/* If HDA is enabled, enable HDA elements */
- dev = dev_find_slot(0, PCH_DEVFN_HDA);
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
if (!dev)
m_cfg->PchHdaEnable = 0;
else
@@ -100,8 +100,8 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
- const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+ const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index e8f0d17..cc5a7dd 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -78,7 +78,7 @@
void smihandler_soc_at_finalize(void)
{
const struct soc_intel_cannonlake_config *config;
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
diff --git a/src/soc/intel/denverton_ns/include/soc/pci_devs.h b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
index b902097..303ba67 100644
--- a/src/soc/intel/denverton_ns/include/soc/pci_devs.h
+++ b/src/soc/intel/denverton_ns/include/soc/pci_devs.h
@@ -27,8 +27,8 @@
#if ENV_RAMSTAGE
#include <device/device.h>
#include <device/pci_def.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func)
diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c
index ba7ba0f..ef95f7e 100644
--- a/src/soc/intel/denverton_ns/soc_util.c
+++ b/src/soc/intel/denverton_ns/soc_util.c
@@ -37,7 +37,7 @@
#else
struct device *get_hostbridge_dev(void)
{
- return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));
+ return pcidev_on_root(SA_DEV, SA_FUNC);
}
#endif
@@ -49,7 +49,7 @@
#else
struct device *get_lpc_dev(void)
{
- return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+ return pcidev_on_root(LPC_DEV, LPC_FUNC);
}
#endif
@@ -61,7 +61,7 @@
#else
struct device *get_pmc_dev(void)
{
- return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));
+ return pcidev_on_root(PMC_DEV, PMC_FUNC);
}
#endif
@@ -73,7 +73,7 @@
#else
struct device *get_smbus_dev(void)
{
- return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
+ return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
}
#endif
diff --git a/src/soc/intel/denverton_ns/uart.c b/src/soc/intel/denverton_ns/uart.c
index 07e0704..50f8a29 100644
--- a/src/soc/intel/denverton_ns/uart.c
+++ b/src/soc/intel/denverton_ns/uart.c
@@ -76,7 +76,7 @@
last one. */
for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) {
struct device *uart_dev;
- uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i));
+ uart_dev = pcidev_on_root(HSUART_DEV, i);
if (uart_dev == NULL)
continue;
pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1);
diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h
index 889b5c5..b242113 100644
--- a/src/soc/intel/icelake/include/soc/pci_devs.h
+++ b/src/soc/intel/icelake/include/soc/pci_devs.h
@@ -23,8 +23,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index f446708..49af604 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -218,7 +218,7 @@
uintptr_t dram_base;
const struct device *dev;
- dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+ dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0);
if (!dev)
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - IGD device not found!");
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c
index cdb39ad..0edec4b 100644
--- a/src/soc/intel/icelake/pmutil.c
+++ b/src/soc/intel/icelake/pmutil.c
@@ -176,7 +176,7 @@
DEVTREE_CONST struct soc_intel_icelake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index 5fb2480..a7ea094 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -76,7 +76,7 @@
void smihandler_soc_at_finalize(void)
{
const struct soc_intel_icelake_config *config;
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c
index bd944da..910db97 100644
--- a/src/soc/intel/skylake/acpi.c
+++ b/src/soc/intel/skylake/acpi.c
@@ -174,7 +174,7 @@
static void acpi_create_gnvs(global_nvs_t *gnvs)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
/* Set unknown wake source */
@@ -561,7 +561,7 @@
static unsigned long acpi_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
@@ -584,7 +584,7 @@
acpi_dmar_rmrr_fixup(tmp, current);
}
- struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+ struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
@@ -695,7 +695,7 @@
/* Save wake source information for calculating ACPI _SWS values */
int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
struct chipset_power_state *ps;
static uint32_t gpe0_sts[GPE0_REG_MAX];
diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 6f90178..7f28340 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -92,7 +92,7 @@
/* UPD parameters to be initialized before SiliconInit */
void soc_silicon_init_params(SILICON_INIT_UPD *params)
{
- struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
int i;
@@ -152,7 +152,7 @@
params->ScsSdCardEnabled = config->ScsSdCardEnabled;
/* Enable ISH if device is on */
- dev = dev_find_slot(0, PCH_DEVFN_ISH);
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev)
params->IshEnable = dev->enabled;
else
@@ -219,11 +219,11 @@
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Show SPI controller if enabled in devicetree.cb */
- dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index d179598..08f5d79 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -102,7 +102,7 @@
for (group = 0; group < pci_groups; group++) {
devfn0 = pcie_rp_group[group].devfn;
- func0 = dev_find_slot(0, devfn0);
+ func0 = pcidev_path_on_root(devfn0);
if (func0 == NULL)
continue;
@@ -119,7 +119,7 @@
*/
for (i = 1; i < pcie_rp_group[group].func_count;
i++, devfn += inc) {
- struct device *dev = dev_find_slot(0, devfn);
+ struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL || !dev->enabled)
continue;
@@ -354,7 +354,7 @@
}
/* If ISH is enabled, enable ISH elements */
- dev = dev_find_slot(0, PCH_DEVFN_ISH);
+ dev = pcidev_path_on_root(PCH_DEVFN_ISH);
if (dev)
params->PchIshEnable = dev->enabled;
else
@@ -433,11 +433,11 @@
fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
/* Show SPI controller if enabled in devicetree.cb */
- dev = dev_find_slot(0, PCH_DEVFN_SPI);
+ dev = pcidev_path_on_root(PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled;
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (!xdci_can_enable())
dev->enabled = 0;
params->XdciEnable = dev->enabled;
diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h
index d59c800..5acaaebc 100644
--- a/src/soc/intel/skylake/include/soc/pci_devs.h
+++ b/src/soc/intel/skylake/include/soc/pci_devs.h
@@ -24,8 +24,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
@@ -39,7 +39,7 @@
#define SA_DEV_SLOT_PEG 0x01
#define SA_DEVFN_PEG(func) PCI_DEVFN(SA_DEV_SLOT_PEG, func)
-#define SA_DEV_PEG(func) dev_find_slot(0, SA_DEVFN_PEG(func))
+#define SA_DEV_PEG(func) pcidev_path_on_root(SA_DEVFN_PEG(func))
#define SA_DEV_PEG0 SA_DEV_PEG(0)
#define SA_DEV_PEG1 SA_DEV_PEG(1)
#define SA_DEV_PEG2 SA_DEV_PEG(2)
diff --git a/src/soc/intel/skylake/irq.c b/src/soc/intel/skylake/irq.c
index d10ca74..03cdb07 100644
--- a/src/soc/intel/skylake/irq.c
+++ b/src/soc/intel/skylake/irq.c
@@ -223,7 +223,7 @@
uint32_t i, intdeventry;
u8 irq_config[PCH_MAX_IRQ_CONFIG];
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
const struct soc_intel_skylake_config *config = dev->chip_info;
/* Get Device Int Count */
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 7d0dc0a..9732aa1 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -178,7 +178,7 @@
DEVTREE_CONST struct soc_intel_skylake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 29c4774..2bbab47 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -57,7 +57,7 @@
const struct soc_intel_skylake_config *config;
/* Set the parameters for MemoryInit */
- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
config = dev->chip_info;
/*
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c
index fafa343..6884a32 100644
--- a/src/soc/intel/skylake/romstage/romstage_fsp20.c
+++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c
@@ -301,7 +301,7 @@
{
const struct device *dev;
- dev = dev_find_slot(0, SA_DEVFN_IGD);
+ dev = pcidev_path_on_root(SA_DEVFN_IGD);
if (!dev || !dev->enabled) {
/*
* If iGPU is disabled or not defined in the devicetree.cb,
@@ -331,7 +331,7 @@
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
- dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+ dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
config = dev->chip_info;
soc_memory_init_params(m_cfg, config);
diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index 71a9bee..00f620f 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -26,8 +26,8 @@
static void systemagent_vtd_init(void)
{
- const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT);
- const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
const struct soc_intel_skylake_config *config = NULL;
if (root_dev)