soc/intel: Replace uses of dev_find_slot()
To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.
Replace this with method that relies on bus topology
that walks the root bus only.
Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/src/soc/intel/cannonlake/acpi.c b/src/soc/intel/cannonlake/acpi.c
index ff9da45..26c2847 100644
--- a/src/soc/intel/cannonlake/acpi.c
+++ b/src/soc/intel/cannonlake/acpi.c
@@ -293,7 +293,7 @@
static unsigned long soc_fill_dmar(unsigned long current)
{
- struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+ struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -306,7 +306,7 @@
acpi_dmar_drhd_fixup(tmp, current);
}
- struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
+ struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 783ebb7..a58a97c 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -51,7 +51,7 @@
{
struct device *dev;
- dev = dev_find_slot(0, serial_io_dev[dev_offset]);
+ dev = pcidev_path_on_root(serial_io_dev[dev_offset]);
if (!dev || !dev->enabled)
return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled);
@@ -178,7 +178,7 @@
params->PchLockDownRtcMemoryLock = 0;
/* SATA */
- dev = dev_find_slot(0, PCH_DEVFN_SATA);
+ dev = pcidev_path_on_root(PCH_DEVFN_SATA);
if (!dev)
params->SataEnable = 0;
else {
@@ -192,7 +192,7 @@
}
/* Lan */
- dev = dev_find_slot(0, PCH_DEVFN_GBE);
+ dev = pcidev_path_on_root(PCH_DEVFN_GBE);
if (!dev)
params->PchLanEnable = 0;
else {
@@ -275,7 +275,7 @@
}
/* Enable xDCI controller if enabled in devicetree and allowed */
- dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
if (dev) {
if (!xdci_can_enable())
dev->enabled = 0;
@@ -287,7 +287,7 @@
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
/* Enable CNVi Wifi if enabled in device tree */
- dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
+ dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);
#if CONFIG(SOC_INTEL_COMETLAKE)
if (dev)
params->CnviMode = dev->enabled;
@@ -314,7 +314,7 @@
sizeof(config->PcieRpHotPlug));
/* eMMC and SD */
- dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+ dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
if (!dev)
params->ScsEmmcEnabled = 0;
else {
@@ -329,7 +329,7 @@
}
}
- dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
if (!dev) {
params->ScsSdCardEnabled = 0;
} else {
@@ -338,7 +338,7 @@
CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
}
- dev = dev_find_slot(0, PCH_DEVFN_UFS);
+ dev = pcidev_path_on_root(PCH_DEVFN_UFS);
if (!dev)
params->ScsUfsEnabled = 0;
else
diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h
index 2c932da..46bc1bf 100644
--- a/src/soc/intel/cannonlake/include/soc/pci_devs.h
+++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h
@@ -24,8 +24,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
diff --git a/src/soc/intel/cannonlake/memmap.c b/src/soc/intel/cannonlake/memmap.c
index 3cae54f..355c36b 100644
--- a/src/soc/intel/cannonlake/memmap.c
+++ b/src/soc/intel/cannonlake/memmap.c
@@ -219,7 +219,7 @@
uintptr_t dram_base;
const struct device *dev;
- dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+ dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0);
if (!dev)
die_with_post_code(POST_HW_INIT_FAILURE,
"ERROR - IGD device not found!");
diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c
index ab36c70..9997d16 100644
--- a/src/soc/intel/cannonlake/pmutil.c
+++ b/src/soc/intel/cannonlake/pmutil.c
@@ -177,7 +177,7 @@
DEVTREE_CONST struct soc_intel_cannonlake_config *config;
/* Look up the device in devicetree */
- DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+ DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index a1e3d76..eb71f5d 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -30,7 +30,7 @@
{
unsigned int i;
uint32_t mask = 0;
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
/* Set IGD stolen size to 64MB. */
m_cfg->IgdDvmt50PreAlloc = 2;
@@ -85,7 +85,7 @@
m_cfg->PchIshEnable = dev->enabled;
/* If HDA is enabled, enable HDA elements */
- dev = dev_find_slot(0, PCH_DEVFN_HDA);
+ dev = pcidev_path_on_root(PCH_DEVFN_HDA);
if (!dev)
m_cfg->PchHdaEnable = 0;
else
@@ -100,8 +100,8 @@
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
{
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
- const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
+ const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
diff --git a/src/soc/intel/cannonlake/smihandler.c b/src/soc/intel/cannonlake/smihandler.c
index e8f0d17..cc5a7dd 100644
--- a/src/soc/intel/cannonlake/smihandler.c
+++ b/src/soc/intel/cannonlake/smihandler.c
@@ -78,7 +78,7 @@
void smihandler_soc_at_finalize(void)
{
const struct soc_intel_cannonlake_config *config;
- const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
+ const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",