soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
srcclk_pin is 0-based and '0' is a valid clock source number. If
srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.
BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI entries are generated as
expected. For those PCI devices with RTD3 driver whose srcclk_pin to
0, the RTD3 entries should not be missing due to check error.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
index 8b372ed..82336d9 100644
--- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c
+++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c
@@ -419,9 +419,10 @@
return;
}
}
- if (config->srcclk_pin == 0) {
+ if (config->srcclk_pin == -1) {
if (config->ext_pm_support & ACPI_PCIE_RP_EMIT_SRCK) {
- printk(BIOS_ERR, "%s: Can not export SRCK method\n", __func__);
+ printk(BIOS_ERR, "%s: Can not export SRCK method since clock source gating is not enabled\n",
+ __func__);
return;
}
}