| chip soc/intel/alderlake |
| register "power_limits_config[ADL_P_142_242_282_15W_CORE]" = "{ |
| .tdp_pl1_override = 15, |
| .tdp_pl2_override = 46, |
| .tdp_pl4 = 65, |
| }" |
| |
| # GPE configuration |
| register "pmc_gpe0_dw0" = "PMC_GPP_A" |
| register "pmc_gpe0_dw1" = "PMC_GPP_R" |
| register "pmc_gpe0_dw2" = "PMC_GPD" |
| |
| device domain 0 on |
| subsystemid 0x1558 0x7718 inherit |
| |
| device ref pcie4_0 on |
| # PCIe PEG0 x4, Clock 0 (SSD2) |
| register "cpu_pcie_rp[CPU_RP(1)]" = "{ |
| .clk_src = 0, |
| .clk_req = 0, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# |
| register "srcclk_pin" = "0" # SSD0_CLKREQ# |
| device generic 0 on end |
| end |
| end |
| device ref tcss_xhci on |
| register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" |
| chip drivers/usb/acpi |
| device ref tcss_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""TBT Type-C"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| device ref tcss_usb3_port1 on end |
| end |
| end |
| end |
| end |
| device ref xhci on |
| # USB2 |
| register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Left |
| register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Right |
| register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 |
| register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # 3G/LTE |
| register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera |
| register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth |
| # USB3 |
| register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Left |
| register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Right |
| register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 3G/LTE |
| # ACPI |
| chip drivers/usb/acpi |
| device ref xhci_root_hub on |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Left"" |
| register "type" = "UPC_TYPE_A" |
| device ref usb2_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-A Right"" |
| register "type" = "UPC_TYPE_A" |
| device ref usb2_port2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Type-C"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| device ref usb2_port3 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 3G/LTE"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port4 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Camera"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port7 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB2 Bluetooth"" |
| register "type" = "UPC_TYPE_INTERNAL" |
| device ref usb2_port10 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Left"" |
| register "type" = "UPC_TYPE_A" |
| device ref usb3_port1 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-A Right"" |
| register "type" = "UPC_TYPE_A" |
| device ref usb3_port2 on end |
| end |
| chip drivers/usb/acpi |
| register "desc" = ""USB3 Type-C"" |
| register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" |
| device ref usb3_port3 on end |
| end |
| end |
| end |
| end |
| device ref tcss_dma0 on |
| chip drivers/intel/usb4/retimer |
| register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" |
| use tcss_usb3_port1 as dfp[0].typec_port |
| device generic 0 on end |
| end |
| end |
| device ref pcie_rp5 on |
| # PCIe RP#5 x1, Clock 2 (WLAN) |
| register "pch_pcie_rp[PCH_RP(5)]" = "{ |
| .clk_src = 2, |
| .clk_req = 2, |
| .flags = PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A13)" # PCH_BT_EN |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)" # WLAN_RST# |
| register "srcclk_pin" = "2" # WLAN_CLKREQ# |
| device generic 0 on end |
| end |
| end |
| device ref pcie_rp6 on |
| # PCIe RP#6 x1, Clock 6 (CARD) |
| register "pch_pcie_rp[PCH_RP(6)]" = "{ |
| .clk_src = 6, |
| .clk_req = 6, |
| .flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER, |
| }" |
| end |
| device ref pcie_rp9 on |
| # PCIe RP#9 x4, Clock 1 (SSD1) |
| register "pch_pcie_rp[PCH_RP(9)]" = "{ |
| .clk_src = 1, |
| .clk_req = 1, |
| .flags = PCIE_RP_LTR, |
| }" |
| chip soc/intel/common/block/pcie/rtd3 |
| register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN |
| register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # M2_SSD1_RST# |
| register "srcclk_pin" = "1" # SSD1_CLKREQ# |
| device generic 0 on end |
| end |
| end |
| device ref pmc hidden |
| chip drivers/intel/pmc_mux |
| device generic 0 on |
| chip drivers/intel/pmc_mux/conn |
| # J_TYPEC1 |
| use usb2_port3 as usb2_port |
| use tcss_usb3_port1 as usb3_port |
| device generic 0 alias conn0 on end |
| end |
| end |
| end |
| end |
| end |
| end |