Gitiles
Code Review
Sign In
review.coreboot.org
/
coreboot
/
8e3787eaf01f84b449cca3d37ec584ad77228b86
/
.
/
src
/
mainboard
/
system76
/
tgl-h
/
variants
/
oryp8
/
romstage.c
blob: 85606d0d05f20b8ec5eb91b9ce42cb3352796851 [
file
] [
log
] [
blame
]
/* SPDX-License-Identifier: GPL-2.0-only */
#include
<variant/romstage.h>
void
variant_memory_init_params
(
FSPM_UPD
*
mupd
)
{
// Enable M.2 PCIE 4.0 and PEG1
mupd
->
FspmConfig
.
CpuPcieRpEnableMask
=
0x3
;
}