| commit | 8bcd8210ea64bdbb35485d361e645f2c9cfcf763 | [log] [tgz] |
|---|---|---|
| author | Elyes Haouas <ehaouas@noos.fr> | Mon May 06 11:48:41 2024 +0200 |
| committer | Elyes Haouas <ehaouas@noos.fr> | Tue May 07 10:53:31 2024 +0000 |
| tree | 7f36324e0d9e90e03f239974c7ae99220616c6d7 | |
| parent | 0f45e17f564a657ddf9804124e4e30da0edb1d13 [diff] [blame] |
dram/ddr3: Use the same naming convention as DDR4 Change-Id: Ifaff19c0117b5247d3321605ccc2e97bf8226ca8 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82216 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 2a4eae5..8a8bd83 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -142,7 +142,7 @@ { int j; if (id_only) { - for (j = SPD_DIMM_MOD_ID1; j < 128; j++) + for (j = SPD_DDR3_MOD_ID1; j < 128; j++) (*spd)[j] = smbus_read_byte(addr, j); } else { for (j = 0; j < SPD_SIZE_MAX_DDR3; j++)