commit 8b76605a4af9b45894c39cd7b9c480bd96f523cd
author Arthur Heymans <arthur@aheymans.xyz> Wed Jan 24 23:25:13 2018 +0100
committer Patrick Georgi <pgeorgi@google.com> Wed Mar 28 06:49:19 2018 +0000
tree 4d24a5aa80b7e6e1b19ef62868fc442aa1a8c128
parent a050817ce57ef960bf2bec3a18f23b59039dd184

nb/intel/gm45: Allocate a 8M TSEG region

Tested on Thinkpad X200.

Change-Id: I9db7a71608aaec956a7b22649498b97d58f35265
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23418
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/gm45/gm45.h

diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 34f734c..df9c449 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -433,6 +433,7 @@
 
 u32 decode_igd_memory_size(u32 gms);
 u32 decode_igd_gtt_size(u32 gsm);
+u32 decode_tseg_size(u8 esmramc);
 
 void init_iommu(void);
 

src/northbridge/intel/gm45/northbridge.c

diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c
index 8215979..4927e53 100644
--- a/src/northbridge/intel/gm45/northbridge.c
+++ b/src/northbridge/intel/gm45/northbridge.c
@@ -119,16 +119,21 @@
 
 		/* Graphics memory */
 		const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf);
-		printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10);
+		printk(BIOS_DEBUG, "%uM UMA, ", gms_sizek >> 10);
 		tomk -= gms_sizek;
 
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
-		printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
+		printk(BIOS_DEBUG, "%uM GTT", gsm_sizek >> 10);
 		tomk -= gsm_sizek;
 
 		uma_sizek = gms_sizek + gsm_sizek;
 	}
+	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
+	const u32 tseg_sizek = decode_tseg_size(esmramc);
+	printk(BIOS_DEBUG, " and %uM TSEG\n", tseg_sizek >> 10);
+	tomk -= tseg_sizek;
+	uma_sizek += tseg_sizek;
 
 	printk(BIOS_INFO, "Available memory below 4GB: %uM\n", tomk >> 10);
 

src/northbridge/intel/gm45/ram_calc.c

diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c
index 780bed4..1e434c7 100644
--- a/src/northbridge/intel/gm45/ram_calc.c
+++ b/src/northbridge/intel/gm45/ram_calc.c
@@ -65,6 +65,24 @@
 	}
 }
 
+/* Decodes TSEG region size to kilobytes. */
+u32 decode_tseg_size(u8 esmramc)
+{
+	if (!(esmramc & 1))
+		return 0;
+	switch ((esmramc >> 1) & 3) {
+	case 0:
+		return 1 << 10;
+	case 1:
+		return 2 << 10;
+	case 2:
+		return 8 << 10;
+	case 3:
+	default:
+		die("Bad TSEG setting.\n");
+	}
+}
+
 static uintptr_t smm_region_start(void)
 {
 	const pci_devfn_t dev = PCI_DEV(0, 0, 0);
@@ -76,12 +94,15 @@
 
 	/* Graphics memory comes next */
 	const u32 ggc = pci_read_config16(dev, D0F0_GGC);
+	const u8 esmramc = pci_read_config8(dev, D0F0_ESMRAMC);
 	if (!(ggc & 2)) {
 		/* Graphics memory */
 		tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10;
 		/* GTT Graphics Stolen Memory Size (GGMS) */
 		tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10;
 	}
+	/* TSEG size */
+	tor -= decode_tseg_size(esmramc) << 10;
 	return tor;
 }
 

src/northbridge/intel/gm45/raminit.c

diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index a44e397..af5faf0c 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1242,6 +1242,12 @@
 
 			uma_sizem = (gms_sizek + gsm_sizek) >> 10;
 		}
+		/* TSEG 8M */
+		u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC);
+		reg8 &= ~0x7;
+		reg8 |= (2 << 1) | (1 << 0); /* 8M and TSEG_Enable */
+		pci_write_config8(PCI_DEV(0, 0, 0), D0F0_ESMRAMC, reg8);
+		uma_sizem += 8;
 	}
 
 	const unsigned int mmio_size = get_mmio_size();