| |
| config CPU_INTEL_HASWELL |
| bool |
| |
| if CPU_INTEL_HASWELL |
| |
| config CPU_SPECIFIC_OPTIONS |
| def_bool y |
| select ARCH_BOOTBLOCK_X86_32 |
| select ARCH_VERSTAGE_X86_32 |
| select ARCH_ROMSTAGE_X86_32 |
| select ARCH_RAMSTAGE_X86_32 |
| select HAVE_MONOTONIC_TIMER |
| select SMP |
| select MMX |
| select SSE2 |
| select UDELAY_TSC |
| select TSC_CONSTANT_RATE |
| select SUPPORT_CPU_UCODE_IN_CBFS |
| #select AP_IN_SIPI_WAIT |
| select TSC_SYNC_MFENCE |
| select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
| select PARALLEL_MP |
| select CPU_INTEL_COMMON |
| select NO_FIXED_XIP_ROM_SIZE |
| |
| config SMM_TSEG_SIZE |
| hex |
| default 0x800000 |
| |
| config IED_REGION_SIZE |
| hex |
| default 0x400000 |
| |
| config SMM_RESERVED_SIZE |
| hex |
| default 0x100000 |
| |
| config RESET_ON_INVALID_RAMSTAGE_CACHE |
| bool "Reset the system on S3 wake when ramstage cache invalid." |
| default n |
| help |
| The haswell romstage code caches the loaded ramstage program |
| in SMM space. On S3 wake the romstage will copy over a fresh |
| ramstage that was cached in the SMM space. This option determines |
| the action to take when the ramstage cache is invalid. If selected |
| the system will reset otherwise the ramstage will be reloaded from |
| cbfs. |
| |
| endif |